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FEB_1315 30.01.25 08:55:49
Info
08:55:49:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
08:55:49:ST3_Shared:INFO: FEB-Sensor
08:55:49:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
08:55:54:ST3_ModuleSelector:DEBUG: M4UR3T0011310A2
08:55:54:ST3_ModuleSelector:DEBUG: L4UR301131
08:55:54:ST3_ModuleSelector:DEBUG: 08362
08:55:54:ST3_ModuleSelector:DEBUG: 62x42
08:55:54:ST3_ModuleSelector:DEBUG: A
08:55:54:ST3_ModuleSelector:DEBUG: M4UR3T0011310A2
08:55:54:ST3_ModuleSelector:DEBUG: L4UR301131
08:55:54:ST3_ModuleSelector:DEBUG: 08362
08:55:54:ST3_ModuleSelector:DEBUG: 62x42
08:55:54:ST3_ModuleSelector:DEBUG: A
08:56:00:ST3_ModuleSelector:INFO: M4UR3T0011310A2
08:56:00:ST3_ModuleSelector:INFO: 08362
08:56:00:febtest:INFO: Testing FEB with SN 1315
08:56:02:smx_tester:INFO: Scanning setup
08:56:02:elinks:INFO: Disabling clock on downlink 0
08:56:02:elinks:INFO: Disabling clock on downlink 1
08:56:02:elinks:INFO: Disabling clock on downlink 2
08:56:02:elinks:INFO: Disabling clock on downlink 3
08:56:02:elinks:INFO: Disabling clock on downlink 4
08:56:02:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:56:02:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
08:56:02:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:56:02:elinks:INFO: Disabling clock on downlink 0
08:56:02:elinks:INFO: Disabling clock on downlink 1
08:56:02:elinks:INFO: Disabling clock on downlink 2
08:56:02:elinks:INFO: Disabling clock on downlink 3
08:56:02:elinks:INFO: Disabling clock on downlink 4
08:56:02:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:56:02:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
08:56:02:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 0
08:56:02:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 1
08:56:02:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 2
08:56:02:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 3
08:56:02:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 4
08:56:02:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 5
08:56:02:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 6
08:56:02:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 7
08:56:02:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 8
08:56:02:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 9
08:56:02:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 10
08:56:02:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 11
08:56:02:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 12
08:56:02:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 13
08:56:02:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 14
08:56:02:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 15
08:56:02:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:56:02:elinks:INFO: Disabling clock on downlink 0
08:56:02:elinks:INFO: Disabling clock on downlink 1
08:56:02:elinks:INFO: Disabling clock on downlink 2
08:56:02:elinks:INFO: Disabling clock on downlink 3
08:56:02:elinks:INFO: Disabling clock on downlink 4
08:56:02:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:56:02:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
08:56:03:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:56:03:elinks:INFO: Disabling clock on downlink 0
08:56:03:elinks:INFO: Disabling clock on downlink 1
08:56:03:elinks:INFO: Disabling clock on downlink 2
08:56:03:elinks:INFO: Disabling clock on downlink 3
08:56:03:elinks:INFO: Disabling clock on downlink 4
08:56:03:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:56:03:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
08:56:03:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:56:03:elinks:INFO: Disabling clock on downlink 0
08:56:03:elinks:INFO: Disabling clock on downlink 1
08:56:03:elinks:INFO: Disabling clock on downlink 2
08:56:03:elinks:INFO: Disabling clock on downlink 3
08:56:03:elinks:INFO: Disabling clock on downlink 4
08:56:03:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:56:03:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
08:56:03:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
==============================================OOO==============================================
08:56:03:setup_element:INFO: Scanning clock phase
08:56:03:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
08:56:03:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
08:56:03:setup_element:INFO: Clock phase scan results for group 0, downlink 1
08:56:03:setup_element:INFO: Eye window for uplink 0 : ___________________________________________________________________________XXXXX
Clock Delay: 37
08:56:03:setup_element:INFO: Eye window for uplink 1 : ___________________________________________________________________________XXXXX
Clock Delay: 37
08:56:03:setup_element:INFO: Eye window for uplink 2 : X___________________________________________________________________________XXXX
Clock Delay: 38
08:56:03:setup_element:INFO: Eye window for uplink 3 : X___________________________________________________________________________XXXX
Clock Delay: 38
08:56:03:setup_element:INFO: Eye window for uplink 4 : ___________________________________________________________________________XXXXX
Clock Delay: 37
08:56:03:setup_element:INFO: Eye window for uplink 5 : ___________________________________________________________________________XXXXX
Clock Delay: 37
08:56:03:setup_element:INFO: Eye window for uplink 6 : __________________________________________________________________________XXXX__
Clock Delay: 35
08:56:03:setup_element:INFO: Eye window for uplink 7 : __________________________________________________________________________XXXX__
Clock Delay: 35
08:56:03:setup_element:INFO: Eye window for uplink 8 : _________________________________________________________________________XXXXXX_
Clock Delay: 35
08:56:03:setup_element:INFO: Eye window for uplink 9 : _________________________________________________________________________XXXXXX_
Clock Delay: 35
08:56:03:setup_element:INFO: Eye window for uplink 10: _________________________________________________________________________XXXXXX_
Clock Delay: 35
08:56:03:setup_element:INFO: Eye window for uplink 11: _________________________________________________________________________XXXXXX_
Clock Delay: 35
08:56:03:setup_element:INFO: Eye window for uplink 12: __________________________________________________________________________XXXXXX
Clock Delay: 36
08:56:03:setup_element:INFO: Eye window for uplink 13: __________________________________________________________________________XXXXXX
Clock Delay: 36
08:56:03:setup_element:INFO: Eye window for uplink 14: X_________________________________________________________________________XXXXXX
Clock Delay: 37
08:56:03:setup_element:INFO: Eye window for uplink 15: X_________________________________________________________________________XXXXXX
Clock Delay: 37
08:56:03:setup_element:INFO: Setting the clock phase to 36 for group 0, downlink 1
==============================================OOO==============================================
08:56:03:setup_element:INFO: Scanning data phases
08:56:03:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
08:56:03:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
08:56:09:setup_element:INFO: Data phase scan results for group 0, downlink 1
08:56:09:setup_element:INFO: Eye window for uplink 0 : ___________XXXXXX_______________________
Data delay found: 33
08:56:09:setup_element:INFO: Eye window for uplink 1 : ______XXXXXX____________________________
Data delay found: 28
08:56:09:setup_element:INFO: Eye window for uplink 2 : ______XXXXXXX___________________________
Data delay found: 29
08:56:09:setup_element:INFO: Eye window for uplink 3 : ____XXXXXX______________________________
Data delay found: 26
08:56:09:setup_element:INFO: Eye window for uplink 4 : ____XXXXXXX_____________________________
Data delay found: 27
08:56:09:setup_element:INFO: Eye window for uplink 5 : _XXXXX__________________________________
Data delay found: 23
08:56:09:setup_element:INFO: Eye window for uplink 6 : X__________________________________XXXXX
Data delay found: 17
08:56:09:setup_element:INFO: Eye window for uplink 7 : ________________________________XXXXX___
Data delay found: 14
08:56:09:setup_element:INFO: Eye window for uplink 8 : _______________________XXXXXX___________
Data delay found: 5
08:56:09:setup_element:INFO: Eye window for uplink 9 : ____________________________XXXXXX______
Data delay found: 10
08:56:09:setup_element:INFO: Eye window for uplink 10: _________________________XXXXX__________
Data delay found: 7
08:56:09:setup_element:INFO: Eye window for uplink 11: _____________________________XXXXXX_____
Data delay found: 11
08:56:09:setup_element:INFO: Eye window for uplink 12: _____________________________XXXX_______
Data delay found: 10
08:56:09:setup_element:INFO: Eye window for uplink 13: _______________________________XXXXX____
Data delay found: 13
08:56:09:setup_element:INFO: Eye window for uplink 14: ____________________________XXXXXX______
Data delay found: 10
08:56:09:setup_element:INFO: Eye window for uplink 15: _______________________________XXXXX____
Data delay found: 13
08:56:09:setup_element:INFO: Setting the data phase to 33 for uplink 0
08:56:09:setup_element:INFO: Setting the data phase to 28 for uplink 1
08:56:09:setup_element:INFO: Setting the data phase to 29 for uplink 2
08:56:09:setup_element:INFO: Setting the data phase to 26 for uplink 3
08:56:09:setup_element:INFO: Setting the data phase to 27 for uplink 4
08:56:09:setup_element:INFO: Setting the data phase to 23 for uplink 5
08:56:09:setup_element:INFO: Setting the data phase to 17 for uplink 6
08:56:09:setup_element:INFO: Setting the data phase to 14 for uplink 7
08:56:09:setup_element:INFO: Setting the data phase to 5 for uplink 8
08:56:09:setup_element:INFO: Setting the data phase to 10 for uplink 9
08:56:09:setup_element:INFO: Setting the data phase to 7 for uplink 10
08:56:09:setup_element:INFO: Setting the data phase to 11 for uplink 11
08:56:09:setup_element:INFO: Setting the data phase to 10 for uplink 12
08:56:09:setup_element:INFO: Setting the data phase to 13 for uplink 13
08:56:09:setup_element:INFO: Setting the data phase to 10 for uplink 14
08:56:09:setup_element:INFO: Setting the data phase to 13 for uplink 15
==============================================OOO==============================================
08:56:09:setup_element:INFO: Beginning SMX ASICs map scan
08:56:09:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
08:56:09:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
08:56:09:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
08:56:09:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
08:56:09:uplink:INFO: Setting uplinks mask [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
08:56:09:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 1
08:56:09:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 0
08:56:09:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 8
08:56:09:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 9
08:56:09:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 3
08:56:09:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 2
08:56:09:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 10
08:56:09:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 11
08:56:09:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 5
08:56:09:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 4
08:56:10:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 12
08:56:10:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 13
08:56:10:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 7
08:56:10:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 6
08:56:10:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 14
08:56:10:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 15
08:56:11:ST3_emu:INFO:
Setup Element:
Group: 0
Downlink: 1
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 1), (1, 0)
ASIC address 0x1: (ASIC uplink, uplink): (0, 8), (1, 9)
ASIC address 0x2: (ASIC uplink, uplink): (0, 3), (1, 2)
ASIC address 0x3: (ASIC uplink, uplink): (0, 10), (1, 11)
ASIC address 0x4: (ASIC uplink, uplink): (0, 5), (1, 4)
ASIC address 0x5: (ASIC uplink, uplink): (0, 12), (1, 13)
ASIC address 0x6: (ASIC uplink, uplink): (0, 7), (1, 6)
ASIC address 0x7: (ASIC uplink, uplink): (0, 14), (1, 15)
Clock Phase Characteristic:
Optimal Phase: 36
Window Length: 72
Eye Windows:
Uplink 0: ___________________________________________________________________________XXXXX
Uplink 1: ___________________________________________________________________________XXXXX
Uplink 2: X___________________________________________________________________________XXXX
Uplink 3: X___________________________________________________________________________XXXX
Uplink 4: ___________________________________________________________________________XXXXX
Uplink 5: ___________________________________________________________________________XXXXX
Uplink 6: __________________________________________________________________________XXXX__
Uplink 7: __________________________________________________________________________XXXX__
Uplink 8: _________________________________________________________________________XXXXXX_
Uplink 9: _________________________________________________________________________XXXXXX_
Uplink 10: _________________________________________________________________________XXXXXX_
Uplink 11: _________________________________________________________________________XXXXXX_
Uplink 12: __________________________________________________________________________XXXXXX
Uplink 13: __________________________________________________________________________XXXXXX
Uplink 14: X_________________________________________________________________________XXXXXX
Uplink 15: X_________________________________________________________________________XXXXXX
Data phase characteristics:
Uplink 0:
Optimal Phase: 33
Window Length: 34
Eye Window: ___________XXXXXX_______________________
Uplink 1:
Optimal Phase: 28
Window Length: 34
Eye Window: ______XXXXXX____________________________
Uplink 2:
Optimal Phase: 29
Window Length: 33
Eye Window: ______XXXXXXX___________________________
Uplink 3:
Optimal Phase: 26
Window Length: 34
Eye Window: ____XXXXXX______________________________
Uplink 4:
Optimal Phase: 27
Window Length: 33
Eye Window: ____XXXXXXX_____________________________
Uplink 5:
Optimal Phase: 23
Window Length: 35
Eye Window: _XXXXX__________________________________
Uplink 6:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXXX
Uplink 7:
Optimal Phase: 14
Window Length: 35
Eye Window: ________________________________XXXXX___
Uplink 8:
Optimal Phase: 5
Window Length: 34
Eye Window: _______________________XXXXXX___________
Uplink 9:
Optimal Phase: 10
Window Length: 34
Eye Window: ____________________________XXXXXX______
Uplink 10:
Optimal Phase: 7
Window Length: 35
Eye Window: _________________________XXXXX__________
Uplink 11:
Optimal Phase: 11
Window Length: 34
Eye Window: _____________________________XXXXXX_____
Uplink 12:
Optimal Phase: 10
Window Length: 36
Eye Window: _____________________________XXXX_______
Uplink 13:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 14:
Optimal Phase: 10
Window Length: 34
Eye Window: ____________________________XXXXXX______
Uplink 15:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
==============================================OOO==============================================
08:56:11:setup_element:INFO: Performing Elink synchronization
08:56:11:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
08:56:11:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
08:56:11:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
08:56:11:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
==============================================OOO==============================================
08:56:11:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 1
08:56:11:uplink:INFO: Enabling uplinks [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
==============================================OOO==============================================
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
0 | [0] | 1 | 0 | [1] | 2 | [(0, 1), (1, 0)]
1 | [0] | 1 | 0 | [8] | 2 | [(0, 8), (1, 9)]
2 | [0] | 1 | 0 | [3] | 2 | [(0, 3), (1, 2)]
3 | [0] | 1 | 0 | [10] | 2 | [(0, 10), (1, 11)]
4 | [0] | 1 | 0 | [5] | 2 | [(0, 5), (1, 4)]
5 | [0] | 1 | 0 | [12] | 2 | [(0, 12), (1, 13)]
6 | [0] | 1 | 0 | [7] | 2 | [(0, 7), (1, 6)]
7 | [0] | 1 | 0 | [14] | 2 | [(0, 14), (1, 15)]
|_________________________________________________________________________|
08:56:12:febtest:INFO: Init all SMX (CSA): 30
08:56:27:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
08:56:27:febtest:INFO: 01-00 | XA-000-09-004-007-006-024-12 | 34.6 | 1153.7
08:56:27:febtest:INFO: 08-01 | XA-000-09-004-007-005-024-02 | 37.7 | 1147.8
08:56:28:febtest:INFO: 03-02 | XA-000-09-004-007-005-016-02 | 34.6 | 1177.4
08:56:28:febtest:INFO: 10-03 | XA-000-09-004-007-006-017-12 | 44.1 | 1124.0
08:56:28:febtest:INFO: 05-04 | XA-000-09-004-007-006-023-12 | 47.3 | 1130.0
08:56:28:febtest:INFO: 12-05 | XA-000-09-004-007-006-022-12 | 40.9 | 1130.0
08:56:28:febtest:INFO: 07-06 | XA-000-09-004-007-006-018-12 | 37.7 | 1159.7
08:56:29:febtest:INFO: 14-07 | XA-000-09-004-007-004-016-15 | 31.4 | 1177.4
08:56:30:febtest:INFO: Set all CSA to ZERO
FEB type: A FEB_A: 1 FEB_B: 0
08:56:32:ST3_smx:INFO: chip: 1-0 37.726682 C 1165.571835 mV
08:56:32:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:56:32:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:56:32:ST3_smx:INFO: Electrons
08:56:32:ST3_smx:INFO: # loops 0
08:56:33:ST3_smx:INFO: # loops 1
08:56:35:ST3_smx:INFO: # loops 2
08:56:37:ST3_smx:INFO: # loops 3
08:56:38:ST3_smx:INFO: # loops 4
08:56:40:ST3_smx:INFO: Total # of broken channels: 0
08:56:40:ST3_smx:INFO: List of broken channels: []
08:56:40:ST3_smx:INFO: Total # of broken channels: 1
08:56:40:ST3_smx:INFO: List of broken channels: [127]
08:56:42:ST3_smx:INFO: chip: 8-1 37.726682 C 1159.654860 mV
08:56:42:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:56:42:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:56:42:ST3_smx:INFO: Electrons
08:56:42:ST3_smx:INFO: # loops 0
08:56:44:ST3_smx:INFO: # loops 1
08:56:45:ST3_smx:INFO: # loops 2
08:56:47:ST3_smx:INFO: # loops 3
08:56:49:ST3_smx:INFO: # loops 4
08:56:50:ST3_smx:INFO: Total # of broken channels: 0
08:56:50:ST3_smx:INFO: List of broken channels: []
08:56:50:ST3_smx:INFO: Total # of broken channels: 0
08:56:50:ST3_smx:INFO: List of broken channels: []
08:56:52:ST3_smx:INFO: chip: 3-2 34.556970 C 1189.190035 mV
08:56:52:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:56:52:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:56:52:ST3_smx:INFO: Electrons
08:56:52:ST3_smx:INFO: # loops 0
08:56:54:ST3_smx:INFO: # loops 1
08:56:55:ST3_smx:INFO: # loops 2
08:56:57:ST3_smx:INFO: # loops 3
08:56:59:ST3_smx:INFO: # loops 4
08:57:00:ST3_smx:INFO: Total # of broken channels: 0
08:57:00:ST3_smx:INFO: List of broken channels: []
08:57:00:ST3_smx:INFO: Total # of broken channels: 0
08:57:00:ST3_smx:INFO: List of broken channels: []
08:57:02:ST3_smx:INFO: chip: 10-3 44.073563 C 1135.937260 mV
08:57:02:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:57:02:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:57:02:ST3_smx:INFO: Electrons
08:57:02:ST3_smx:INFO: # loops 0
08:57:04:ST3_smx:INFO: # loops 1
08:57:05:ST3_smx:INFO: # loops 2
08:57:07:ST3_smx:INFO: # loops 3
08:57:08:ST3_smx:INFO: # loops 4
08:57:10:ST3_smx:INFO: Total # of broken channels: 0
08:57:10:ST3_smx:INFO: List of broken channels: []
08:57:10:ST3_smx:INFO: Total # of broken channels: 1
08:57:10:ST3_smx:INFO: List of broken channels: [123]
08:57:11:ST3_smx:INFO: chip: 5-4 47.250730 C 1135.937260 mV
08:57:11:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:57:11:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:57:11:ST3_smx:INFO: Electrons
08:57:11:ST3_smx:INFO: # loops 0
08:57:13:ST3_smx:INFO: # loops 1
08:57:14:ST3_smx:INFO: # loops 2
08:57:16:ST3_smx:INFO: # loops 3
08:57:17:ST3_smx:INFO: # loops 4
08:57:19:ST3_smx:INFO: Total # of broken channels: 0
08:57:19:ST3_smx:INFO: List of broken channels: []
08:57:19:ST3_smx:INFO: Total # of broken channels: 1
08:57:19:ST3_smx:INFO: List of broken channels: [69]
08:57:21:ST3_smx:INFO: chip: 12-5 40.898880 C 1141.874115 mV
08:57:21:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:57:21:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:57:21:ST3_smx:INFO: Electrons
08:57:21:ST3_smx:INFO: # loops 0
08:57:22:ST3_smx:INFO: # loops 1
08:57:24:ST3_smx:INFO: # loops 2
08:57:25:ST3_smx:INFO: # loops 3
08:57:27:ST3_smx:INFO: # loops 4
08:57:28:ST3_smx:INFO: Total # of broken channels: 0
08:57:28:ST3_smx:INFO: List of broken channels: []
08:57:28:ST3_smx:INFO: Total # of broken channels: 0
08:57:28:ST3_smx:INFO: List of broken channels: []
08:57:30:ST3_smx:INFO: chip: 7-6 37.726682 C 1171.483840 mV
08:57:30:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:57:30:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:57:30:ST3_smx:INFO: Electrons
08:57:30:ST3_smx:INFO: # loops 0
08:57:31:ST3_smx:INFO: # loops 1
08:57:33:ST3_smx:INFO: # loops 2
08:57:34:ST3_smx:INFO: # loops 3
08:57:36:ST3_smx:INFO: # loops 4
08:57:37:ST3_smx:INFO: Total # of broken channels: 0
08:57:37:ST3_smx:INFO: List of broken channels: []
08:57:37:ST3_smx:INFO: Total # of broken channels: 0
08:57:37:ST3_smx:INFO: List of broken channels: []
08:57:39:ST3_smx:INFO: chip: 14-7 31.389742 C 1183.292940 mV
08:57:39:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:57:39:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:57:39:ST3_smx:INFO: Electrons
08:57:39:ST3_smx:INFO: # loops 0
08:57:40:ST3_smx:INFO: # loops 1
08:57:42:ST3_smx:INFO: # loops 2
08:57:43:ST3_smx:INFO: # loops 3
08:57:45:ST3_smx:INFO: # loops 4
08:57:47:ST3_smx:INFO: Total # of broken channels: 0
08:57:47:ST3_smx:INFO: List of broken channels: []
08:57:47:ST3_smx:INFO: Total # of broken channels: 1
08:57:47:ST3_smx:INFO: List of broken channels: [1]
08:57:47:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
08:57:47:febtest:INFO: 01-00 | XA-000-09-004-007-006-024-12 | 37.7 | 1189.2
08:57:47:febtest:INFO: 08-01 | XA-000-09-004-007-005-024-02 | 37.7 | 1183.3
08:57:47:febtest:INFO: 03-02 | XA-000-09-004-007-005-016-02 | 34.6 | 1206.9
08:57:48:febtest:INFO: 10-03 | XA-000-09-004-007-006-017-12 | 44.1 | 1153.7
08:57:48:febtest:INFO: 05-04 | XA-000-09-004-007-006-023-12 | 47.3 | 1159.7
08:57:48:febtest:INFO: 12-05 | XA-000-09-004-007-006-022-12 | 44.1 | 1165.6
08:57:48:febtest:INFO: 07-06 | XA-000-09-004-007-006-018-12 | 40.9 | 1189.2
08:57:48:febtest:INFO: 14-07 | XA-000-09-004-007-004-016-15 | 34.6 | 1206.9
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-Sensor
TEST_DATE : 25_01_30-08_55_49
OPERATOR : Kerstin S.;
SITE : GSI | SETUP : GSI_TEST_SETUP_2
------------------------------------------------------------
| FEB_SN : 1315| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_A
AMP_MODE : STS
------------------------------------------------------------
SENSOR_NAME: 08362 | SIZE: 62x42 | GRADE: A
MODULE_NAME: M4UR3T0011310A2
LADDER_NAME: L4UR301131
------------------------------------------------------------
VI_before_Init : ['2.448', '1.5410', '1.850', '2.6280', '0.000', '0.0000', '0.000', '0.0000']
VI_after__Init : ['2.450', '2.0170', '1.850', '2.5530', '0.000', '0.0000', '0.000', '0.0000']
VI_at__the_End : ['2.450', '1.9750', '1.850', '0.5250', '0.000', '0.0000', '0.000', '0.0000']