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FEB_1322 04.02.25 09:41:02
Info
09:41:02:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
09:41:02:ST3_Shared:INFO: FEB-Sensor
09:41:02:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
09:41:34:ST3_ModuleSelector:INFO: M4UR3T3011313A2
09:41:34:ST3_ModuleSelector:INFO: 07363
09:41:34:febtest:INFO: Testing FEB with SN 1322
09:41:36:smx_tester:INFO: Scanning setup
09:41:36:elinks:INFO: Disabling clock on downlink 0
09:41:36:elinks:INFO: Disabling clock on downlink 1
09:41:36:elinks:INFO: Disabling clock on downlink 2
09:41:36:elinks:INFO: Disabling clock on downlink 3
09:41:36:elinks:INFO: Disabling clock on downlink 4
09:41:36:setup_element:INFO: Checking SOS, encoding_mode: SOS
09:41:36:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
09:41:36:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
09:41:36:elinks:INFO: Disabling clock on downlink 0
09:41:36:elinks:INFO: Disabling clock on downlink 1
09:41:36:elinks:INFO: Disabling clock on downlink 2
09:41:36:elinks:INFO: Disabling clock on downlink 3
09:41:36:elinks:INFO: Disabling clock on downlink 4
09:41:36:setup_element:INFO: Checking SOS, encoding_mode: SOS
09:41:36:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
09:41:36:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 0
09:41:36:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 1
09:41:36:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 2
09:41:36:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 3
09:41:36:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 4
09:41:36:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 5
09:41:36:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 6
09:41:36:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 7
09:41:36:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 8
09:41:36:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 9
09:41:36:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 10
09:41:36:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 11
09:41:36:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 12
09:41:36:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 13
09:41:36:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 14
09:41:36:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 15
09:41:36:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
09:41:36:elinks:INFO: Disabling clock on downlink 0
09:41:36:elinks:INFO: Disabling clock on downlink 1
09:41:36:elinks:INFO: Disabling clock on downlink 2
09:41:36:elinks:INFO: Disabling clock on downlink 3
09:41:36:elinks:INFO: Disabling clock on downlink 4
09:41:36:setup_element:INFO: Checking SOS, encoding_mode: SOS
09:41:36:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
09:41:36:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
09:41:36:elinks:INFO: Disabling clock on downlink 0
09:41:36:elinks:INFO: Disabling clock on downlink 1
09:41:36:elinks:INFO: Disabling clock on downlink 2
09:41:36:elinks:INFO: Disabling clock on downlink 3
09:41:36:elinks:INFO: Disabling clock on downlink 4
09:41:36:setup_element:INFO: Checking SOS, encoding_mode: SOS
09:41:36:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
09:41:36:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
09:41:36:elinks:INFO: Disabling clock on downlink 0
09:41:36:elinks:INFO: Disabling clock on downlink 1
09:41:36:elinks:INFO: Disabling clock on downlink 2
09:41:36:elinks:INFO: Disabling clock on downlink 3
09:41:36:elinks:INFO: Disabling clock on downlink 4
09:41:36:setup_element:INFO: Checking SOS, encoding_mode: SOS
09:41:36:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
09:41:37:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
==============================================OOO==============================================
09:41:37:setup_element:INFO: Scanning clock phase
09:41:37:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
09:41:37:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
09:41:37:setup_element:INFO: Clock phase scan results for group 0, downlink 1
09:41:37:setup_element:INFO: Eye window for uplink 0 : X_________________________________________________________________________XXXXXX
Clock Delay: 37
09:41:37:setup_element:INFO: Eye window for uplink 1 : X_________________________________________________________________________XXXXXX
Clock Delay: 37
09:41:37:setup_element:INFO: Eye window for uplink 2 : ___________________________________________________________________________XXXXX
Clock Delay: 37
09:41:37:setup_element:INFO: Eye window for uplink 3 : ___________________________________________________________________________XXXXX
Clock Delay: 37
09:41:37:setup_element:INFO: Eye window for uplink 4 : __________________________________________________________________________XXXXX_
Clock Delay: 36
09:41:37:setup_element:INFO: Eye window for uplink 5 : __________________________________________________________________________XXXXX_
Clock Delay: 36
09:41:37:setup_element:INFO: Eye window for uplink 6 : __________________________________________________________________________XXXXX_
Clock Delay: 36
09:41:37:setup_element:INFO: Eye window for uplink 7 : __________________________________________________________________________XXXXX_
Clock Delay: 36
09:41:37:setup_element:INFO: Eye window for uplink 8 : __________________________________________________________________________XXXXX_
Clock Delay: 36
09:41:37:setup_element:INFO: Eye window for uplink 9 : __________________________________________________________________________XXXXX_
Clock Delay: 36
09:41:37:setup_element:INFO: Eye window for uplink 10: ________________________________________________________________________XXXXXX__
Clock Delay: 34
09:41:37:setup_element:INFO: Eye window for uplink 11: ________________________________________________________________________XXXXXX__
Clock Delay: 34
09:41:37:setup_element:INFO: Eye window for uplink 12: ________________________________________________________________________XXXXXX__
Clock Delay: 34
09:41:37:setup_element:INFO: Eye window for uplink 13: ________________________________________________________________________XXXXXX__
Clock Delay: 34
09:41:37:setup_element:INFO: Eye window for uplink 14: _________________________________________________________________________XXXXXX_
Clock Delay: 35
09:41:37:setup_element:INFO: Eye window for uplink 15: _________________________________________________________________________XXXXXX_
Clock Delay: 35
09:41:37:setup_element:INFO: Setting the clock phase to 36 for group 0, downlink 1
==============================================OOO==============================================
09:41:37:setup_element:INFO: Scanning data phases
09:41:37:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
09:41:37:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
09:41:42:setup_element:INFO: Data phase scan results for group 0, downlink 1
09:41:42:setup_element:INFO: Eye window for uplink 0 : _________XXXXXX_________________________
Data delay found: 31
09:41:42:setup_element:INFO: Eye window for uplink 1 : _____XXXXX______________________________
Data delay found: 27
09:41:42:setup_element:INFO: Eye window for uplink 2 : _______XXXXX____________________________
Data delay found: 29
09:41:42:setup_element:INFO: Eye window for uplink 3 : ____XXXXX_______________________________
Data delay found: 26
09:41:42:setup_element:INFO: Eye window for uplink 4 : _XXXXXXX________________________________
Data delay found: 24
09:41:42:setup_element:INFO: Eye window for uplink 5 : XXX___________________________________XX
Data delay found: 20
09:41:42:setup_element:INFO: Eye window for uplink 6 : XXX_________________________________XXXX
Data delay found: 19
09:41:42:setup_element:INFO: Eye window for uplink 7 : __________________________________XXXXX_
Data delay found: 16
09:41:42:setup_element:INFO: Eye window for uplink 8 : _______________________XXXXXX___________
Data delay found: 5
09:41:42:setup_element:INFO: Eye window for uplink 9 : _____________________________XXXXX______
Data delay found: 11
09:41:42:setup_element:INFO: Eye window for uplink 10: ______________________XXXXX_____________
Data delay found: 4
09:41:42:setup_element:INFO: Eye window for uplink 11: __________________________XXXXXX________
Data delay found: 8
09:41:42:setup_element:INFO: Eye window for uplink 12: _________________________XXXX_________XX
Data delay found: 12
09:41:42:setup_element:INFO: Eye window for uplink 13: ___________________________XXXXX______XX
Data delay found: 13
09:41:42:setup_element:INFO: Eye window for uplink 14: _________________________XXXXX__________
Data delay found: 7
09:41:42:setup_element:INFO: Eye window for uplink 15: ___________________________XXXXX________
Data delay found: 9
09:41:42:setup_element:INFO: Setting the data phase to 31 for uplink 0
09:41:42:setup_element:INFO: Setting the data phase to 27 for uplink 1
09:41:42:setup_element:INFO: Setting the data phase to 29 for uplink 2
09:41:42:setup_element:INFO: Setting the data phase to 26 for uplink 3
09:41:42:setup_element:INFO: Setting the data phase to 24 for uplink 4
09:41:42:setup_element:INFO: Setting the data phase to 20 for uplink 5
09:41:42:setup_element:INFO: Setting the data phase to 19 for uplink 6
09:41:42:setup_element:INFO: Setting the data phase to 16 for uplink 7
09:41:42:setup_element:INFO: Setting the data phase to 5 for uplink 8
09:41:42:setup_element:INFO: Setting the data phase to 11 for uplink 9
09:41:42:setup_element:INFO: Setting the data phase to 4 for uplink 10
09:41:42:setup_element:INFO: Setting the data phase to 8 for uplink 11
09:41:42:setup_element:INFO: Setting the data phase to 12 for uplink 12
09:41:42:setup_element:INFO: Setting the data phase to 13 for uplink 13
09:41:42:setup_element:INFO: Setting the data phase to 7 for uplink 14
09:41:42:setup_element:INFO: Setting the data phase to 9 for uplink 15
==============================================OOO==============================================
09:41:42:setup_element:INFO: Beginning SMX ASICs map scan
09:41:42:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
09:41:42:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
09:41:42:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
09:41:42:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
09:41:42:uplink:INFO: Setting uplinks mask [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
09:41:42:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 1
09:41:42:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 0
09:41:42:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 8
09:41:43:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 9
09:41:43:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 3
09:41:43:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 2
09:41:43:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 10
09:41:43:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 11
09:41:43:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 5
09:41:43:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 4
09:41:43:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 12
09:41:43:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 13
09:41:43:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 7
09:41:43:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 6
09:41:44:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 14
09:41:44:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 15
09:41:45:ST3_emu:INFO:
Setup Element:
Group: 0
Downlink: 1
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 1), (1, 0)
ASIC address 0x1: (ASIC uplink, uplink): (0, 8), (1, 9)
ASIC address 0x2: (ASIC uplink, uplink): (0, 3), (1, 2)
ASIC address 0x3: (ASIC uplink, uplink): (0, 10), (1, 11)
ASIC address 0x4: (ASIC uplink, uplink): (0, 5), (1, 4)
ASIC address 0x5: (ASIC uplink, uplink): (0, 12), (1, 13)
ASIC address 0x6: (ASIC uplink, uplink): (0, 7), (1, 6)
ASIC address 0x7: (ASIC uplink, uplink): (0, 14), (1, 15)
Clock Phase Characteristic:
Optimal Phase: 36
Window Length: 71
Eye Windows:
Uplink 0: X_________________________________________________________________________XXXXXX
Uplink 1: X_________________________________________________________________________XXXXXX
Uplink 2: ___________________________________________________________________________XXXXX
Uplink 3: ___________________________________________________________________________XXXXX
Uplink 4: __________________________________________________________________________XXXXX_
Uplink 5: __________________________________________________________________________XXXXX_
Uplink 6: __________________________________________________________________________XXXXX_
Uplink 7: __________________________________________________________________________XXXXX_
Uplink 8: __________________________________________________________________________XXXXX_
Uplink 9: __________________________________________________________________________XXXXX_
Uplink 10: ________________________________________________________________________XXXXXX__
Uplink 11: ________________________________________________________________________XXXXXX__
Uplink 12: ________________________________________________________________________XXXXXX__
Uplink 13: ________________________________________________________________________XXXXXX__
Uplink 14: _________________________________________________________________________XXXXXX_
Uplink 15: _________________________________________________________________________XXXXXX_
Data phase characteristics:
Uplink 0:
Optimal Phase: 31
Window Length: 34
Eye Window: _________XXXXXX_________________________
Uplink 1:
Optimal Phase: 27
Window Length: 35
Eye Window: _____XXXXX______________________________
Uplink 2:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 3:
Optimal Phase: 26
Window Length: 35
Eye Window: ____XXXXX_______________________________
Uplink 4:
Optimal Phase: 24
Window Length: 33
Eye Window: _XXXXXXX________________________________
Uplink 5:
Optimal Phase: 20
Window Length: 35
Eye Window: XXX___________________________________XX
Uplink 6:
Optimal Phase: 19
Window Length: 33
Eye Window: XXX_________________________________XXXX
Uplink 7:
Optimal Phase: 16
Window Length: 35
Eye Window: __________________________________XXXXX_
Uplink 8:
Optimal Phase: 5
Window Length: 34
Eye Window: _______________________XXXXXX___________
Uplink 9:
Optimal Phase: 11
Window Length: 35
Eye Window: _____________________________XXXXX______
Uplink 10:
Optimal Phase: 4
Window Length: 35
Eye Window: ______________________XXXXX_____________
Uplink 11:
Optimal Phase: 8
Window Length: 34
Eye Window: __________________________XXXXXX________
Uplink 12:
Optimal Phase: 12
Window Length: 25
Eye Window: _________________________XXXX_________XX
Uplink 13:
Optimal Phase: 13
Window Length: 27
Eye Window: ___________________________XXXXX______XX
Uplink 14:
Optimal Phase: 7
Window Length: 35
Eye Window: _________________________XXXXX__________
Uplink 15:
Optimal Phase: 9
Window Length: 35
Eye Window: ___________________________XXXXX________
==============================================OOO==============================================
09:41:45:setup_element:INFO: Performing Elink synchronization
09:41:45:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
09:41:45:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
09:41:45:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
09:41:45:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
==============================================OOO==============================================
09:41:45:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 1
09:41:45:uplink:INFO: Enabling uplinks [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
==============================================OOO==============================================
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
0 | [0] | 1 | 0 | [1] | 2 | [(0, 1), (1, 0)]
1 | [0] | 1 | 0 | [8] | 2 | [(0, 8), (1, 9)]
2 | [0] | 1 | 0 | [3] | 2 | [(0, 3), (1, 2)]
3 | [0] | 1 | 0 | [10] | 2 | [(0, 10), (1, 11)]
4 | [0] | 1 | 0 | [5] | 2 | [(0, 5), (1, 4)]
5 | [0] | 1 | 0 | [12] | 2 | [(0, 12), (1, 13)]
6 | [0] | 1 | 0 | [7] | 2 | [(0, 7), (1, 6)]
7 | [0] | 1 | 0 | [14] | 2 | [(0, 14), (1, 15)]
|_________________________________________________________________________|
09:41:46:febtest:INFO: Init all SMX (CSA): 30
09:41:59:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
09:42:00:febtest:INFO: 01-00 | XA-000-09-004-006-012-013-12 | 28.2 | 1177.4
09:42:00:febtest:INFO: 08-01 | XA-000-09-004-007-004-008-08 | 34.6 | 1153.7
09:42:00:febtest:INFO: 03-02 | XA-000-09-004-007-004-014-08 | 28.2 | 1195.1
09:42:00:febtest:INFO: 10-03 | XA-000-09-004-007-006-009-11 | 28.2 | 1177.4
09:42:00:febtest:INFO: 05-04 | XA-000-09-004-007-004-015-08 | 25.1 | 1201.0
09:42:01:febtest:INFO: 12-05 | XA-000-09-004-007-005-015-05 | 34.6 | 1153.7
09:42:01:febtest:INFO: 07-06 | XA-000-09-004-007-006-016-12 | 40.9 | 1153.7
09:42:01:febtest:INFO: 14-07 | XA-000-09-004-006-011-010-04 | 37.7 | 1153.7
09:42:02:febtest:INFO: Set all CSA to ZERO
FEB type: A FEB_A: 1 FEB_B: 0
09:42:04:ST3_smx:INFO: chip: 1-0 28.225000 C 1189.190035 mV
09:42:04:ST3_discr_histo:WARNING: Not enough entries for fit!!!
09:42:04:ST3_discr_histo:WARNING: Not enough entries for fit!!!
09:42:04:ST3_smx:INFO: Electrons
09:42:04:ST3_smx:INFO: # loops 0
09:42:06:ST3_smx:INFO: # loops 1
09:42:07:ST3_smx:INFO: # loops 2
09:42:09:ST3_smx:INFO: # loops 3
09:42:10:ST3_smx:INFO: # loops 4
09:42:12:ST3_smx:INFO: Total # of broken channels: 0
09:42:12:ST3_smx:INFO: List of broken channels: []
09:42:12:ST3_smx:INFO: Total # of broken channels: 0
09:42:12:ST3_smx:INFO: List of broken channels: []
09:42:14:ST3_smx:INFO: chip: 8-1 34.556970 C 1171.483840 mV
09:42:14:ST3_discr_histo:WARNING: Not enough entries for fit!!!
09:42:14:ST3_discr_histo:WARNING: Not enough entries for fit!!!
09:42:14:ST3_smx:INFO: Electrons
09:42:14:ST3_smx:INFO: # loops 0
09:42:15:ST3_smx:INFO: # loops 1
09:42:17:ST3_smx:INFO: # loops 2
09:42:18:ST3_smx:INFO: # loops 3
09:42:20:ST3_smx:INFO: # loops 4
09:42:21:ST3_smx:INFO: Total # of broken channels: 0
09:42:21:ST3_smx:INFO: List of broken channels: []
09:42:21:ST3_smx:INFO: Total # of broken channels: 0
09:42:21:ST3_smx:INFO: List of broken channels: []
09:42:23:ST3_smx:INFO: chip: 3-2 28.225000 C 1206.851500 mV
09:42:23:ST3_discr_histo:WARNING: Not enough entries for fit!!!
09:42:23:ST3_discr_histo:WARNING: Not enough entries for fit!!!
09:42:23:ST3_smx:INFO: Electrons
09:42:23:ST3_smx:INFO: # loops 0
09:42:25:ST3_smx:INFO: # loops 1
09:42:26:ST3_smx:INFO: # loops 2
09:42:28:ST3_smx:INFO: # loops 3
09:42:29:ST3_smx:INFO: # loops 4
09:42:31:ST3_smx:INFO: Total # of broken channels: 0
09:42:31:ST3_smx:INFO: List of broken channels: []
09:42:31:ST3_smx:INFO: Total # of broken channels: 1
09:42:31:ST3_smx:INFO: List of broken channels: [126]
09:42:33:ST3_smx:INFO: chip: 10-3 28.225000 C 1189.190035 mV
09:42:33:ST3_discr_histo:WARNING: Not enough entries for fit!!!
09:42:33:ST3_discr_histo:WARNING: Not enough entries for fit!!!
09:42:33:ST3_smx:INFO: Electrons
09:42:33:ST3_smx:INFO: # loops 0
09:42:34:ST3_smx:INFO: # loops 1
09:42:36:ST3_smx:INFO: # loops 2
09:42:37:ST3_smx:INFO: # loops 3
09:42:39:ST3_smx:INFO: # loops 4
09:42:40:ST3_smx:INFO: Total # of broken channels: 0
09:42:40:ST3_smx:INFO: List of broken channels: []
09:42:40:ST3_smx:INFO: Total # of broken channels: 0
09:42:40:ST3_smx:INFO: List of broken channels: []
09:42:42:ST3_smx:INFO: chip: 5-4 25.062742 C 1212.728715 mV
09:42:42:ST3_discr_histo:WARNING: Not enough entries for fit!!!
09:42:42:ST3_discr_histo:WARNING: Not enough entries for fit!!!
09:42:42:ST3_smx:INFO: Electrons
09:42:42:ST3_smx:INFO: # loops 0
09:42:44:ST3_smx:INFO: # loops 1
09:42:45:ST3_smx:INFO: # loops 2
09:42:47:ST3_smx:INFO: # loops 3
09:42:48:ST3_smx:INFO: # loops 4
09:42:50:ST3_smx:INFO: Total # of broken channels: 0
09:42:50:ST3_smx:INFO: List of broken channels: []
09:42:50:ST3_smx:INFO: Total # of broken channels: 0
09:42:50:ST3_smx:INFO: List of broken channels: []
09:42:51:ST3_smx:INFO: chip: 12-5 37.726682 C 1165.571835 mV
09:42:51:ST3_discr_histo:WARNING: Not enough entries for fit!!!
09:42:51:ST3_discr_histo:WARNING: Not enough entries for fit!!!
09:42:51:ST3_smx:INFO: Electrons
09:42:51:ST3_smx:INFO: # loops 0
09:42:53:ST3_smx:INFO: # loops 1
09:42:54:ST3_smx:INFO: # loops 2
09:42:56:ST3_smx:INFO: # loops 3
09:42:57:ST3_smx:INFO: # loops 4
09:42:59:ST3_smx:INFO: Total # of broken channels: 1
09:42:59:ST3_smx:INFO: List of broken channels: [0]
09:42:59:ST3_smx:INFO: Total # of broken channels: 10
09:42:59:ST3_smx:INFO: List of broken channels: [0, 2, 4, 6, 8, 118, 120, 122, 124, 126]
09:43:01:ST3_smx:INFO: chip: 7-6 40.898880 C 1165.571835 mV
09:43:01:ST3_discr_histo:WARNING: Not enough entries for fit!!!
09:43:01:ST3_discr_histo:WARNING: Not enough entries for fit!!!
09:43:01:ST3_smx:INFO: Electrons
09:43:01:ST3_smx:INFO: # loops 0
09:43:02:ST3_smx:INFO: # loops 1
09:43:04:ST3_smx:INFO: # loops 2
09:43:05:ST3_smx:INFO: # loops 3
09:43:07:ST3_smx:INFO: # loops 4
09:43:08:ST3_smx:INFO: Total # of broken channels: 0
09:43:08:ST3_smx:INFO: List of broken channels: []
09:43:08:ST3_smx:INFO: Total # of broken channels: 1
09:43:08:ST3_smx:INFO: List of broken channels: [24]
09:43:10:ST3_smx:INFO: chip: 14-7 40.898880 C 1159.654860 mV
09:43:10:ST3_discr_histo:WARNING: Not enough entries for fit!!!
09:43:10:ST3_discr_histo:WARNING: Not enough entries for fit!!!
09:43:10:ST3_smx:INFO: Electrons
09:43:10:ST3_smx:INFO: # loops 0
09:43:12:ST3_smx:INFO: # loops 1
09:43:13:ST3_smx:INFO: # loops 2
09:43:15:ST3_smx:INFO: # loops 3
09:43:16:ST3_smx:INFO: # loops 4
09:43:18:ST3_smx:INFO: Total # of broken channels: 0
09:43:18:ST3_smx:INFO: List of broken channels: []
09:43:18:ST3_smx:INFO: Total # of broken channels: 0
09:43:18:ST3_smx:INFO: List of broken channels: []
09:43:18:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
09:43:18:febtest:INFO: 01-00 | XA-000-09-004-006-012-013-12 | 31.4 | 1212.7
09:43:18:febtest:INFO: 08-01 | XA-000-09-004-007-004-008-08 | 34.6 | 1189.2
09:43:19:febtest:INFO: 03-02 | XA-000-09-004-007-004-014-08 | 31.4 | 1224.5
09:43:19:febtest:INFO: 10-03 | XA-000-09-004-007-006-009-11 | 31.4 | 1212.7
09:43:19:febtest:INFO: 05-04 | XA-000-09-004-007-004-015-08 | 28.2 | 1236.2
09:43:19:febtest:INFO: 12-05 | XA-000-09-004-007-005-015-05 | 37.7 | 1183.3
09:43:20:febtest:INFO: 07-06 | XA-000-09-004-007-006-016-12 | 44.1 | 1189.2
09:43:20:febtest:INFO: 14-07 | XA-000-09-004-006-011-010-04 | 40.9 | 1183.3
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-Sensor
TEST_DATE : 25_02_04-09_41_02
OPERATOR : Dennis P.;
SITE : GSI | SETUP : GSI_TEST_SETUP_2
------------------------------------------------------------
| FEB_SN : 1322| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_A
AMP_MODE : STS
------------------------------------------------------------
SENSOR_NAME: 07363 | SIZE: 62x62 | GRADE: A
MODULE_NAME: M4UR3T3011313A2
LADDER_NAME: L4UR301131
------------------------------------------------------------
VI_before_Init : ['2.447', '1.5280', '1.850', '2.2690', '0.000', '0.0000', '0.000', '0.0000']
VI_after__Init : ['2.450', '2.0220', '1.850', '2.3130', '0.000', '0.0000', '0.000', '0.0000']
VI_at__the_End : ['2.450', '1.9790', '1.850', '0.5280', '0.000', '0.0000', '0.000', '0.0000']