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FEB_1325 03.02.25 10:13:58
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10:13:58:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
10:13:58:ST3_Shared:INFO: FEB-Sensor
10:13:58:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
10:14:03:ST3_ModuleSelector:DEBUG: M4UR3B1011311B2
10:14:03:ST3_ModuleSelector:DEBUG: L4UR301131
10:14:03:ST3_ModuleSelector:DEBUG: 17382
10:14:03:ST3_ModuleSelector:DEBUG: 62x42
10:14:03:ST3_ModuleSelector:DEBUG: A
10:14:03:ST3_ModuleSelector:DEBUG: M4UR3B1011311B2
10:14:03:ST3_ModuleSelector:DEBUG: L4UR301131
10:14:03:ST3_ModuleSelector:DEBUG: 17382
10:14:03:ST3_ModuleSelector:DEBUG: 62x42
10:14:03:ST3_ModuleSelector:DEBUG: A
10:15:47:ST3_ModuleSelector:INFO: M4UR3B1011311B2
10:15:47:ST3_ModuleSelector:INFO: 17382
10:15:47:febtest:INFO: Testing FEB with SN 1325
10:15:48:smx_tester:INFO: Scanning setup
10:15:48:elinks:INFO: Disabling clock on downlink 0
10:15:48:elinks:INFO: Disabling clock on downlink 1
10:15:48:elinks:INFO: Disabling clock on downlink 2
10:15:48:elinks:INFO: Disabling clock on downlink 3
10:15:48:elinks:INFO: Disabling clock on downlink 4
10:15:48:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:15:48:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
10:15:48:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:15:48:elinks:INFO: Disabling clock on downlink 0
10:15:48:elinks:INFO: Disabling clock on downlink 1
10:15:48:elinks:INFO: Disabling clock on downlink 2
10:15:48:elinks:INFO: Disabling clock on downlink 3
10:15:48:elinks:INFO: Disabling clock on downlink 4
10:15:48:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:15:48:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
10:15:48:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 0
10:15:48:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 1
10:15:48:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 2
10:15:48:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 3
10:15:48:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 4
10:15:48:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 5
10:15:48:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 6
10:15:48:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 7
10:15:48:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 8
10:15:48:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 9
10:15:48:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 10
10:15:48:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 11
10:15:48:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 12
10:15:48:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 13
10:15:48:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 14
10:15:48:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 15
10:15:48:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:15:48:elinks:INFO: Disabling clock on downlink 0
10:15:48:elinks:INFO: Disabling clock on downlink 1
10:15:48:elinks:INFO: Disabling clock on downlink 2
10:15:48:elinks:INFO: Disabling clock on downlink 3
10:15:49:elinks:INFO: Disabling clock on downlink 4
10:15:49:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:15:49:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
10:15:49:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:15:49:elinks:INFO: Disabling clock on downlink 0
10:15:49:elinks:INFO: Disabling clock on downlink 1
10:15:49:elinks:INFO: Disabling clock on downlink 2
10:15:49:elinks:INFO: Disabling clock on downlink 3
10:15:49:elinks:INFO: Disabling clock on downlink 4
10:15:49:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:15:49:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
10:15:49:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:15:49:elinks:INFO: Disabling clock on downlink 0
10:15:49:elinks:INFO: Disabling clock on downlink 1
10:15:49:elinks:INFO: Disabling clock on downlink 2
10:15:49:elinks:INFO: Disabling clock on downlink 3
10:15:49:elinks:INFO: Disabling clock on downlink 4
10:15:49:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:15:49:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
10:15:49:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
==============================================OOO==============================================
10:15:49:setup_element:INFO: Scanning clock phase
10:15:49:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
10:15:49:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
10:15:49:setup_element:INFO: Clock phase scan results for group 0, downlink 1
10:15:49:setup_element:INFO: Eye window for uplink 0 : _______________________________________________________________________XXXXXXX__
Clock Delay: 34
10:15:49:setup_element:INFO: Eye window for uplink 1 : _______________________________________________________________________XXXXXXX__
Clock Delay: 34
10:15:49:setup_element:INFO: Eye window for uplink 2 : _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
10:15:49:setup_element:INFO: Eye window for uplink 3 : _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
10:15:49:setup_element:INFO: Eye window for uplink 4 : _______________________________________________________________________XXXXXXX__
Clock Delay: 34
10:15:49:setup_element:INFO: Eye window for uplink 5 : _______________________________________________________________________XXXXXXX__
Clock Delay: 34
10:15:49:setup_element:INFO: Eye window for uplink 6 : _______________________________________________________________________XXXXXXX__
Clock Delay: 34
10:15:49:setup_element:INFO: Eye window for uplink 7 : _______________________________________________________________________XXXXXXX__
Clock Delay: 34
10:15:49:setup_element:INFO: Eye window for uplink 8 : _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
10:15:49:setup_element:INFO: Eye window for uplink 9 : _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
10:15:49:setup_element:INFO: Eye window for uplink 10: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
10:15:49:setup_element:INFO: Eye window for uplink 11: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
10:15:49:setup_element:INFO: Eye window for uplink 12: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
10:15:49:setup_element:INFO: Eye window for uplink 13: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
10:15:49:setup_element:INFO: Eye window for uplink 14: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
10:15:49:setup_element:INFO: Eye window for uplink 15: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
10:15:49:setup_element:INFO: Setting the clock phase to 33 for group 0, downlink 1
==============================================OOO==============================================
10:15:49:setup_element:INFO: Scanning data phases
10:15:49:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
10:15:49:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
10:15:55:setup_element:INFO: Data phase scan results for group 0, downlink 1
10:15:55:setup_element:INFO: Eye window for uplink 0 : ______________XXXXX_____________________
Data delay found: 36
10:15:55:setup_element:INFO: Eye window for uplink 1 : ____________XXXXX_______________________
Data delay found: 34
10:15:55:setup_element:INFO: Eye window for uplink 2 : ___________XXXX_________________________
Data delay found: 32
10:15:55:setup_element:INFO: Eye window for uplink 3 : ___________XXXXX________________________
Data delay found: 33
10:15:55:setup_element:INFO: Eye window for uplink 4 : ___________XXXXXX_______________________
Data delay found: 33
10:15:55:setup_element:INFO: Eye window for uplink 5 : _________XXXXXX_________________________
Data delay found: 31
10:15:55:setup_element:INFO: Eye window for uplink 6 : ____XXXXX_______________________________
Data delay found: 26
10:15:55:setup_element:INFO: Eye window for uplink 7 : __XXXXX_________________________________
Data delay found: 24
10:15:55:setup_element:INFO: Eye window for uplink 8 : ________________________________XXXX____
Data delay found: 13
10:15:55:setup_element:INFO: Eye window for uplink 9 : __________________________________XXXXXX
Data delay found: 16
10:15:55:setup_element:INFO: Eye window for uplink 10: X_________________________________XXXXXX
Data delay found: 17
10:15:55:setup_element:INFO: Eye window for uplink 11: XX_________________________________XXXXX
Data delay found: 18
10:15:55:setup_element:INFO: Eye window for uplink 12: X_________________________________XXXXXX
Data delay found: 17
10:15:55:setup_element:INFO: Eye window for uplink 13: X__________________________________XXXXX
Data delay found: 17
10:15:55:setup_element:INFO: Eye window for uplink 14: X__________________________________XXXXX
Data delay found: 17
10:15:55:setup_element:INFO: Eye window for uplink 15: XX_________________________________XXXXX
Data delay found: 18
10:15:55:setup_element:INFO: Setting the data phase to 36 for uplink 0
10:15:55:setup_element:INFO: Setting the data phase to 34 for uplink 1
10:15:55:setup_element:INFO: Setting the data phase to 32 for uplink 2
10:15:55:setup_element:INFO: Setting the data phase to 33 for uplink 3
10:15:55:setup_element:INFO: Setting the data phase to 33 for uplink 4
10:15:55:setup_element:INFO: Setting the data phase to 31 for uplink 5
10:15:55:setup_element:INFO: Setting the data phase to 26 for uplink 6
10:15:55:setup_element:INFO: Setting the data phase to 24 for uplink 7
10:15:55:setup_element:INFO: Setting the data phase to 13 for uplink 8
10:15:55:setup_element:INFO: Setting the data phase to 16 for uplink 9
10:15:55:setup_element:INFO: Setting the data phase to 17 for uplink 10
10:15:55:setup_element:INFO: Setting the data phase to 18 for uplink 11
10:15:55:setup_element:INFO: Setting the data phase to 17 for uplink 12
10:15:55:setup_element:INFO: Setting the data phase to 17 for uplink 13
10:15:55:setup_element:INFO: Setting the data phase to 17 for uplink 14
10:15:55:setup_element:INFO: Setting the data phase to 18 for uplink 15
==============================================OOO==============================================
10:15:55:setup_element:INFO: Beginning SMX ASICs map scan
10:15:55:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
10:15:55:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
10:15:55:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
10:15:55:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
10:15:55:uplink:INFO: Setting uplinks mask [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
10:15:55:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 1
10:15:55:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 0
10:15:55:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 8
10:15:55:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 9
10:15:55:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 3
10:15:55:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 2
10:15:55:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 10
10:15:56:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 11
10:15:56:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 5
10:15:56:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 4
10:15:56:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 12
10:15:56:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 13
10:15:56:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 7
10:15:56:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 6
10:15:56:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 14
10:15:56:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 15
10:15:58:ST3_emu:INFO:
Setup Element:
Group: 0
Downlink: 1
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 1), (1, 0)
ASIC address 0x1: (ASIC uplink, uplink): (0, 8), (1, 9)
ASIC address 0x2: (ASIC uplink, uplink): (0, 3), (1, 2)
ASIC address 0x3: (ASIC uplink, uplink): (0, 10), (1, 11)
ASIC address 0x4: (ASIC uplink, uplink): (0, 5), (1, 4)
ASIC address 0x5: (ASIC uplink, uplink): (0, 12), (1, 13)
ASIC address 0x6: (ASIC uplink, uplink): (0, 7), (1, 6)
ASIC address 0x7: (ASIC uplink, uplink): (0, 14), (1, 15)
Clock Phase Characteristic:
Optimal Phase: 33
Window Length: 71
Eye Windows:
Uplink 0: _______________________________________________________________________XXXXXXX__
Uplink 1: _______________________________________________________________________XXXXXXX__
Uplink 2: _____________________________________________________________________XXXXXXXX___
Uplink 3: _____________________________________________________________________XXXXXXXX___
Uplink 4: _______________________________________________________________________XXXXXXX__
Uplink 5: _______________________________________________________________________XXXXXXX__
Uplink 6: _______________________________________________________________________XXXXXXX__
Uplink 7: _______________________________________________________________________XXXXXXX__
Uplink 8: _____________________________________________________________________XXXXXXXX___
Uplink 9: _____________________________________________________________________XXXXXXXX___
Uplink 10: _____________________________________________________________________XXXXXXXX___
Uplink 11: _____________________________________________________________________XXXXXXXX___
Uplink 12: ______________________________________________________________________XXXXXXXX__
Uplink 13: ______________________________________________________________________XXXXXXXX__
Uplink 14: ______________________________________________________________________XXXXXXXX__
Uplink 15: ______________________________________________________________________XXXXXXXX__
Data phase characteristics:
Uplink 0:
Optimal Phase: 36
Window Length: 35
Eye Window: ______________XXXXX_____________________
Uplink 1:
Optimal Phase: 34
Window Length: 35
Eye Window: ____________XXXXX_______________________
Uplink 2:
Optimal Phase: 32
Window Length: 36
Eye Window: ___________XXXX_________________________
Uplink 3:
Optimal Phase: 33
Window Length: 35
Eye Window: ___________XXXXX________________________
Uplink 4:
Optimal Phase: 33
Window Length: 34
Eye Window: ___________XXXXXX_______________________
Uplink 5:
Optimal Phase: 31
Window Length: 34
Eye Window: _________XXXXXX_________________________
Uplink 6:
Optimal Phase: 26
Window Length: 35
Eye Window: ____XXXXX_______________________________
Uplink 7:
Optimal Phase: 24
Window Length: 35
Eye Window: __XXXXX_________________________________
Uplink 8:
Optimal Phase: 13
Window Length: 36
Eye Window: ________________________________XXXX____
Uplink 9:
Optimal Phase: 16
Window Length: 34
Eye Window: __________________________________XXXXXX
Uplink 10:
Optimal Phase: 17
Window Length: 33
Eye Window: X_________________________________XXXXXX
Uplink 11:
Optimal Phase: 18
Window Length: 33
Eye Window: XX_________________________________XXXXX
Uplink 12:
Optimal Phase: 17
Window Length: 33
Eye Window: X_________________________________XXXXXX
Uplink 13:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXXX
Uplink 14:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXXX
Uplink 15:
Optimal Phase: 18
Window Length: 33
Eye Window: XX_________________________________XXXXX
==============================================OOO==============================================
10:15:58:setup_element:INFO: Performing Elink synchronization
10:15:58:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
10:15:58:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
10:15:58:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
10:15:58:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
==============================================OOO==============================================
10:15:58:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 1
10:15:58:uplink:INFO: Enabling uplinks [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
==============================================OOO==============================================
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
0 | [0] | 1 | 0 | [1] | 2 | [(0, 1), (1, 0)]
1 | [0] | 1 | 0 | [8] | 2 | [(0, 8), (1, 9)]
2 | [0] | 1 | 0 | [3] | 2 | [(0, 3), (1, 2)]
3 | [0] | 1 | 0 | [10] | 2 | [(0, 10), (1, 11)]
4 | [0] | 1 | 0 | [5] | 2 | [(0, 5), (1, 4)]
5 | [0] | 1 | 0 | [12] | 2 | [(0, 12), (1, 13)]
6 | [0] | 1 | 0 | [7] | 2 | [(0, 7), (1, 6)]
7 | [0] | 1 | 0 | [14] | 2 | [(0, 14), (1, 15)]
|_________________________________________________________________________|
10:15:58:febtest:INFO: Init all SMX (CSA): 30
10:16:13:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
10:16:13:febtest:INFO: 01-00 | XA-000-09-004-007-004-006-08 | 37.7 | 1141.9
10:16:13:febtest:INFO: 08-01 | XA-000-09-004-007-009-007-15 | 28.2 | 1189.2
10:16:14:febtest:INFO: 03-02 | XA-000-09-004-007-005-006-05 | 37.7 | 1159.7
10:16:14:febtest:INFO: 10-03 | XA-000-09-004-007-008-007-02 | 47.3 | 1118.1
10:16:14:febtest:INFO: 05-04 | XA-000-09-004-007-004-007-08 | 40.9 | 1141.9
10:16:14:febtest:INFO: 12-05 | XA-000-09-004-007-005-007-05 | 37.7 | 1147.8
10:16:14:febtest:INFO: 07-06 | XA-000-09-004-007-006-008-11 | 50.4 | 1118.1
10:16:15:febtest:INFO: 14-07 | XA-000-09-004-007-006-007-11 | 34.6 | 1153.7
10:16:16:febtest:INFO: Set all CSA to ZERO
FEB type: A FEB_A: 1 FEB_B: 0
10:16:18:ST3_smx:INFO: chip: 1-0 37.726682 C 1153.732915 mV
10:16:18:ST3_discr_histo:WARNING: Not enough entries for fit!!!
10:16:18:ST3_discr_histo:WARNING: Not enough entries for fit!!!
10:16:18:ST3_smx:INFO: Electrons
10:16:18:ST3_smx:INFO: # loops 0
10:16:20:ST3_smx:INFO: # loops 1
10:16:21:ST3_smx:INFO: # loops 2
10:16:23:ST3_smx:INFO: # loops 3
10:16:25:ST3_smx:INFO: # loops 4
10:16:26:ST3_smx:INFO: Total # of broken channels: 0
10:16:26:ST3_smx:INFO: List of broken channels: []
10:16:26:ST3_smx:INFO: Total # of broken channels: 0
10:16:26:ST3_smx:INFO: List of broken channels: []
10:16:28:ST3_smx:INFO: chip: 8-1 28.225000 C 1200.969315 mV
10:16:28:ST3_discr_histo:WARNING: Not enough entries for fit!!!
10:16:28:ST3_discr_histo:WARNING: Not enough entries for fit!!!
10:16:28:ST3_smx:INFO: Electrons
10:16:28:ST3_smx:INFO: # loops 0
10:16:30:ST3_smx:INFO: # loops 1
10:16:31:ST3_smx:INFO: # loops 2
10:16:33:ST3_smx:INFO: # loops 3
10:16:35:ST3_smx:INFO: # loops 4
10:16:37:ST3_smx:INFO: Total # of broken channels: 0
10:16:37:ST3_smx:INFO: List of broken channels: []
10:16:37:ST3_smx:INFO: Total # of broken channels: 0
10:16:37:ST3_smx:INFO: List of broken channels: []
10:16:38:ST3_smx:INFO: chip: 3-2 37.726682 C 1171.483840 mV
10:16:38:ST3_discr_histo:WARNING: Not enough entries for fit!!!
10:16:38:ST3_discr_histo:WARNING: Not enough entries for fit!!!
10:16:38:ST3_smx:INFO: Electrons
10:16:38:ST3_smx:INFO: # loops 0
10:16:40:ST3_smx:INFO: # loops 1
10:16:42:ST3_smx:INFO: # loops 2
10:16:44:ST3_smx:INFO: # loops 3
10:16:45:ST3_smx:INFO: # loops 4
10:16:47:ST3_smx:INFO: Total # of broken channels: 0
10:16:47:ST3_smx:INFO: List of broken channels: []
10:16:47:ST3_smx:INFO: Total # of broken channels: 1
10:16:47:ST3_smx:INFO: List of broken channels: [118]
10:16:49:ST3_smx:INFO: chip: 10-3 47.250730 C 1129.995435 mV
10:16:49:ST3_discr_histo:WARNING: Not enough entries for fit!!!
10:16:49:ST3_discr_histo:WARNING: Not enough entries for fit!!!
10:16:49:ST3_smx:INFO: Electrons
10:16:49:ST3_smx:INFO: # loops 0
10:16:50:ST3_smx:INFO: # loops 1
10:16:52:ST3_smx:INFO: # loops 2
10:16:54:ST3_smx:INFO: # loops 3
10:16:55:ST3_smx:INFO: # loops 4
10:16:57:ST3_smx:INFO: Total # of broken channels: 0
10:16:57:ST3_smx:INFO: List of broken channels: []
10:16:57:ST3_smx:INFO: Total # of broken channels: 0
10:16:57:ST3_smx:INFO: List of broken channels: []
10:16:59:ST3_smx:INFO: chip: 5-4 40.898880 C 1153.732915 mV
10:16:59:ST3_discr_histo:WARNING: Not enough entries for fit!!!
10:16:59:ST3_discr_histo:WARNING: Not enough entries for fit!!!
10:16:59:ST3_smx:INFO: Electrons
10:16:59:ST3_smx:INFO: # loops 0
10:17:01:ST3_smx:INFO: # loops 1
10:17:02:ST3_smx:INFO: # loops 2
10:17:04:ST3_smx:INFO: # loops 3
10:17:06:ST3_smx:INFO: # loops 4
10:17:07:ST3_smx:INFO: Total # of broken channels: 0
10:17:07:ST3_smx:INFO: List of broken channels: []
10:17:07:ST3_smx:INFO: Total # of broken channels: 0
10:17:07:ST3_smx:INFO: List of broken channels: []
10:17:09:ST3_smx:INFO: chip: 12-5 37.726682 C 1159.654860 mV
10:17:09:ST3_discr_histo:WARNING: Not enough entries for fit!!!
10:17:09:ST3_discr_histo:WARNING: Not enough entries for fit!!!
10:17:09:ST3_smx:INFO: Electrons
10:17:09:ST3_smx:INFO: # loops 0
10:17:11:ST3_smx:INFO: # loops 1
10:17:13:ST3_smx:INFO: # loops 2
10:17:14:ST3_smx:INFO: # loops 3
10:17:16:ST3_smx:INFO: # loops 4
10:17:18:ST3_smx:INFO: Total # of broken channels: 0
10:17:18:ST3_smx:INFO: List of broken channels: []
10:17:18:ST3_smx:INFO: Total # of broken channels: 0
10:17:18:ST3_smx:INFO: List of broken channels: []
10:17:20:ST3_smx:INFO: chip: 7-6 50.430383 C 1129.995435 mV
10:17:20:ST3_discr_histo:WARNING: Not enough entries for fit!!!
10:17:20:ST3_discr_histo:WARNING: Not enough entries for fit!!!
10:17:20:ST3_smx:INFO: Electrons
10:17:20:ST3_smx:INFO: # loops 0
10:17:21:ST3_smx:INFO: # loops 1
10:17:23:ST3_smx:INFO: # loops 2
10:17:24:ST3_smx:INFO: # loops 3
10:17:26:ST3_smx:INFO: # loops 4
10:17:27:ST3_smx:INFO: Total # of broken channels: 0
10:17:27:ST3_smx:INFO: List of broken channels: []
10:17:27:ST3_smx:INFO: Total # of broken channels: 0
10:17:27:ST3_smx:INFO: List of broken channels: []
10:17:29:ST3_smx:INFO: chip: 14-7 37.726682 C 1165.571835 mV
10:17:29:ST3_discr_histo:WARNING: Not enough entries for fit!!!
10:17:29:ST3_discr_histo:WARNING: Not enough entries for fit!!!
10:17:29:ST3_smx:INFO: Electrons
10:17:29:ST3_smx:INFO: # loops 0
10:17:31:ST3_smx:INFO: # loops 1
10:17:32:ST3_smx:INFO: # loops 2
10:17:34:ST3_smx:INFO: # loops 3
10:17:35:ST3_smx:INFO: # loops 4
10:17:37:ST3_smx:INFO: Total # of broken channels: 0
10:17:37:ST3_smx:INFO: List of broken channels: []
10:17:37:ST3_smx:INFO: Total # of broken channels: 0
10:17:37:ST3_smx:INFO: List of broken channels: []
10:17:37:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
10:17:38:febtest:INFO: 01-00 | XA-000-09-004-007-004-006-08 | 37.7 | 1177.4
10:17:38:febtest:INFO: 08-01 | XA-000-09-004-007-009-007-15 | 28.2 | 1236.2
10:17:38:febtest:INFO: 03-02 | XA-000-09-004-007-005-006-05 | 37.7 | 1195.1
10:17:38:febtest:INFO: 10-03 | XA-000-09-004-007-008-007-02 | 47.3 | 1153.7
10:17:38:febtest:INFO: 05-04 | XA-000-09-004-007-004-007-08 | 40.9 | 1177.4
10:17:38:febtest:INFO: 12-05 | XA-000-09-004-007-005-007-05 | 40.9 | 1177.4
10:17:39:febtest:INFO: 07-06 | XA-000-09-004-007-006-008-11 | 50.4 | 1141.9
10:17:39:febtest:INFO: 14-07 | XA-000-09-004-007-006-007-11 | 37.7 | 1183.3
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-Sensor
TEST_DATE : 25_02_03-10_13_58
OPERATOR : Alois Alzheimer
SITE : GSI | SETUP : GSI_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 1325| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_A
AMP_MODE : STS
------------------------------------------------------------
SENSOR_NAME: 17382 | SIZE: 62x42 | GRADE: A
MODULE_NAME: M4UR3B1011311B2
LADDER_NAME: L4UR301131
------------------------------------------------------------
VI_before_Init : ['2.449', '1.5280', '1.849', '2.4230', '0.000', '0.0000', '0.000', '0.0000']
VI_after__Init : ['2.450', '2.0830', '1.850', '2.3650', '0.000', '0.0000', '0.000', '0.0000']
VI_at__the_End : ['2.450', '2.0160', '1.850', '0.5294', '0.000', '0.0000', '0.000', '0.0000']