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FEB_1371 15.01.25 07:39:34
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07:39:34:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
07:39:34:ST3_Shared:INFO: FEB-Sensor
07:39:34:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
07:39:36:ST3_Shared:INFO: STS mode selected
07:39:48:ST3_ModuleSelector:DEBUG: M4UR5T0011330A2
07:39:48:ST3_ModuleSelector:DEBUG: L4UR501133
07:39:48:ST3_ModuleSelector:DEBUG: 03462
07:39:48:ST3_ModuleSelector:DEBUG: 62x42
07:39:48:ST3_ModuleSelector:DEBUG: C
07:39:48:ST3_ModuleSelector:DEBUG: M4UR5T0011330A2
07:39:48:ST3_ModuleSelector:DEBUG: L4UR501133
07:39:48:ST3_ModuleSelector:DEBUG: 03462
07:39:48:ST3_ModuleSelector:DEBUG: 62x42
07:39:48:ST3_ModuleSelector:DEBUG: C
07:40:00:ST3_ModuleSelector:INFO: M4UR5T0011330A2
07:40:00:ST3_ModuleSelector:INFO: 03462
07:40:00:febtest:INFO: Testing FEB with SN 1371
07:40:01:smx_tester:INFO: Scanning setup
07:40:01:elinks:INFO: Disabling clock on downlink 0
07:40:01:elinks:INFO: Disabling clock on downlink 1
07:40:01:elinks:INFO: Disabling clock on downlink 2
07:40:01:elinks:INFO: Disabling clock on downlink 3
07:40:01:elinks:INFO: Disabling clock on downlink 4
07:40:01:setup_element:INFO: Checking SOS, encoding_mode: SOS
07:40:01:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
07:40:02:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
07:40:02:elinks:INFO: Disabling clock on downlink 0
07:40:02:elinks:INFO: Disabling clock on downlink 1
07:40:02:elinks:INFO: Disabling clock on downlink 2
07:40:02:elinks:INFO: Disabling clock on downlink 3
07:40:02:elinks:INFO: Disabling clock on downlink 4
07:40:02:setup_element:INFO: Checking SOS, encoding_mode: SOS
07:40:02:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
07:40:02:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 0
07:40:02:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 1
07:40:02:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 2
07:40:02:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 3
07:40:02:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 4
07:40:02:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 5
07:40:02:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 6
07:40:02:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 7
07:40:02:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 8
07:40:02:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 9
07:40:02:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 10
07:40:02:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 11
07:40:02:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 12
07:40:02:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 13
07:40:02:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 14
07:40:02:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 15
07:40:02:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
07:40:02:elinks:INFO: Disabling clock on downlink 0
07:40:02:elinks:INFO: Disabling clock on downlink 1
07:40:02:elinks:INFO: Disabling clock on downlink 2
07:40:02:elinks:INFO: Disabling clock on downlink 3
07:40:02:elinks:INFO: Disabling clock on downlink 4
07:40:02:setup_element:INFO: Checking SOS, encoding_mode: SOS
07:40:02:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
07:40:02:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
07:40:02:elinks:INFO: Disabling clock on downlink 0
07:40:02:elinks:INFO: Disabling clock on downlink 1
07:40:02:elinks:INFO: Disabling clock on downlink 2
07:40:02:elinks:INFO: Disabling clock on downlink 3
07:40:02:elinks:INFO: Disabling clock on downlink 4
07:40:02:setup_element:INFO: Checking SOS, encoding_mode: SOS
07:40:02:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
07:40:02:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
07:40:02:elinks:INFO: Disabling clock on downlink 0
07:40:02:elinks:INFO: Disabling clock on downlink 1
07:40:02:elinks:INFO: Disabling clock on downlink 2
07:40:02:elinks:INFO: Disabling clock on downlink 3
07:40:02:elinks:INFO: Disabling clock on downlink 4
07:40:02:setup_element:INFO: Checking SOS, encoding_mode: SOS
07:40:02:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
07:40:02:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
==============================================OOO==============================================
07:40:02:setup_element:INFO: Scanning clock phase
07:40:02:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
07:40:02:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
07:40:03:setup_element:INFO: Clock phase scan results for group 0, downlink 1
07:40:03:setup_element:INFO: Eye window for uplink 0 : XXXXXXXXXXXXXXXXXXXXXXX___________________________________________________XXXXXX
Clock Delay: 48
07:40:03:setup_element:INFO: Eye window for uplink 1 : XXXXXXXXXXXXXXXXXXXXXXX___________________________________________________XXXXXX
Clock Delay: 48
07:40:03:setup_element:INFO: Eye window for uplink 2 : XXXXXXXXXXXXXXXXXXX_____________________________________________________________
Clock Delay: 49
07:40:03:setup_element:INFO: Eye window for uplink 3 : XXXXXXXXXXXXXXXXXXX_____________________________________________________________
Clock Delay: 49
07:40:03:setup_element:INFO: Eye window for uplink 4 : XXXXXXXXXXXXXXXXXX______________________________________________________XXXXXXXX
Clock Delay: 44
07:40:03:setup_element:INFO: Eye window for uplink 5 : XXXXXXXXXXXXXXXXXX______________________________________________________XXXXXXXX
Clock Delay: 44
07:40:03:setup_element:INFO: Eye window for uplink 6 : XXXXXXXXXXXXXX__________________________________________________________XXXXXXXX
Clock Delay: 42
07:40:03:setup_element:INFO: Eye window for uplink 7 : XXXXXXXXXXXXXX__________________________________________________________XXXXXXXX
Clock Delay: 42
07:40:03:setup_element:INFO: Eye window for uplink 8 : XXXXXXXX_____________________________________________________________XXXXXXXXXXX
Clock Delay: 38
07:40:03:setup_element:INFO: Eye window for uplink 9 : XXXXXXXX_____________________________________________________________XXXXXXXXXXX
Clock Delay: 38
07:40:03:setup_element:INFO: Eye window for uplink 10: XXXXX________________________________________________________________XXXXXXXXXXX
Clock Delay: 36
07:40:03:setup_element:INFO: Eye window for uplink 11: XXXXX________________________________________________________________XXXXXXXXXXX
Clock Delay: 36
07:40:03:setup_element:INFO: Eye window for uplink 12: XXXXXXXXX_______________________________________________________________________
Clock Delay: 44
07:40:03:setup_element:INFO: Eye window for uplink 13: XXXXXXXXX_______________________________________________________________________
Clock Delay: 44
07:40:03:setup_element:INFO: Eye window for uplink 14: XXXXXXXXX_______________________________________________________________XXXXXXXX
Clock Delay: 40
07:40:03:setup_element:INFO: Eye window for uplink 15: XXXXXXXXX_______________________________________________________________XXXXXXXX
Clock Delay: 40
07:40:03:setup_element:INFO: Setting the clock phase to 45 for group 0, downlink 1
==============================================OOO==============================================
07:40:03:setup_element:INFO: Scanning data phases
07:40:03:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
07:40:03:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
07:40:08:setup_element:INFO: Data phase scan results for group 0, downlink 1
07:40:08:setup_element:INFO: Eye window for uplink 0 : ___XXXXXX_______________________________
Data delay found: 25
07:40:08:setup_element:INFO: Eye window for uplink 1 : XXXXX________________________________XXX
Data delay found: 20
07:40:08:setup_element:INFO: Eye window for uplink 2 : XXXXXX_____________XXXXXX_____________XX
Data delay found: 12
07:40:08:setup_element:INFO: Eye window for uplink 3 : XX_________________XXXXXX__________XXXXX
Data delay found: 10
07:40:08:setup_element:INFO: Eye window for uplink 4 : XX_____________________XXXXXXXXXXXXXXXXX
Data delay found: 12
07:40:08:setup_element:INFO: Eye window for uplink 5 : _______________________XXXXXXXXXXXXXXXXX
Data delay found: 11
07:40:08:setup_element:INFO: Eye window for uplink 6 : ______________________________XXXXX_____
Data delay found: 12
07:40:08:setup_element:INFO: Eye window for uplink 7 : __________________________XXXXX_________
Data delay found: 8
07:40:08:setup_element:INFO: Eye window for uplink 8 : _____________XXXXX______________________
Data delay found: 35
07:40:08:setup_element:INFO: Eye window for uplink 9 : __________________XXXXXX________________
Data delay found: 0
07:40:08:setup_element:INFO: Eye window for uplink 10: _________XXXXXXXXXXXXX__________________
Data delay found: 35
07:40:08:setup_element:INFO: Eye window for uplink 11: _________XXXXXXXXX__XXXXXX______________
Data delay found: 37
07:40:08:setup_element:INFO: Eye window for uplink 12: ______XXXXXXXXXXXXXXXXXX________________
Data delay found: 34
07:40:08:setup_element:INFO: Eye window for uplink 13: ______XXXXXXXXXXXXXXXXXXXXX_____________
Data delay found: 36
07:40:08:setup_element:INFO: Eye window for uplink 14: ____________________XXXXXXX_____________
Data delay found: 3
07:40:08:setup_element:INFO: Eye window for uplink 15: ______________________XXXXXXX___________
Data delay found: 5
07:40:08:setup_element:INFO: Setting the data phase to 25 for uplink 0
07:40:08:setup_element:INFO: Setting the data phase to 20 for uplink 1
07:40:08:setup_element:INFO: Setting the data phase to 12 for uplink 2
07:40:08:setup_element:INFO: Setting the data phase to 10 for uplink 3
07:40:08:setup_element:INFO: Setting the data phase to 12 for uplink 4
07:40:08:setup_element:INFO: Setting the data phase to 11 for uplink 5
07:40:08:setup_element:INFO: Setting the data phase to 12 for uplink 6
07:40:08:setup_element:INFO: Setting the data phase to 8 for uplink 7
07:40:08:setup_element:INFO: Setting the data phase to 35 for uplink 8
07:40:08:setup_element:INFO: Setting the data phase to 0 for uplink 9
07:40:08:setup_element:INFO: Setting the data phase to 35 for uplink 10
07:40:08:setup_element:INFO: Setting the data phase to 37 for uplink 11
07:40:08:setup_element:INFO: Setting the data phase to 34 for uplink 12
07:40:08:setup_element:INFO: Setting the data phase to 36 for uplink 13
07:40:08:setup_element:INFO: Setting the data phase to 3 for uplink 14
07:40:08:setup_element:INFO: Setting the data phase to 5 for uplink 15
==============================================OOO==============================================
07:40:08:setup_element:INFO: Beginning SMX ASICs map scan
07:40:08:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
07:40:08:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
07:40:08:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
07:40:08:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
07:40:08:uplink:INFO: Setting uplinks mask [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
07:40:08:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 1
07:40:08:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 0
07:40:09:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 8
07:40:09:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 9
07:40:09:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 3
07:40:09:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 2
07:40:09:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 10
07:40:09:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 11
07:40:09:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 5
07:40:09:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 4
07:40:09:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 12
07:40:09:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 13
07:40:10:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 7
07:40:10:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 6
07:40:10:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 14
07:40:10:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 15
07:40:11:ST3_emu:INFO:
Setup Element:
Group: 0
Downlink: 1
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 1), (1, 0)
ASIC address 0x1: (ASIC uplink, uplink): (0, 8), (1, 9)
ASIC address 0x2: (ASIC uplink, uplink): (0, 3), (1, 2)
ASIC address 0x3: (ASIC uplink, uplink): (0, 10), (1, 11)
ASIC address 0x4: (ASIC uplink, uplink): (0, 5), (1, 4)
ASIC address 0x5: (ASIC uplink, uplink): (0, 12), (1, 13)
ASIC address 0x6: (ASIC uplink, uplink): (0, 7), (1, 6)
ASIC address 0x7: (ASIC uplink, uplink): (0, 14), (1, 15)
Clock Phase Characteristic:
Optimal Phase: 45
Window Length: 46
Eye Windows:
Uplink 0: XXXXXXXXXXXXXXXXXXXXXXX___________________________________________________XXXXXX
Uplink 1: XXXXXXXXXXXXXXXXXXXXXXX___________________________________________________XXXXXX
Uplink 2: XXXXXXXXXXXXXXXXXXX_____________________________________________________________
Uplink 3: XXXXXXXXXXXXXXXXXXX_____________________________________________________________
Uplink 4: XXXXXXXXXXXXXXXXXX______________________________________________________XXXXXXXX
Uplink 5: XXXXXXXXXXXXXXXXXX______________________________________________________XXXXXXXX
Uplink 6: XXXXXXXXXXXXXX__________________________________________________________XXXXXXXX
Uplink 7: XXXXXXXXXXXXXX__________________________________________________________XXXXXXXX
Uplink 8: XXXXXXXX_____________________________________________________________XXXXXXXXXXX
Uplink 9: XXXXXXXX_____________________________________________________________XXXXXXXXXXX
Uplink 10: XXXXX________________________________________________________________XXXXXXXXXXX
Uplink 11: XXXXX________________________________________________________________XXXXXXXXXXX
Uplink 12: XXXXXXXXX_______________________________________________________________________
Uplink 13: XXXXXXXXX_______________________________________________________________________
Uplink 14: XXXXXXXXX_______________________________________________________________XXXXXXXX
Uplink 15: XXXXXXXXX_______________________________________________________________XXXXXXXX
Data phase characteristics:
Uplink 0:
Optimal Phase: 25
Window Length: 34
Eye Window: ___XXXXXX_______________________________
Uplink 1:
Optimal Phase: 20
Window Length: 32
Eye Window: XXXXX________________________________XXX
Uplink 2:
Optimal Phase: 12
Window Length: 13
Eye Window: XXXXXX_____________XXXXXX_____________XX
Uplink 3:
Optimal Phase: 10
Window Length: 17
Eye Window: XX_________________XXXXXX__________XXXXX
Uplink 4:
Optimal Phase: 12
Window Length: 21
Eye Window: XX_____________________XXXXXXXXXXXXXXXXX
Uplink 5:
Optimal Phase: 11
Window Length: 23
Eye Window: _______________________XXXXXXXXXXXXXXXXX
Uplink 6:
Optimal Phase: 12
Window Length: 35
Eye Window: ______________________________XXXXX_____
Uplink 7:
Optimal Phase: 8
Window Length: 35
Eye Window: __________________________XXXXX_________
Uplink 8:
Optimal Phase: 35
Window Length: 35
Eye Window: _____________XXXXX______________________
Uplink 9:
Optimal Phase: 0
Window Length: 34
Eye Window: __________________XXXXXX________________
Uplink 10:
Optimal Phase: 35
Window Length: 27
Eye Window: _________XXXXXXXXXXXXX__________________
Uplink 11:
Optimal Phase: 37
Window Length: 23
Eye Window: _________XXXXXXXXX__XXXXXX______________
Uplink 12:
Optimal Phase: 34
Window Length: 22
Eye Window: ______XXXXXXXXXXXXXXXXXX________________
Uplink 13:
Optimal Phase: 36
Window Length: 19
Eye Window: ______XXXXXXXXXXXXXXXXXXXXX_____________
Uplink 14:
Optimal Phase: 3
Window Length: 33
Eye Window: ____________________XXXXXXX_____________
Uplink 15:
Optimal Phase: 5
Window Length: 33
Eye Window: ______________________XXXXXXX___________
==============================================OOO==============================================
07:40:11:setup_element:INFO: Performing Elink synchronization
07:40:11:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
07:40:11:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
07:40:11:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
07:40:11:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
==============================================OOO==============================================
07:40:11:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 1
07:40:11:uplink:INFO: Enabling uplinks [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
==============================================OOO==============================================
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
0 | [0] | 1 | 0 | [1] | 2 | [(0, 1), (1, 0)]
1 | [0] | 1 | 0 | [8] | 2 | [(0, 8), (1, 9)]
2 | [0] | 1 | 0 | [3] | 2 | [(0, 3), (1, 2)]
3 | [0] | 1 | 0 | [10] | 2 | [(0, 10), (1, 11)]
4 | [0] | 1 | 0 | [5] | 2 | [(0, 5), (1, 4)]
5 | [0] | 1 | 0 | [12] | 2 | [(0, 12), (1, 13)]
6 | [0] | 1 | 0 | [7] | 2 | [(0, 7), (1, 6)]
7 | [0] | 1 | 0 | [14] | 2 | [(0, 14), (1, 15)]
|_________________________________________________________________________|
07:40:12:febtest:INFO: Init all SMX (CSA): 30
07:40:26:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
07:40:26:febtest:INFO: 01-00 | XA-000-09-004-012-002-013-03 | 28.2 | 1177.4
07:40:26:febtest:INFO: 08-01 | XA-000-09-004-012-003-015-14 | 37.7 | 1141.9
07:40:26:febtest:INFO: 03-02 | XA-000-09-004-012-002-014-03 | 25.1 | 1183.3
07:40:27:febtest:INFO: 10-03 | XA-000-09-004-012-009-027-06 | 15.6 | 1206.9
07:40:27:febtest:INFO: 05-04 | XA-000-09-004-012-003-014-14 | 34.6 | 1159.7
07:40:27:febtest:INFO: 12-05 | XA-000-09-004-012-005-024-12 | 28.2 | 1177.4
07:40:27:febtest:INFO: 07-06 | XA-000-09-004-012-003-013-14 | 25.1 | 1189.2
07:40:28:febtest:INFO: 14-07 | XA-000-09-004-012-005-025-12 | 34.6 | 1147.8
07:40:29:febtest:INFO: Set all CSA to ZERO
FEB type: A FEB_A: 1 FEB_B: 0
07:40:31:ST3_smx:INFO: chip: 1-0 28.225000 C 1189.190035 mV
07:40:31:ST3_discr_histo:WARNING: Not enough entries for fit!!!
07:40:31:ST3_discr_histo:WARNING: Not enough entries for fit!!!
07:40:31:ST3_smx:INFO: Electrons
07:40:31:ST3_smx:INFO: # loops 0
07:40:32:ST3_smx:INFO: # loops 1
07:40:34:ST3_smx:INFO: # loops 2
07:40:35:ST3_smx:INFO: # loops 3
07:40:37:ST3_smx:INFO: # loops 4
07:40:38:ST3_smx:INFO: Total # of broken channels: 0
07:40:38:ST3_smx:INFO: List of broken channels: []
07:40:38:ST3_smx:INFO: Total # of broken channels: 1
07:40:38:ST3_smx:INFO: List of broken channels: [36]
07:40:40:ST3_smx:INFO: chip: 8-1 37.726682 C 1159.654860 mV
07:40:40:ST3_discr_histo:WARNING: Not enough entries for fit!!!
07:40:40:ST3_discr_histo:WARNING: Not enough entries for fit!!!
07:40:40:ST3_smx:INFO: Electrons
07:40:40:ST3_smx:INFO: # loops 0
07:40:42:ST3_smx:INFO: # loops 1
07:40:43:ST3_smx:INFO: # loops 2
07:40:45:ST3_smx:INFO: # loops 3
07:40:46:ST3_smx:INFO: # loops 4
07:40:48:ST3_smx:INFO: Total # of broken channels: 0
07:40:48:ST3_smx:INFO: List of broken channels: []
07:40:48:ST3_smx:INFO: Total # of broken channels: 1
07:40:48:ST3_smx:INFO: List of broken channels: [34]
07:40:50:ST3_smx:INFO: chip: 3-2 28.225000 C 1195.082160 mV
07:40:50:ST3_discr_histo:WARNING: Not enough entries for fit!!!
07:40:50:ST3_discr_histo:WARNING: Not enough entries for fit!!!
07:40:50:ST3_smx:INFO: Electrons
07:40:50:ST3_smx:INFO: # loops 0
07:40:51:ST3_smx:INFO: # loops 1
07:40:53:ST3_smx:INFO: # loops 2
07:40:54:ST3_smx:INFO: # loops 3
07:40:56:ST3_smx:INFO: # loops 4
07:40:57:ST3_smx:INFO: Total # of broken channels: 0
07:40:57:ST3_smx:INFO: List of broken channels: []
07:40:57:ST3_smx:INFO: Total # of broken channels: 7
07:40:57:ST3_smx:INFO: List of broken channels: [6, 22, 42, 44, 56, 72, 78]
07:40:59:ST3_smx:INFO: chip: 10-3 15.590880 C 1212.728715 mV
07:40:59:ST3_discr_histo:WARNING: Not enough entries for fit!!!
07:40:59:ST3_discr_histo:WARNING: Not enough entries for fit!!!
07:40:59:ST3_smx:INFO: Electrons
07:40:59:ST3_smx:INFO: # loops 0
07:41:01:ST3_smx:INFO: # loops 1
07:41:02:ST3_smx:INFO: # loops 2
07:41:04:ST3_smx:INFO: # loops 3
07:41:05:ST3_smx:INFO: # loops 4
07:41:07:ST3_smx:INFO: Total # of broken channels: 0
07:41:07:ST3_smx:INFO: List of broken channels: []
07:41:07:ST3_smx:INFO: Total # of broken channels: 1
07:41:07:ST3_smx:INFO: List of broken channels: [52]
07:41:08:ST3_smx:INFO: chip: 5-4 34.556970 C 1165.571835 mV
07:41:08:ST3_discr_histo:WARNING: Not enough entries for fit!!!
07:41:08:ST3_discr_histo:WARNING: Not enough entries for fit!!!
07:41:08:ST3_smx:INFO: Electrons
07:41:08:ST3_smx:INFO: # loops 0
07:41:10:ST3_smx:INFO: # loops 1
07:41:11:ST3_smx:INFO: # loops 2
07:41:13:ST3_smx:INFO: # loops 3
07:41:15:ST3_smx:INFO: # loops 4
07:41:16:ST3_smx:INFO: Total # of broken channels: 0
07:41:16:ST3_smx:INFO: List of broken channels: []
07:41:16:ST3_smx:INFO: Total # of broken channels: 0
07:41:16:ST3_smx:INFO: List of broken channels: []
07:41:18:ST3_smx:INFO: chip: 12-5 28.225000 C 1189.190035 mV
07:41:18:ST3_discr_histo:WARNING: Not enough entries for fit!!!
07:41:18:ST3_discr_histo:WARNING: Not enough entries for fit!!!
07:41:18:ST3_smx:INFO: Electrons
07:41:18:ST3_smx:INFO: # loops 0
07:41:19:ST3_smx:INFO: # loops 1
07:41:21:ST3_smx:INFO: # loops 2
07:41:22:ST3_smx:INFO: # loops 3
07:41:24:ST3_smx:INFO: # loops 4
07:41:26:ST3_smx:INFO: Total # of broken channels: 0
07:41:26:ST3_smx:INFO: List of broken channels: []
07:41:26:ST3_smx:INFO: Total # of broken channels: 0
07:41:26:ST3_smx:INFO: List of broken channels: []
07:41:27:ST3_smx:INFO: chip: 7-6 25.062742 C 1200.969315 mV
07:41:27:ST3_discr_histo:WARNING: Not enough entries for fit!!!
07:41:27:ST3_discr_histo:WARNING: Not enough entries for fit!!!
07:41:27:ST3_smx:INFO: Electrons
07:41:27:ST3_smx:INFO: # loops 0
07:41:29:ST3_smx:INFO: # loops 1
07:41:30:ST3_smx:INFO: # loops 2
07:41:32:ST3_smx:INFO: # loops 3
07:41:33:ST3_smx:INFO: # loops 4
07:41:35:ST3_smx:INFO: Total # of broken channels: 1
07:41:35:ST3_smx:INFO: List of broken channels: [1]
07:41:35:ST3_smx:INFO: Total # of broken channels: 1
07:41:35:ST3_smx:INFO: List of broken channels: [1]
07:41:37:ST3_smx:INFO: chip: 14-7 34.556970 C 1159.654860 mV
07:41:37:ST3_discr_histo:WARNING: Not enough entries for fit!!!
07:41:37:ST3_discr_histo:WARNING: Not enough entries for fit!!!
07:41:37:ST3_smx:INFO: Electrons
07:41:37:ST3_smx:INFO: # loops 0
07:41:38:ST3_smx:INFO: # loops 1
07:41:40:ST3_smx:INFO: # loops 2
07:41:41:ST3_smx:INFO: # loops 3
07:41:43:ST3_smx:INFO: # loops 4
07:41:44:ST3_smx:INFO: Total # of broken channels: 0
07:41:44:ST3_smx:INFO: List of broken channels: []
07:41:44:ST3_smx:INFO: Total # of broken channels: 0
07:41:44:ST3_smx:INFO: List of broken channels: []
07:41:45:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
07:41:45:febtest:INFO: 01-00 | XA-000-09-004-012-002-013-03 | 28.2 | 1206.9
07:41:45:febtest:INFO: 08-01 | XA-000-09-004-012-003-015-14 | 37.7 | 1177.4
07:41:45:febtest:INFO: 03-02 | XA-000-09-004-012-002-014-03 | 28.2 | 1212.7
07:41:46:febtest:INFO: 10-03 | XA-000-09-004-012-009-027-06 | 18.7 | 1242.0
07:41:46:febtest:INFO: 05-04 | XA-000-09-004-012-003-014-14 | 37.7 | 1189.2
07:41:46:febtest:INFO: 12-05 | XA-000-09-004-012-005-024-12 | 28.2 | 1206.9
07:41:46:febtest:INFO: 07-06 | XA-000-09-004-012-003-013-14 | 25.1 | 1218.6
07:41:47:febtest:INFO: 14-07 | XA-000-09-004-012-005-025-12 | 37.7 | 1177.4
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-Sensor
TEST_DATE : 25_01_15-07_39_34
OPERATOR : Robert V.;
SITE : GSI | SETUP : GSI_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 1371| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_A
AMP_MODE : STS
------------------------------------------------------------
SENSOR_NAME: 03462 | SIZE: 62x42 | GRADE: C
MODULE_NAME: M4UR5T0011330A2
LADDER_NAME: L4UR501133
------------------------------------------------------------
VI_before_Init : ['2.448', '1.4540', '1.849', '2.0270', '0.000', '0.0000', '0.000', '0.0000']
VI_after__Init : ['2.450', '2.0290', '1.850', '2.3870', '0.000', '0.0000', '0.000', '0.0000']
VI_at__the_End : ['2.450', '1.9990', '1.850', '0.5130', '0.000', '0.0000', '0.000', '0.0000']