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FEB_1439 11.06.25 11:02:40
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11:02:40:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
11:02:40:ST3_Shared:INFO: FEB-Microcable
11:02:40:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
11:02:40:febtest:INFO: Testing FEB with SN 1439
==============================================OOO==============================================
11:02:41:smx_tester:INFO: Scanning setup
11:02:42:elinks:INFO: Disabling clock on downlink 0
11:02:42:elinks:INFO: Disabling clock on downlink 1
11:02:42:elinks:INFO: Disabling clock on downlink 2
11:02:42:elinks:INFO: Disabling clock on downlink 3
11:02:42:elinks:INFO: Disabling clock on downlink 4
11:02:42:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:02:42:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
11:02:42:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:02:42:elinks:INFO: Disabling clock on downlink 0
11:02:42:elinks:INFO: Disabling clock on downlink 1
11:02:42:elinks:INFO: Disabling clock on downlink 2
11:02:42:elinks:INFO: Disabling clock on downlink 3
11:02:42:elinks:INFO: Disabling clock on downlink 4
11:02:42:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:02:42:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
11:02:42:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 0
11:02:42:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 1
11:02:42:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 2
11:02:42:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 3
11:02:42:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 4
11:02:42:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 5
11:02:42:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 6
11:02:42:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 7
11:02:42:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 8
11:02:42:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 9
11:02:42:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 10
11:02:42:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 11
11:02:42:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 12
11:02:42:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 13
11:02:42:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 14
11:02:42:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 15
11:02:42:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:02:42:elinks:INFO: Disabling clock on downlink 0
11:02:42:elinks:INFO: Disabling clock on downlink 1
11:02:42:elinks:INFO: Disabling clock on downlink 2
11:02:42:elinks:INFO: Disabling clock on downlink 3
11:02:42:elinks:INFO: Disabling clock on downlink 4
11:02:42:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:02:42:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
11:02:42:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:02:42:elinks:INFO: Disabling clock on downlink 0
11:02:42:elinks:INFO: Disabling clock on downlink 1
11:02:42:elinks:INFO: Disabling clock on downlink 2
11:02:42:elinks:INFO: Disabling clock on downlink 3
11:02:42:elinks:INFO: Disabling clock on downlink 4
11:02:42:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:02:42:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
11:02:42:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:02:42:elinks:INFO: Disabling clock on downlink 0
11:02:42:elinks:INFO: Disabling clock on downlink 1
11:02:42:elinks:INFO: Disabling clock on downlink 2
11:02:42:elinks:INFO: Disabling clock on downlink 3
11:02:42:elinks:INFO: Disabling clock on downlink 4
11:02:42:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:02:42:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
11:02:42:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
==============================================OOO==============================================
11:02:42:setup_element:INFO: Scanning clock phase
11:02:42:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
11:02:42:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
11:02:43:setup_element:INFO: Clock phase scan results for group 0, downlink 1
11:02:43:setup_element:INFO: Eye window for uplink 0 : ________________________________________________________________________XXXXXXX_
Clock Delay: 35
11:02:43:setup_element:INFO: Eye window for uplink 1 : ________________________________________________________________________XXXXXXX_
Clock Delay: 35
11:02:43:setup_element:INFO: Eye window for uplink 2 : _______________________________________________________________________XXXXXX___
Clock Delay: 33
11:02:43:setup_element:INFO: Eye window for uplink 3 : _______________________________________________________________________XXXXXX___
Clock Delay: 33
11:02:43:setup_element:INFO: Eye window for uplink 4 : _____________________________________________________________________XXXXXXXXXX_
Clock Delay: 33
11:02:43:setup_element:INFO: Eye window for uplink 5 : _____________________________________________________________________XXXXXXXXXX_
Clock Delay: 33
11:02:43:setup_element:INFO: Eye window for uplink 6 : ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
11:02:43:setup_element:INFO: Eye window for uplink 7 : ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
11:02:43:setup_element:INFO: Eye window for uplink 8 : _____________________________________________________________________XXXXXXXXX__
Clock Delay: 33
11:02:43:setup_element:INFO: Eye window for uplink 9 : _____________________________________________________________________XXXXXXXXX__
Clock Delay: 33
11:02:43:setup_element:INFO: Eye window for uplink 10: ______________________________________________________________________XXXXXXXXX_
Clock Delay: 34
11:02:43:setup_element:INFO: Eye window for uplink 11: ______________________________________________________________________XXXXXXXXX_
Clock Delay: 34
11:02:43:setup_element:INFO: Eye window for uplink 12: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
11:02:43:setup_element:INFO: Eye window for uplink 13: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
11:02:43:setup_element:INFO: Eye window for uplink 14: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
11:02:43:setup_element:INFO: Eye window for uplink 15: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
11:02:43:setup_element:INFO: Setting the clock phase to 33 for group 0, downlink 1
==============================================OOO==============================================
11:02:43:setup_element:INFO: Scanning data phases
11:02:43:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
11:02:43:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
11:02:48:setup_element:INFO: Data phase scan results for group 0, downlink 1
11:02:48:setup_element:INFO: Eye window for uplink 0 : __________________XXXXX_________________
Data delay found: 0
11:02:48:setup_element:INFO: Eye window for uplink 1 : _______________XXXXXX___________________
Data delay found: 37
11:02:48:setup_element:INFO: Eye window for uplink 2 : ___________XXXX_________________________
Data delay found: 32
11:02:48:setup_element:INFO: Eye window for uplink 3 : ___________XXXXX________________________
Data delay found: 33
11:02:48:setup_element:INFO: Eye window for uplink 4 : ___________XXXXX________________________
Data delay found: 33
11:02:48:setup_element:INFO: Eye window for uplink 5 : _________XXXXX__________________________
Data delay found: 31
11:02:48:setup_element:INFO: Eye window for uplink 6 : ___XXXX_________________________________
Data delay found: 24
11:02:48:setup_element:INFO: Eye window for uplink 7 : _XXXXX_________________________________X
Data delay found: 22
11:02:48:setup_element:INFO: Eye window for uplink 8 : _________________________________XXXXX__
Data delay found: 15
11:02:48:setup_element:INFO: Eye window for uplink 9 : XX__________________________________XXXX
Data delay found: 18
11:02:48:setup_element:INFO: Eye window for uplink 10: XXXX_________________________________XXX
Data delay found: 20
11:02:48:setup_element:INFO: Eye window for uplink 11: XXXXX_________________________________XX
Data delay found: 21
11:02:48:setup_element:INFO: Eye window for uplink 12: XXX_________________________________XXXX
Data delay found: 19
11:02:48:setup_element:INFO: Eye window for uplink 13: XXXX_________________________________XXX
Data delay found: 20
11:02:48:setup_element:INFO: Eye window for uplink 14: XX___________________________________XXX
Data delay found: 19
11:02:48:setup_element:INFO: Eye window for uplink 15: XXX__________________________________XXX
Data delay found: 19
11:02:48:setup_element:INFO: Setting the data phase to 0 for uplink 0
11:02:48:setup_element:INFO: Setting the data phase to 37 for uplink 1
11:02:48:setup_element:INFO: Setting the data phase to 32 for uplink 2
11:02:48:setup_element:INFO: Setting the data phase to 33 for uplink 3
11:02:48:setup_element:INFO: Setting the data phase to 33 for uplink 4
11:02:48:setup_element:INFO: Setting the data phase to 31 for uplink 5
11:02:48:setup_element:INFO: Setting the data phase to 24 for uplink 6
11:02:48:setup_element:INFO: Setting the data phase to 22 for uplink 7
11:02:48:setup_element:INFO: Setting the data phase to 15 for uplink 8
11:02:48:setup_element:INFO: Setting the data phase to 18 for uplink 9
11:02:48:setup_element:INFO: Setting the data phase to 20 for uplink 10
11:02:48:setup_element:INFO: Setting the data phase to 21 for uplink 11
11:02:48:setup_element:INFO: Setting the data phase to 19 for uplink 12
11:02:48:setup_element:INFO: Setting the data phase to 20 for uplink 13
11:02:48:setup_element:INFO: Setting the data phase to 19 for uplink 14
11:02:48:setup_element:INFO: Setting the data phase to 19 for uplink 15
==============================================OOO==============================================
11:02:48:setup_element:INFO: Beginning SMX ASICs map scan
11:02:48:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
11:02:48:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
11:02:48:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
11:02:48:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
11:02:48:uplink:INFO: Setting uplinks mask [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
11:02:48:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 1
11:02:48:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 0
11:02:49:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 8
11:02:49:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 9
11:02:49:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 3
11:02:49:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 2
11:02:49:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 10
11:02:49:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 11
11:02:49:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 5
11:02:49:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 4
11:02:49:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 12
11:02:49:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 13
11:02:49:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 7
11:02:50:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 6
11:02:50:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 14
11:02:50:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 15
11:02:51:ST3_emu:INFO:
Setup Element:
Group: 0
Downlink: 1
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 1), (1, 0)
ASIC address 0x1: (ASIC uplink, uplink): (0, 8), (1, 9)
ASIC address 0x2: (ASIC uplink, uplink): (0, 3), (1, 2)
ASIC address 0x3: (ASIC uplink, uplink): (0, 10), (1, 11)
ASIC address 0x4: (ASIC uplink, uplink): (0, 5), (1, 4)
ASIC address 0x5: (ASIC uplink, uplink): (0, 12), (1, 13)
ASIC address 0x6: (ASIC uplink, uplink): (0, 7), (1, 6)
ASIC address 0x7: (ASIC uplink, uplink): (0, 14), (1, 15)
Clock Phase Characteristic:
Optimal Phase: 33
Window Length: 70
Eye Windows:
Uplink 0: ________________________________________________________________________XXXXXXX_
Uplink 1: ________________________________________________________________________XXXXXXX_
Uplink 2: _______________________________________________________________________XXXXXX___
Uplink 3: _______________________________________________________________________XXXXXX___
Uplink 4: _____________________________________________________________________XXXXXXXXXX_
Uplink 5: _____________________________________________________________________XXXXXXXXXX_
Uplink 6: ______________________________________________________________________XXXXXXXX__
Uplink 7: ______________________________________________________________________XXXXXXXX__
Uplink 8: _____________________________________________________________________XXXXXXXXX__
Uplink 9: _____________________________________________________________________XXXXXXXXX__
Uplink 10: ______________________________________________________________________XXXXXXXXX_
Uplink 11: ______________________________________________________________________XXXXXXXXX_
Uplink 12: _______________________________________________________________________XXXXXXXX_
Uplink 13: _______________________________________________________________________XXXXXXXX_
Uplink 14: _______________________________________________________________________XXXXXXX__
Uplink 15: _______________________________________________________________________XXXXXXX__
Data phase characteristics:
Uplink 0:
Optimal Phase: 0
Window Length: 35
Eye Window: __________________XXXXX_________________
Uplink 1:
Optimal Phase: 37
Window Length: 34
Eye Window: _______________XXXXXX___________________
Uplink 2:
Optimal Phase: 32
Window Length: 36
Eye Window: ___________XXXX_________________________
Uplink 3:
Optimal Phase: 33
Window Length: 35
Eye Window: ___________XXXXX________________________
Uplink 4:
Optimal Phase: 33
Window Length: 35
Eye Window: ___________XXXXX________________________
Uplink 5:
Optimal Phase: 31
Window Length: 35
Eye Window: _________XXXXX__________________________
Uplink 6:
Optimal Phase: 24
Window Length: 36
Eye Window: ___XXXX_________________________________
Uplink 7:
Optimal Phase: 22
Window Length: 33
Eye Window: _XXXXX_________________________________X
Uplink 8:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
Uplink 9:
Optimal Phase: 18
Window Length: 34
Eye Window: XX__________________________________XXXX
Uplink 10:
Optimal Phase: 20
Window Length: 33
Eye Window: XXXX_________________________________XXX
Uplink 11:
Optimal Phase: 21
Window Length: 33
Eye Window: XXXXX_________________________________XX
Uplink 12:
Optimal Phase: 19
Window Length: 33
Eye Window: XXX_________________________________XXXX
Uplink 13:
Optimal Phase: 20
Window Length: 33
Eye Window: XXXX_________________________________XXX
Uplink 14:
Optimal Phase: 19
Window Length: 35
Eye Window: XX___________________________________XXX
Uplink 15:
Optimal Phase: 19
Window Length: 34
Eye Window: XXX__________________________________XXX
==============================================OOO==============================================
11:02:51:setup_element:INFO: Performing Elink synchronization
11:02:51:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
11:02:51:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
11:02:51:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
11:02:51:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
==============================================OOO==============================================
11:02:51:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 1
11:02:51:uplink:INFO: Enabling uplinks [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
==============================================OOO==============================================
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
0 | [0] | 1 | 0 | [1] | 2 | [(0, 1), (1, 0)]
1 | [0] | 1 | 0 | [8] | 2 | [(0, 8), (1, 9)]
2 | [0] | 1 | 0 | [3] | 2 | [(0, 3), (1, 2)]
3 | [0] | 1 | 0 | [10] | 2 | [(0, 10), (1, 11)]
4 | [0] | 1 | 0 | [5] | 2 | [(0, 5), (1, 4)]
5 | [0] | 1 | 0 | [12] | 2 | [(0, 12), (1, 13)]
6 | [0] | 1 | 0 | [7] | 2 | [(0, 7), (1, 6)]
7 | [0] | 1 | 0 | [14] | 2 | [(0, 14), (1, 15)]
|_________________________________________________________________________|
11:02:51:ST3_emu_feb:DEBUG: Chip address: 0x0
11:02:52:ST3_emu_feb:DEBUG: Chip address: 0x1
11:02:52:ST3_emu_feb:DEBUG: Chip address: 0x2
11:02:52:ST3_emu_feb:DEBUG: Chip address: 0x3
11:02:52:ST3_emu_feb:DEBUG: Chip address: 0x4
11:02:52:ST3_emu_feb:DEBUG: Chip address: 0x5
11:02:52:ST3_emu_feb:DEBUG: Chip address: 0x6
11:02:52:ST3_emu_feb:DEBUG: Chip address: 0x7
11:02:52:febtest:INFO: Init all SMX (CSA): 30
11:03:07:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
11:03:07:febtest:INFO: 01-00 | XA-000-09-004-015-005-023-13 | 18.7 | 1183.3
11:03:07:febtest:INFO: 08-01 | XA-000-09-004-015-008-025-10 | 25.1 | 1165.6
11:03:08:febtest:INFO: 03-02 | XA-000-09-004-015-009-021-07 | 37.7 | 1130.0
11:03:08:febtest:INFO: 10-03 | XA-000-09-004-015-015-023-02 | 18.7 | 1183.3
11:03:08:febtest:INFO: 05-04 | XA-000-09-004-009-005-013-08 | 31.4 | 1153.7
11:03:08:febtest:INFO: 12-05 | XA-000-09-004-015-005-025-13 | 25.1 | 1165.6
11:03:08:febtest:INFO: 07-06 | XA-000-09-004-015-011-024-04 | 25.1 | 1171.5
11:03:09:febtest:INFO: 14-07 | XA-000-09-004-015-015-022-02 | 28.2 | 1159.7
11:03:10:febtest:INFO: Set all CSA to ZERO
FEB type: A FEB_A: 1 FEB_B: 0
11:03:12:ST3_smx:INFO: chip: 1-0 18.745682 C 1195.082160 mV
11:03:12:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:03:12:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:03:12:ST3_smx:INFO: Electrons
11:03:17:ST3_smx:INFO: Total # of broken channels: 3
11:03:17:ST3_smx:INFO: List of broken channels: [12, 77, 88]
11:03:17:ST3_smx:INFO: Total # of broken channels: 0
11:03:17:ST3_smx:INFO: List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
11:03:18:ST3_smx:INFO: chip: 8-1 25.062742 C 1189.190035 mV
11:03:18:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:03:18:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:03:18:ST3_smx:INFO: Electrons
11:03:23:ST3_smx:INFO: Total # of broken channels: 3
11:03:23:ST3_smx:INFO: List of broken channels: [5, 19, 118]
11:03:23:ST3_smx:INFO: Total # of broken channels: 0
11:03:23:ST3_smx:INFO: List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
11:03:25:ST3_smx:INFO: chip: 3-2 37.726682 C 1141.874115 mV
11:03:25:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:03:25:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:03:25:ST3_smx:INFO: Electrons
11:03:30:ST3_smx:INFO: Total # of broken channels: 6
11:03:30:ST3_smx:INFO: List of broken channels: [33, 50, 67, 84, 88, 126]
11:03:30:ST3_smx:INFO: Total # of broken channels: 0
11:03:30:ST3_smx:INFO: List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
11:03:32:ST3_smx:INFO: chip: 10-3 18.745682 C 1200.969315 mV
11:03:32:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:03:32:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:03:32:ST3_smx:INFO: Electrons
11:03:36:ST3_smx:INFO: Total # of broken channels: 2
11:03:36:ST3_smx:INFO: List of broken channels: [103, 111]
11:03:36:ST3_smx:INFO: Total # of broken channels: 0
11:03:36:ST3_smx:INFO: List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
11:03:38:ST3_smx:INFO: chip: 5-4 31.389742 C 1165.571835 mV
11:03:38:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:03:38:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:03:38:ST3_smx:INFO: Electrons
11:03:43:ST3_smx:INFO: Total # of broken channels: 6
11:03:43:ST3_smx:INFO: List of broken channels: [17, 41, 74, 88, 122, 123]
11:03:43:ST3_smx:INFO: Total # of broken channels: 0
11:03:43:ST3_smx:INFO: List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
11:03:45:ST3_smx:INFO: chip: 12-5 25.062742 C 1177.390875 mV
11:03:45:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:03:45:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:03:45:ST3_smx:INFO: Electrons
11:03:50:ST3_smx:INFO: Total # of broken channels: 9
11:03:50:ST3_smx:INFO: List of broken channels: [9, 23, 26, 65, 72, 73, 86, 99, 101]
11:03:50:ST3_smx:INFO: Total # of broken channels: 0
11:03:50:ST3_smx:INFO: List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
11:03:51:ST3_smx:INFO: chip: 7-6 28.225000 C 1177.390875 mV
11:03:51:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:03:51:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:03:51:ST3_smx:INFO: Electrons
11:03:56:ST3_smx:INFO: Total # of broken channels: 4
11:03:56:ST3_smx:INFO: List of broken channels: [39, 41, 111, 116]
11:03:56:ST3_smx:INFO: Total # of broken channels: 0
11:03:56:ST3_smx:INFO: List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
11:03:58:ST3_smx:INFO: chip: 14-7 28.225000 C 1171.483840 mV
11:03:58:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:03:58:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:03:58:ST3_smx:INFO: Electrons
11:04:03:ST3_smx:INFO: Total # of broken channels: 7
11:04:03:ST3_smx:INFO: List of broken channels: [8, 26, 29, 41, 96, 113, 127]
11:04:03:ST3_smx:INFO: Total # of broken channels: 0
11:04:03:ST3_smx:INFO: List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
11:04:03:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
11:04:03:febtest:INFO: 01-00 | XA-000-09-004-015-005-023-13 | 21.9 | 1212.7
11:04:04:febtest:INFO: 08-01 | XA-000-09-004-015-008-025-10 | 25.1 | 1288.7
11:04:04:febtest:INFO: 03-02 | XA-000-09-004-015-009-021-07 | 40.9 | 1165.6
11:04:04:febtest:INFO: 10-03 | XA-000-09-004-015-015-023-02 | 18.7 | 1224.5
11:04:04:febtest:INFO: 05-04 | XA-000-09-004-009-005-013-08 | 34.6 | 1183.3
11:04:05:febtest:INFO: 12-05 | XA-000-09-004-015-005-025-13 | 28.2 | 1195.1
11:04:05:febtest:INFO: 07-06 | XA-000-09-004-015-011-024-04 | 31.4 | 1201.0
11:04:05:febtest:INFO: 14-07 | XA-000-09-004-015-015-022-02 | 31.4 | 1189.2
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-Microcable
TEST_DATE : 25_06_11-11_02_40
OPERATOR : Oleksandr S.; Robert V.;
SITE : GSI | SETUP : GSI_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 1439| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_A
AMP_MODE : STS
------------------------------------------------------------
------------------------------------------------------------
VI_before_Init : ['2.449', '1.8910', '1.849', '2.2240', '0.000', '0.0000', '0.000', '0.0000']
VI_after__Init : ['2.450', '1.9870', '1.850', '2.3010', '0.000', '0.0000', '0.000', '0.0000']
VI_at__the_End : ['2.450', '1.9680', '1.850', '0.5205', '0.000', '0.0000', '0.000', '0.0000']