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FEB_162 31.10.24 11:28:11
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11:28:11:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
11:28:11:ST3_Shared:INFO: FEB-Microcable
11:28:11:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
11:28:11:febtest:INFO: Testing FEB with SN 162
11:28:13:smx_tester:INFO: Scanning setup
11:28:13:elinks:INFO: Disabling clock on downlink 0
11:28:13:elinks:INFO: Disabling clock on downlink 1
11:28:13:elinks:INFO: Disabling clock on downlink 2
11:28:13:elinks:INFO: Disabling clock on downlink 3
11:28:13:elinks:INFO: Disabling clock on downlink 4
11:28:13:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:28:13:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
11:28:13:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:28:13:elinks:INFO: Disabling clock on downlink 0
11:28:13:elinks:INFO: Disabling clock on downlink 1
11:28:13:elinks:INFO: Disabling clock on downlink 2
11:28:13:elinks:INFO: Disabling clock on downlink 3
11:28:13:elinks:INFO: Disabling clock on downlink 4
11:28:13:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:28:13:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
11:28:13:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:28:13:elinks:INFO: Disabling clock on downlink 0
11:28:13:elinks:INFO: Disabling clock on downlink 1
11:28:13:elinks:INFO: Disabling clock on downlink 2
11:28:13:elinks:INFO: Disabling clock on downlink 3
11:28:13:elinks:INFO: Disabling clock on downlink 4
11:28:13:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:28:13:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
11:28:14:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:28:14:elinks:INFO: Disabling clock on downlink 0
11:28:14:elinks:INFO: Disabling clock on downlink 1
11:28:14:elinks:INFO: Disabling clock on downlink 2
11:28:14:elinks:INFO: Disabling clock on downlink 3
11:28:14:elinks:INFO: Disabling clock on downlink 4
11:28:14:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:28:14:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
11:28:14:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:28:14:elinks:INFO: Disabling clock on downlink 0
11:28:14:elinks:INFO: Disabling clock on downlink 1
11:28:14:elinks:INFO: Disabling clock on downlink 2
11:28:14:elinks:INFO: Disabling clock on downlink 3
11:28:14:elinks:INFO: Disabling clock on downlink 4
11:28:14:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:28:14:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
11:28:14:setup_element:INFO: SOS detected for group 0, downlink 4, uplink 32
11:28:14:setup_element:INFO: SOS detected for group 0, downlink 4, uplink 33
11:28:14:setup_element:INFO: SOS detected for group 0, downlink 4, uplink 34
11:28:14:setup_element:INFO: SOS detected for group 0, downlink 4, uplink 35
11:28:14:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
==============================================OOO==============================================
11:28:14:setup_element:INFO: Scanning clock phase
11:28:14:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
11:28:14:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [4]
11:28:14:setup_element:INFO: Clock phase scan results for group 0, downlink 4
11:28:14:setup_element:INFO: Eye window for uplink 32: X__________________________________________________________________________XXXXX
Clock Delay: 37
11:28:14:setup_element:INFO: Eye window for uplink 33: X_________________________________________________________________________XXXXXX
Clock Delay: 37
11:28:14:setup_element:INFO: Eye window for uplink 34: XX_________________________________________________________________________XXXXX
Clock Delay: 38
11:28:14:setup_element:INFO: Eye window for uplink 35: XXX_________________________________________________________________________XXXX
Clock Delay: 39
11:28:14:setup_element:INFO: Setting the clock phase to 38 for group 0, downlink 4
==============================================OOO==============================================
11:28:14:setup_element:INFO: Scanning data phases
11:28:14:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
11:28:14:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [4]
11:28:19:setup_element:INFO: Data phase scan results for group 0, downlink 4
11:28:19:setup_element:INFO: Eye window for uplink 32: XXXX__________________________________XX
Data delay found: 20
11:28:19:setup_element:INFO: Eye window for uplink 33: XX_________________________________XXXXX
Data delay found: 18
11:28:19:setup_element:INFO: Eye window for uplink 34: XXXX__________________________________XX
Data delay found: 20
11:28:19:setup_element:INFO: Eye window for uplink 35: _XXXXXX_________________________________
Data delay found: 23
11:28:19:setup_element:INFO: Setting the data phase to 20 for uplink 32
11:28:19:setup_element:INFO: Setting the data phase to 18 for uplink 33
11:28:19:setup_element:INFO: Setting the data phase to 20 for uplink 34
11:28:19:setup_element:INFO: Setting the data phase to 23 for uplink 35
==============================================OOO==============================================
11:28:19:setup_element:INFO: Beginning SMX ASICs map scan
11:28:19:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
11:28:19:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [4]
11:28:19:master:INFO: Setting encoding mode EOS for groups [0], downlinks [4]
11:28:19:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [4]
11:28:19:uplink:INFO: Setting uplinks mask [32, 33, 34, 35]
11:28:19:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 32
11:28:20:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 33
11:28:20:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 34
11:28:20:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 35
11:28:22:ST3_emu:INFO:
Setup Element:
Group: 0
Downlink: 4
Uplinks: [32, 33, 34, 35]
ASICs Map:
ASIC address 0x1: (ASIC uplink, uplink): (0, 32)
ASIC address 0x3: (ASIC uplink, uplink): (0, 33)
ASIC address 0x5: (ASIC uplink, uplink): (0, 34)
ASIC address 0x7: (ASIC uplink, uplink): (0, 35)
Clock Phase Characteristic:
Optimal Phase: 38
Window Length: 71
Eye Windows:
Uplink 32: X__________________________________________________________________________XXXXX
Uplink 33: X_________________________________________________________________________XXXXXX
Uplink 34: XX_________________________________________________________________________XXXXX
Uplink 35: XXX_________________________________________________________________________XXXX
Data phase characteristics:
Uplink 32:
Optimal Phase: 20
Window Length: 34
Eye Window: XXXX__________________________________XX
Uplink 33:
Optimal Phase: 18
Window Length: 33
Eye Window: XX_________________________________XXXXX
Uplink 34:
Optimal Phase: 20
Window Length: 34
Eye Window: XXXX__________________________________XX
Uplink 35:
Optimal Phase: 23
Window Length: 34
Eye Window: _XXXXXX_________________________________
==============================================OOO==============================================
11:28:22:setup_element:INFO: Performing Elink synchronization
11:28:22:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
11:28:22:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [4]
11:28:22:master:INFO: Setting encoding mode EOS for groups [0], downlinks [4]
11:28:22:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [4]
==============================================OOO==============================================
11:28:22:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 4
11:28:22:uplink:INFO: Enabling uplinks [32, 33, 34, 35]
==============================================OOO==============================================
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
1 | [0] | 4 | 0 | [32] | 1 | [(0, 32)]
3 | [0] | 4 | 0 | [33] | 1 | [(0, 33)]
5 | [0] | 4 | 0 | [34] | 1 | [(0, 34)]
7 | [0] | 4 | 0 | [35] | 1 | [(0, 35)]
|_________________________________________________________________________|
11:28:22:febtest:INFO: Init all SMX (CSA): 30
11:28:29:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
11:28:29:febtest:INFO: 32-01 | XA-000-09-004-012-011-014-02 | 28.2 | 1153.7
11:28:30:febtest:INFO: 33-03 | XA-000-09-004-012-012-012-10 | 25.1 | 1153.7
11:28:30:febtest:INFO: 34-05 | XA-000-09-004-012-007-010-08 | 9.3 | 1201.0
11:28:30:febtest:INFO: 35-07 | XA-000-09-004-012-007-005-08 | 18.7 | 1165.6
11:28:31:febtest:INFO: Set all CSA to ZERO
FEB type: A FEB_A: 1 FEB_B: 0
11:28:33:ST3_smx:INFO: chip: 32-1 28.225000 C 1165.571835 mV
11:28:33:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:28:33:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:28:33:ST3_smx:INFO: Electrons
11:28:33:ST3_smx:INFO: # loops 0
11:28:34:ST3_smx:INFO: # loops 1
11:28:36:ST3_smx:INFO: # loops 2
11:28:38:ST3_smx:INFO: Total # of broken channels: 0
11:28:38:ST3_smx:INFO: List of broken channels: []
11:28:38:ST3_smx:INFO: Total # of broken channels: 0
11:28:38:ST3_smx:INFO: List of broken channels: []
11:28:40:ST3_smx:INFO: chip: 33-3 25.062742 C 1165.571835 mV
11:28:40:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:28:40:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:28:40:ST3_smx:INFO: Electrons
11:28:40:ST3_smx:INFO: # loops 0
11:28:41:ST3_smx:INFO: # loops 1
11:28:43:ST3_smx:INFO: # loops 2
11:28:45:ST3_smx:INFO: Total # of broken channels: 0
11:28:45:ST3_smx:INFO: List of broken channels: []
11:28:45:ST3_smx:INFO: Total # of broken channels: 0
11:28:45:ST3_smx:INFO: List of broken channels: []
11:28:46:ST3_smx:INFO: chip: 34-5 9.288730 C 1212.728715 mV
11:28:46:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:28:46:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:28:46:ST3_smx:INFO: Electrons
11:28:46:ST3_smx:INFO: # loops 0
11:28:48:ST3_smx:INFO: # loops 1
11:28:50:ST3_smx:INFO: # loops 2
11:28:51:ST3_smx:INFO: Total # of broken channels: 0
11:28:51:ST3_smx:INFO: List of broken channels: []
11:28:51:ST3_smx:INFO: Total # of broken channels: 0
11:28:51:ST3_smx:INFO: List of broken channels: []
11:28:53:ST3_smx:INFO: chip: 35-7 21.902970 C 1177.390875 mV
11:28:53:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:28:53:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:28:53:ST3_smx:INFO: Electrons
11:28:53:ST3_smx:INFO: # loops 0
11:28:55:ST3_smx:INFO: # loops 1
11:28:57:ST3_smx:INFO: # loops 2
11:28:58:ST3_smx:INFO: Total # of broken channels: 0
11:28:58:ST3_smx:INFO: List of broken channels: []
11:28:58:ST3_smx:INFO: Total # of broken channels: 0
11:28:58:ST3_smx:INFO: List of broken channels: []
11:28:59:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
11:28:59:febtest:INFO: 32-01 | XA-000-09-004-012-011-014-02 | 28.2 | 1189.2
11:28:59:febtest:INFO: 33-03 | XA-000-09-004-012-012-012-10 | 28.2 | 1183.3
11:28:59:febtest:INFO: 34-05 | XA-000-09-004-012-007-010-08 | 9.3 | 1230.3
11:28:59:febtest:INFO: 35-07 | XA-000-09-004-012-007-005-08 | 21.9 | 1201.0
############################################################
# S U M M A R Y #
############################################################
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-Microcable
TEST_DATE : 24_10_31-11_28_11
OPERATOR : Alois Alzheimer
SITE : GSI | SETUP : GSI_TEST_SETUP_2
------------------------------------------------------------
| FEB_SN : 162| FEB_TYPE : 8.1| FEB_UPLINKS : 1| FEB_A
------------------------------------------------------------
------------------------------------------------------------
VI_before_Init : ['2.447', '0.9729', '1.851', '1.2400', '0.000', '0.0000', '0.000', '0.0000']
VI_after__Init : ['2.450', '1.0150', '1.850', '1.1180', '0.000', '0.0000', '0.000', '0.0000']
VI_at__the_End : ['2.450', '0.9918', '1.850', '0.2679', '0.000', '0.0000', '0.000', '0.0000']
11:29:05:ST3_Shared:INFO: Listo of operators:Robert V.;
11:29:06:ST3_Shared:INFO: Listo of operators:Alois Alzheimer
11:29:07:ST3_Shared:INFO: Listo of operators:Robert V.;