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FEB_163 31.10.24 14:40:18
TextEdit.txt
14:40:18:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:40:18:ST3_Shared:INFO: FEB-Microcable
14:40:18:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:40:18:febtest:INFO: Testing FEB with SN 163
14:40:19:smx_tester:INFO: Scanning setup
14:40:19:elinks:INFO: Disabling clock on downlink 0
14:40:19:elinks:INFO: Disabling clock on downlink 1
14:40:19:elinks:INFO: Disabling clock on downlink 2
14:40:19:elinks:INFO: Disabling clock on downlink 3
14:40:19:elinks:INFO: Disabling clock on downlink 4
14:40:19:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:40:19:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
14:40:20:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:40:20:elinks:INFO: Disabling clock on downlink 0
14:40:20:elinks:INFO: Disabling clock on downlink 1
14:40:20:elinks:INFO: Disabling clock on downlink 2
14:40:20:elinks:INFO: Disabling clock on downlink 3
14:40:20:elinks:INFO: Disabling clock on downlink 4
14:40:20:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:40:20:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
14:40:20:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:40:20:elinks:INFO: Disabling clock on downlink 0
14:40:20:elinks:INFO: Disabling clock on downlink 1
14:40:20:elinks:INFO: Disabling clock on downlink 2
14:40:20:elinks:INFO: Disabling clock on downlink 3
14:40:20:elinks:INFO: Disabling clock on downlink 4
14:40:20:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:40:20:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
14:40:20:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:40:20:elinks:INFO: Disabling clock on downlink 0
14:40:20:elinks:INFO: Disabling clock on downlink 1
14:40:20:elinks:INFO: Disabling clock on downlink 2
14:40:20:elinks:INFO: Disabling clock on downlink 3
14:40:20:elinks:INFO: Disabling clock on downlink 4
14:40:20:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:40:20:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
14:40:20:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:40:20:elinks:INFO: Disabling clock on downlink 0
14:40:20:elinks:INFO: Disabling clock on downlink 1
14:40:20:elinks:INFO: Disabling clock on downlink 2
14:40:20:elinks:INFO: Disabling clock on downlink 3
14:40:20:elinks:INFO: Disabling clock on downlink 4
14:40:20:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:40:20:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
14:40:20:setup_element:INFO: SOS detected for group 0, downlink 4, uplink 32
14:40:20:setup_element:INFO: SOS detected for group 0, downlink 4, uplink 33
14:40:20:setup_element:INFO: SOS detected for group 0, downlink 4, uplink 34
14:40:20:setup_element:INFO: SOS detected for group 0, downlink 4, uplink 35
14:40:20:setup_element:INFO: SOS detected for group 0, downlink 4, uplink 36
14:40:20:setup_element:INFO: SOS detected for group 0, downlink 4, uplink 37
14:40:20:setup_element:INFO: SOS detected for group 0, downlink 4, uplink 38
14:40:20:setup_element:INFO: SOS detected for group 0, downlink 4, uplink 39
14:40:20:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
==============================================OOO==============================================
14:40:20:setup_element:INFO: Scanning clock phase
14:40:20:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
14:40:20:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [4]
14:40:21:setup_element:INFO: Clock phase scan results for group 0, downlink 4
14:40:21:setup_element:INFO: Eye window for uplink 32: X__________________________________________________________________________XXXXX
Clock Delay: 37
14:40:21:setup_element:INFO: Eye window for uplink 33: X_______________________________________________________________________________
Clock Delay: 40
14:40:21:setup_element:INFO: Eye window for uplink 34: X_______________________________________________________________________________
Clock Delay: 40
14:40:21:setup_element:INFO: Eye window for uplink 35: XX______________________________________________________________________________
Clock Delay: 40
14:40:21:setup_element:INFO: Eye window for uplink 36: X_________________________________________________________________________XXXXXX
Clock Delay: 37
14:40:21:setup_element:INFO: Eye window for uplink 37: XX_________________________________________________________________________XXXXX
Clock Delay: 38
14:40:21:setup_element:INFO: Eye window for uplink 38: __________________________________________________________________________XXXXXX
Clock Delay: 36
14:40:21:setup_element:INFO: Eye window for uplink 39: XX_________________________________________________________________________XXXXX
Clock Delay: 38
14:40:21:setup_element:INFO: Setting the clock phase to 37 for group 0, downlink 4
==============================================OOO==============================================
14:40:21:setup_element:INFO: Scanning data phases
14:40:21:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
14:40:21:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [4]
14:40:26:setup_element:INFO: Data phase scan results for group 0, downlink 4
14:40:26:setup_element:INFO: Eye window for uplink 32: X__________________________________XXXXX
Data delay found: 17
14:40:26:setup_element:INFO: Eye window for uplink 33: _______XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Data delay found: 3
14:40:26:setup_element:INFO: Eye window for uplink 34: ____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Data delay found: 1
14:40:26:setup_element:INFO: Eye window for uplink 35: XXXX_________XXXXXXXXXXXXXXXXXXXXXXXXXXX
Data delay found: 8
14:40:26:setup_element:INFO: Eye window for uplink 36: ___XXXXX________________________________
Data delay found: 25
14:40:26:setup_element:INFO: Eye window for uplink 37: __XXXXX_________________________________
Data delay found: 24
14:40:26:setup_element:INFO: Eye window for uplink 38: ___________________________________XXXX_
Data delay found: 16
14:40:26:setup_element:INFO: Eye window for uplink 39: XX___________________________________XXX
Data delay found: 19
14:40:26:setup_element:INFO: Setting the data phase to 17 for uplink 32
14:40:26:setup_element:INFO: Setting the data phase to 3 for uplink 33
14:40:26:setup_element:INFO: Setting the data phase to 1 for uplink 34
14:40:26:setup_element:INFO: Setting the data phase to 8 for uplink 35
14:40:26:setup_element:INFO: Setting the data phase to 25 for uplink 36
14:40:26:setup_element:INFO: Setting the data phase to 24 for uplink 37
14:40:26:setup_element:INFO: Setting the data phase to 16 for uplink 38
14:40:26:setup_element:INFO: Setting the data phase to 19 for uplink 39
==============================================OOO==============================================
14:40:26:setup_element:INFO: Beginning SMX ASICs map scan
14:40:26:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
14:40:26:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [4]
14:40:26:master:INFO: Setting encoding mode EOS for groups [0], downlinks [4]
14:40:26:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [4]
14:40:26:uplink:INFO: Setting uplinks mask [32, 33, 34, 35, 36, 37, 38, 39]
14:40:26:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 36
14:40:26:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 32
14:40:26:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 37
14:40:27:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 33
14:40:27:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 38
14:40:27:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 34
14:40:27:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 39
14:40:27:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 35
14:40:29:ST3_emu:INFO:
Setup Element:
Group: 0
Downlink: 4
Uplinks: [32, 33, 34, 35, 36, 37, 38, 39]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 36)
ASIC address 0x1: (ASIC uplink, uplink): (0, 32)
ASIC address 0x2: (ASIC uplink, uplink): (0, 37)
ASIC address 0x3: (ASIC uplink, uplink): (0, 33)
ASIC address 0x4: (ASIC uplink, uplink): (0, 38)
ASIC address 0x5: (ASIC uplink, uplink): (0, 34)
ASIC address 0x6: (ASIC uplink, uplink): (0, 39)
ASIC address 0x7: (ASIC uplink, uplink): (0, 35)
Clock Phase Characteristic:
Optimal Phase: 37
Window Length: 72
Eye Windows:
Uplink 32: X__________________________________________________________________________XXXXX
Uplink 33: X_______________________________________________________________________________
Uplink 34: X_______________________________________________________________________________
Uplink 35: XX______________________________________________________________________________
Uplink 36: X_________________________________________________________________________XXXXXX
Uplink 37: XX_________________________________________________________________________XXXXX
Uplink 38: __________________________________________________________________________XXXXXX
Uplink 39: XX_________________________________________________________________________XXXXX
Data phase characteristics:
Uplink 32:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXXX
Uplink 33:
Optimal Phase: 3
Window Length: 7
Eye Window: _______XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Uplink 34:
Optimal Phase: 1
Window Length: 4
Eye Window: ____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Uplink 35:
Optimal Phase: 8
Window Length: 9
Eye Window: XXXX_________XXXXXXXXXXXXXXXXXXXXXXXXXXX
Uplink 36:
Optimal Phase: 25
Window Length: 35
Eye Window: ___XXXXX________________________________
Uplink 37:
Optimal Phase: 24
Window Length: 35
Eye Window: __XXXXX_________________________________
Uplink 38:
Optimal Phase: 16
Window Length: 36
Eye Window: ___________________________________XXXX_
Uplink 39:
Optimal Phase: 19
Window Length: 35
Eye Window: XX___________________________________XXX
==============================================OOO==============================================
14:40:29:setup_element:INFO: Performing Elink synchronization
14:40:29:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
14:40:29:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [4]
14:40:29:master:INFO: Setting encoding mode EOS for groups [0], downlinks [4]
14:40:29:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [4]
==============================================OOO==============================================
14:40:29:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 4
14:40:29:uplink:INFO: Enabling uplinks [32, 33, 34, 35, 36, 37, 38, 39]
==============================================OOO==============================================
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
0 | [0] | 4 | 0 | [36] | 1 | [(0, 36)]
1 | [0] | 4 | 0 | [32] | 1 | [(0, 32)]
2 | [0] | 4 | 0 | [37] | 1 | [(0, 37)]
3 | [0] | 4 | 0 | [33] | 1 | [(0, 33)]
4 | [0] | 4 | 0 | [38] | 1 | [(0, 38)]
5 | [0] | 4 | 0 | [34] | 1 | [(0, 34)]
6 | [0] | 4 | 0 | [39] | 1 | [(0, 39)]
7 | [0] | 4 | 0 | [35] | 1 | [(0, 35)]
|_________________________________________________________________________|
14:40:30:febtest:INFO: Init all SMX (CSA): 30
14:40:44:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:40:44:febtest:INFO: 36-00 | XA-000-09-004-012-010-015-15 | 44.1 | 1153.7
14:40:44:febtest:INFO: 32-01 | XA-000-09-004-012-008-010-12 | 44.1 | 1135.9
14:40:45:febtest:INFO: 37-02 | XA-000-09-004-012-012-013-10 | 47.3 | 1141.9
14:40:45:febtest:INFO: 33-03 | XA-000-09-004-012-007-009-08 | 28.2 | 1201.0
14:40:45:febtest:INFO: 38-04 | XA-000-09-004-012-011-012-02 | 44.1 | 1153.7
14:40:45:febtest:INFO: 34-05 | XA-000-09-004-012-009-012-01 | 28.2 | 1189.2
14:40:45:febtest:INFO: 39-06 | XA-000-09-004-012-007-011-08 | 47.3 | 1135.9
14:40:46:febtest:INFO: 35-07 | XA-000-09-004-012-009-010-01 | 37.7 | 1159.7
14:40:47:febtest:INFO: Set all CSA to ZERO
FEB type: A FEB_A: 1 FEB_B: 0
14:40:49:ST3_smx:INFO: chip: 36-0 44.073563 C 1171.483840 mV
14:40:49:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:40:49:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:40:49:ST3_smx:INFO: Electrons
14:40:49:ST3_smx:INFO: # loops 0
14:40:50:ST3_smx:INFO: # loops 1
14:40:52:ST3_smx:INFO: # loops 2
14:40:54:ST3_smx:INFO: Total # of broken channels: 0
14:40:54:ST3_smx:INFO: List of broken channels: []
14:40:54:ST3_smx:INFO: Total # of broken channels: 64
14:40:54:ST3_smx:INFO: List of broken channels: [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31, 33, 35, 37, 39, 41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 61, 63, 65, 67, 69, 71, 73, 75, 77, 79, 81, 83, 85, 87, 89, 91, 93, 95, 97, 99, 101, 103, 105, 107, 109, 111, 113, 115, 117, 119, 121, 123, 125, 127]
14:40:56:ST3_smx:INFO: chip: 32-1 44.073563 C 1153.732915 mV
14:40:56:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:40:56:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:40:56:ST3_smx:INFO: Electrons
14:40:56:ST3_smx:INFO: # loops 0
14:40:57:ST3_smx:INFO: # loops 1
14:40:59:ST3_smx:INFO: # loops 2
14:41:01:ST3_smx:INFO: Total # of broken channels: 0
14:41:01:ST3_smx:INFO: List of broken channels: []
14:41:01:ST3_smx:INFO: Total # of broken channels: 0
14:41:01:ST3_smx:INFO: List of broken channels: []
14:41:02:ST3_smx:INFO: chip: 37-2 47.250730 C 1159.654860 mV
14:41:02:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:41:02:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:41:02:ST3_smx:INFO: Electrons
14:41:02:ST3_smx:INFO: # loops 0
14:41:04:ST3_smx:INFO: # loops 1
14:41:06:ST3_smx:INFO: # loops 2
14:41:07:ST3_smx:INFO: Total # of broken channels: 0
14:41:07:ST3_smx:INFO: List of broken channels: []
14:41:07:ST3_smx:INFO: Total # of broken channels: 0
14:41:07:ST3_smx:INFO: List of broken channels: []
14:41:09:ST3_smx:INFO: chip: 33-3 28.225000 C 1218.600960 mV
14:41:09:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:41:09:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:41:09:ST3_smx:INFO: Electrons
14:41:09:ST3_smx:INFO: # loops 0
14:41:11:ST3_smx:INFO: # loops 1
14:41:12:ST3_smx:INFO: # loops 2
14:41:14:ST3_smx:INFO: Total # of broken channels: 0
14:41:14:ST3_smx:INFO: List of broken channels: []
14:41:14:ST3_smx:INFO: Total # of broken channels: 0
14:41:14:ST3_smx:INFO: List of broken channels: []
14:41:16:ST3_smx:INFO: chip: 38-4 40.898880 C 1165.571835 mV
14:41:16:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:41:16:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:41:16:ST3_smx:INFO: Electrons
14:41:16:ST3_smx:INFO: # loops 0
14:41:17:ST3_smx:INFO: # loops 1
14:41:19:ST3_smx:INFO: # loops 2
14:41:21:ST3_smx:INFO: Total # of broken channels: 0
14:41:21:ST3_smx:INFO: List of broken channels: []
14:41:21:ST3_smx:INFO: Total # of broken channels: 1
14:41:21:ST3_smx:INFO: List of broken channels: [4]
14:41:22:ST3_smx:INFO: chip: 34-5 28.225000 C 1206.851500 mV
14:41:22:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:41:22:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:41:22:ST3_smx:INFO: Electrons
14:41:22:ST3_smx:INFO: # loops 0
14:41:24:ST3_smx:INFO: # loops 1
14:41:26:ST3_smx:INFO: # loops 2
14:41:27:ST3_smx:INFO: Total # of broken channels: 0
14:41:27:ST3_smx:INFO: List of broken channels: []
14:41:27:ST3_smx:INFO: Total # of broken channels: 0
14:41:27:ST3_smx:INFO: List of broken channels: []
14:41:29:ST3_smx:INFO: chip: 39-6 50.430383 C 1153.732915 mV
14:41:29:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:41:29:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:41:29:ST3_smx:INFO: Electrons
14:41:29:ST3_smx:INFO: # loops 0
14:41:31:ST3_smx:INFO: # loops 1
14:41:33:ST3_smx:INFO: # loops 2
14:41:34:ST3_smx:INFO: Total # of broken channels: 0
14:41:34:ST3_smx:INFO: List of broken channels: []
14:41:34:ST3_smx:INFO: Total # of broken channels: 4
14:41:34:ST3_smx:INFO: List of broken channels: [5, 7, 15, 27]
14:41:36:ST3_smx:INFO: chip: 35-7 37.726682 C 1171.483840 mV
14:41:36:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:41:36:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:41:36:ST3_smx:INFO: Electrons
14:41:36:ST3_smx:INFO: # loops 0
14:41:38:ST3_smx:INFO: # loops 1
14:41:39:ST3_smx:INFO: # loops 2
14:41:41:ST3_smx:INFO: Total # of broken channels: 0
14:41:41:ST3_smx:INFO: List of broken channels: []
14:41:41:ST3_smx:INFO: Total # of broken channels: 0
14:41:41:ST3_smx:INFO: List of broken channels: []
14:41:41:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:41:41:febtest:INFO: 36-00 | XA-000-09-004-012-010-015-15 | 40.9 | 1195.1
14:41:42:febtest:INFO: 32-01 | XA-000-09-004-012-008-010-12 | 44.1 | 1177.4
14:41:42:febtest:INFO: 37-02 | XA-000-09-004-012-012-013-10 | 44.1 | 1177.4
14:41:42:febtest:INFO: 33-03 | XA-000-09-004-012-007-009-08 | 28.2 | 1253.7
14:41:42:febtest:INFO: 38-04 | XA-000-09-004-012-011-012-02 | 40.9 | 1189.2
14:41:42:febtest:INFO: 34-05 | XA-000-09-004-012-009-012-01 | 28.2 | 1224.5
14:41:43:febtest:INFO: 39-06 | XA-000-09-004-012-007-011-08 | 50.4 | 1171.5
14:41:43:febtest:INFO: 35-07 | XA-000-09-004-012-009-010-01 | 37.7 | 1189.2
############################################################
# S U M M A R Y #
############################################################
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
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# S U M M A R Y #
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TEST_NAME : FEB-Microcable
TEST_DATE : 24_10_31-14_40_18
OPERATOR : Alois Alzheimer
SITE : GSI | SETUP : GSI_TEST_SETUP_2
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| FEB_SN : 163| FEB_TYPE : 8.1| FEB_UPLINKS : 1| FEB_A
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VI_before_Init : ['2.447', '1.9730', '1.850', '2.5710', '0.000', '0.0000', '0.000', '0.0000']
VI_after__Init : ['2.450', '2.0140', '1.850', '2.3680', '0.000', '0.0000', '0.000', '0.0000']
VI_at__the_End : ['2.450', '1.9870', '1.850', '0.5271', '0.000', '0.0000', '0.000', '0.0000']