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FEB_2001 10.07.23 15:54:39
Info
15:53:51:ST3_hmp4040:INFO: ROHDE&SCHWARZ,HMP4040,106569,HW50020003/SW2.62
15:53:54:ST3_Shared:INFO: Listo of operators:Robert V.;
15:53:55:ST3_Shared:INFO: Listo of operators:Robert V.; Irakli K.;
15:53:57:febtest:INFO: FEB8.2 selected
15:53:57:smx_tester:INFO: Setting Elink clock mode to 160 MHz
15:54:39:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
15:54:39:ST3_Shared:INFO: --------------------------FEB-ASIC--------------------------
15:54:39:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
15:54:40:febtest:INFO: Tsting FEB with SN 2002
15:54:42:smx_tester:INFO: Scanning setup
15:54:42:elinks:INFO: Disabling clock on downlink 0
15:54:42:elinks:INFO: Disabling clock on downlink 1
15:54:42:elinks:INFO: Disabling clock on downlink 2
15:54:42:elinks:INFO: Disabling clock on downlink 3
15:54:42:elinks:INFO: Disabling clock on downlink 4
15:54:42:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:54:42:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
15:54:42:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:54:42:elinks:INFO: Disabling clock on downlink 0
15:54:42:elinks:INFO: Disabling clock on downlink 1
15:54:42:elinks:INFO: Disabling clock on downlink 2
15:54:42:elinks:INFO: Disabling clock on downlink 3
15:54:42:elinks:INFO: Disabling clock on downlink 4
15:54:42:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:54:42:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
15:54:42:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:54:43:elinks:INFO: Disabling clock on downlink 0
15:54:43:elinks:INFO: Disabling clock on downlink 1
15:54:43:elinks:INFO: Disabling clock on downlink 2
15:54:43:elinks:INFO: Disabling clock on downlink 3
15:54:43:elinks:INFO: Disabling clock on downlink 4
15:54:43:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:54:43:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:54:43:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 16
15:54:43:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 17
15:54:43:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 18
15:54:43:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 19
15:54:43:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 20
15:54:43:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 21
15:54:43:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 22
15:54:43:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 23
15:54:43:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24
15:54:43:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25
15:54:43:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26
15:54:43:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27
15:54:43:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28
15:54:43:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29
15:54:43:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30
15:54:43:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31
15:54:43:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:54:43:elinks:INFO: Disabling clock on downlink 0
15:54:43:elinks:INFO: Disabling clock on downlink 1
15:54:43:elinks:INFO: Disabling clock on downlink 2
15:54:43:elinks:INFO: Disabling clock on downlink 3
15:54:43:elinks:INFO: Disabling clock on downlink 4
15:54:43:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:54:43:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
15:54:43:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:54:43:elinks:INFO: Disabling clock on downlink 0
15:54:43:elinks:INFO: Disabling clock on downlink 1
15:54:43:elinks:INFO: Disabling clock on downlink 2
15:54:43:elinks:INFO: Disabling clock on downlink 3
15:54:43:elinks:INFO: Disabling clock on downlink 4
15:54:43:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:54:43:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
15:54:43:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:54:43:setup_element:INFO: Scanning clock phase
15:54:43:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:54:43:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
15:54:43:setup_element:INFO: Clock phase scan results for group 0, downlink 2
15:54:43:setup_element:INFO: Eye window for uplink 16: ________________________________________________________________________XXXXXXXX
Clock Delay: 35
15:54:43:setup_element:INFO: Eye window for uplink 17: ________________________________________________________________________XXXXXXXX
Clock Delay: 35
15:54:43:setup_element:INFO: Eye window for uplink 18: ________________________________________________________________________XXXXXXXX
Clock Delay: 35
15:54:43:setup_element:INFO: Eye window for uplink 19: ________________________________________________________________________XXXXXXXX
Clock Delay: 35
15:54:43:setup_element:INFO: Eye window for uplink 20: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
15:54:43:setup_element:INFO: Eye window for uplink 21: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
15:54:43:setup_element:INFO: Eye window for uplink 22: _______________________________________________________________________XXXXXXXXX
Clock Delay: 35
15:54:43:setup_element:INFO: Eye window for uplink 23: _______________________________________________________________________XXXXXXXXX
Clock Delay: 35
15:54:43:setup_element:INFO: Eye window for uplink 24: ________________________________________________________________________XXXXXXX_
Clock Delay: 35
15:54:43:setup_element:INFO: Eye window for uplink 25: ________________________________________________________________________XXXXXXX_
Clock Delay: 35
15:54:43:setup_element:INFO: Eye window for uplink 26: ________________________________________________________________________XXXXXXXX
Clock Delay: 35
15:54:43:setup_element:INFO: Eye window for uplink 27: ________________________________________________________________________XXXXXXXX
Clock Delay: 35
15:54:43:setup_element:INFO: Eye window for uplink 28: ________________________________________________________________________XXXXXXX_
Clock Delay: 35
15:54:43:setup_element:INFO: Eye window for uplink 29: ________________________________________________________________________XXXXXXX_
Clock Delay: 35
15:54:43:setup_element:INFO: Eye window for uplink 30: X________________________________________________________________________XXXXXXX
Clock Delay: 36
15:54:43:setup_element:INFO: Eye window for uplink 31: X________________________________________________________________________XXXXXXX
Clock Delay: 36
15:54:43:setup_element:INFO: Setting the clock phase to 35 for group 0, downlink 2
15:54:43:setup_element:INFO: Scanning data phases
15:54:43:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:54:44:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
15:54:49:setup_element:INFO: Data phase scan results for group 0, downlink 2
15:54:49:setup_element:INFO: Eye window for uplink 16: X___________________________________XXXX
Data delay found: 18
15:54:49:setup_element:INFO: Eye window for uplink 17: ________________________________XXXXX___
Data delay found: 14
15:54:49:setup_element:INFO: Eye window for uplink 18: X__________________________________XXXXX
Data delay found: 17
15:54:49:setup_element:INFO: Eye window for uplink 19: ________________________________XXXXX___
Data delay found: 14
15:54:49:setup_element:INFO: Eye window for uplink 20: __________________________________XXXX__
Data delay found: 15
15:54:49:setup_element:INFO: Eye window for uplink 21: ________________________________XXXXXX__
Data delay found: 14
15:54:49:setup_element:INFO: Eye window for uplink 22: ___________________________________XXXX_
Data delay found: 16
15:54:49:setup_element:INFO: Eye window for uplink 23: _________________________________XXXX___
Data delay found: 14
15:54:49:setup_element:INFO: Eye window for uplink 24: ___XXXXX________________________________
Data delay found: 25
15:54:49:setup_element:INFO: Eye window for uplink 25: ______XXXXX_____________________________
Data delay found: 28
15:54:49:setup_element:INFO: Eye window for uplink 26: _____XXXXX______________________________
Data delay found: 27
15:54:49:setup_element:INFO: Eye window for uplink 27: ________XXXXXX__________________________
Data delay found: 30
15:54:49:setup_element:INFO: Eye window for uplink 28: ___________XXXXX________________________
Data delay found: 33
15:54:49:setup_element:INFO: Eye window for uplink 29: ____________XXXXX_______________________
Data delay found: 34
15:54:49:setup_element:INFO: Eye window for uplink 30: _______________XXXXXX___________________
Data delay found: 37
15:54:49:setup_element:INFO: Eye window for uplink 31: _____________XXXXXX_____________________
Data delay found: 35
15:54:49:setup_element:INFO: Setting the data phase to 18 for uplink 16
15:54:49:setup_element:INFO: Setting the data phase to 14 for uplink 17
15:54:49:setup_element:INFO: Setting the data phase to 17 for uplink 18
15:54:49:setup_element:INFO: Setting the data phase to 14 for uplink 19
15:54:49:setup_element:INFO: Setting the data phase to 15 for uplink 20
15:54:49:setup_element:INFO: Setting the data phase to 14 for uplink 21
15:54:49:setup_element:INFO: Setting the data phase to 16 for uplink 22
15:54:49:setup_element:INFO: Setting the data phase to 14 for uplink 23
15:54:49:setup_element:INFO: Setting the data phase to 25 for uplink 24
15:54:49:setup_element:INFO: Setting the data phase to 28 for uplink 25
15:54:49:setup_element:INFO: Setting the data phase to 27 for uplink 26
15:54:49:setup_element:INFO: Setting the data phase to 30 for uplink 27
15:54:49:setup_element:INFO: Setting the data phase to 33 for uplink 28
15:54:49:setup_element:INFO: Setting the data phase to 34 for uplink 29
15:54:49:setup_element:INFO: Setting the data phase to 37 for uplink 30
15:54:49:setup_element:INFO: Setting the data phase to 35 for uplink 31
15:54:49:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 35
Window Length: 70
Eye Windows:
Uplink 16: ________________________________________________________________________XXXXXXXX
Uplink 17: ________________________________________________________________________XXXXXXXX
Uplink 18: ________________________________________________________________________XXXXXXXX
Uplink 19: ________________________________________________________________________XXXXXXXX
Uplink 20: _______________________________________________________________________XXXXXXXX_
Uplink 21: _______________________________________________________________________XXXXXXXX_
Uplink 22: _______________________________________________________________________XXXXXXXXX
Uplink 23: _______________________________________________________________________XXXXXXXXX
Uplink 24: ________________________________________________________________________XXXXXXX_
Uplink 25: ________________________________________________________________________XXXXXXX_
Uplink 26: ________________________________________________________________________XXXXXXXX
Uplink 27: ________________________________________________________________________XXXXXXXX
Uplink 28: ________________________________________________________________________XXXXXXX_
Uplink 29: ________________________________________________________________________XXXXXXX_
Uplink 30: X________________________________________________________________________XXXXXXX
Uplink 31: X________________________________________________________________________XXXXXXX
Data phase characteristics:
Uplink 16:
Optimal Phase: 18
Window Length: 35
Eye Window: X___________________________________XXXX
Uplink 17:
Optimal Phase: 14
Window Length: 35
Eye Window: ________________________________XXXXX___
Uplink 18:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXXX
Uplink 19:
Optimal Phase: 14
Window Length: 35
Eye Window: ________________________________XXXXX___
Uplink 20:
Optimal Phase: 15
Window Length: 36
Eye Window: __________________________________XXXX__
Uplink 21:
Optimal Phase: 14
Window Length: 34
Eye Window: ________________________________XXXXXX__
Uplink 22:
Optimal Phase: 16
Window Length: 36
Eye Window: ___________________________________XXXX_
Uplink 23:
Optimal Phase: 14
Window Length: 36
Eye Window: _________________________________XXXX___
Uplink 24:
Optimal Phase: 25
Window Length: 35
Eye Window: ___XXXXX________________________________
Uplink 25:
Optimal Phase: 28
Window Length: 35
Eye Window: ______XXXXX_____________________________
Uplink 26:
Optimal Phase: 27
Window Length: 35
Eye Window: _____XXXXX______________________________
Uplink 27:
Optimal Phase: 30
Window Length: 34
Eye Window: ________XXXXXX__________________________
Uplink 28:
Optimal Phase: 33
Window Length: 35
Eye Window: ___________XXXXX________________________
Uplink 29:
Optimal Phase: 34
Window Length: 35
Eye Window: ____________XXXXX_______________________
Uplink 30:
Optimal Phase: 37
Window Length: 34
Eye Window: _______________XXXXXX___________________
Uplink 31:
Optimal Phase: 35
Window Length: 34
Eye Window: _____________XXXXXX_____________________
]
15:54:49:setup_element:INFO: Beginning SMX ASICs map scan
15:54:49:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:54:49:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
15:54:49:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
15:54:49:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
15:54:49:uplink:INFO: Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
15:54:49:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 23
15:54:49:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 22
15:54:49:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 30
15:54:49:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 31
15:54:50:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 21
15:54:50:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 20
15:54:50:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28
15:54:50:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 29
15:54:50:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 19
15:54:50:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 18
15:54:50:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26
15:54:50:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 27
15:54:50:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 17
15:54:50:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 16
15:54:50:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 24
15:54:50:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 25
15:54:52:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 23), (1, 22)
ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
ASIC address 0x2: (ASIC uplink, uplink): (0, 21), (1, 20)
ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
ASIC address 0x4: (ASIC uplink, uplink): (0, 19), (1, 18)
ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
ASIC address 0x6: (ASIC uplink, uplink): (0, 17), (1, 16)
ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
Clock Phase Characteristic:
Optimal Phase: 35
Window Length: 70
Eye Windows:
Uplink 16: ________________________________________________________________________XXXXXXXX
Uplink 17: ________________________________________________________________________XXXXXXXX
Uplink 18: ________________________________________________________________________XXXXXXXX
Uplink 19: ________________________________________________________________________XXXXXXXX
Uplink 20: _______________________________________________________________________XXXXXXXX_
Uplink 21: _______________________________________________________________________XXXXXXXX_
Uplink 22: _______________________________________________________________________XXXXXXXXX
Uplink 23: _______________________________________________________________________XXXXXXXXX
Uplink 24: ________________________________________________________________________XXXXXXX_
Uplink 25: ________________________________________________________________________XXXXXXX_
Uplink 26: ________________________________________________________________________XXXXXXXX
Uplink 27: ________________________________________________________________________XXXXXXXX
Uplink 28: ________________________________________________________________________XXXXXXX_
Uplink 29: ________________________________________________________________________XXXXXXX_
Uplink 30: X________________________________________________________________________XXXXXXX
Uplink 31: X________________________________________________________________________XXXXXXX
Data phase characteristics:
Uplink 16:
Optimal Phase: 18
Window Length: 35
Eye Window: X___________________________________XXXX
Uplink 17:
Optimal Phase: 14
Window Length: 35
Eye Window: ________________________________XXXXX___
Uplink 18:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXXX
Uplink 19:
Optimal Phase: 14
Window Length: 35
Eye Window: ________________________________XXXXX___
Uplink 20:
Optimal Phase: 15
Window Length: 36
Eye Window: __________________________________XXXX__
Uplink 21:
Optimal Phase: 14
Window Length: 34
Eye Window: ________________________________XXXXXX__
Uplink 22:
Optimal Phase: 16
Window Length: 36
Eye Window: ___________________________________XXXX_
Uplink 23:
Optimal Phase: 14
Window Length: 36
Eye Window: _________________________________XXXX___
Uplink 24:
Optimal Phase: 25
Window Length: 35
Eye Window: ___XXXXX________________________________
Uplink 25:
Optimal Phase: 28
Window Length: 35
Eye Window: ______XXXXX_____________________________
Uplink 26:
Optimal Phase: 27
Window Length: 35
Eye Window: _____XXXXX______________________________
Uplink 27:
Optimal Phase: 30
Window Length: 34
Eye Window: ________XXXXXX__________________________
Uplink 28:
Optimal Phase: 33
Window Length: 35
Eye Window: ___________XXXXX________________________
Uplink 29:
Optimal Phase: 34
Window Length: 35
Eye Window: ____________XXXXX_______________________
Uplink 30:
Optimal Phase: 37
Window Length: 34
Eye Window: _______________XXXXXX___________________
Uplink 31:
Optimal Phase: 35
Window Length: 34
Eye Window: _____________XXXXXX_____________________
15:54:52:setup_element:INFO: Performing Elink synchronization
15:54:52:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:54:52:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
15:54:52:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
15:54:52:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
15:54:52:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2
15:54:52:uplink:INFO: Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
15:54:52:ST3_emu:INFO: Number of chips: 8
15:54:52:ST3_emu:INFO: Chip address: 0x0
15:54:52:ST3_emu:INFO: Chip address: 0x1
15:54:52:ST3_emu:INFO: Chip address: 0x2
15:54:52:ST3_emu:INFO: Chip address: 0x3
15:54:52:ST3_emu:INFO: Chip address: 0x4
15:54:52:ST3_emu:INFO: Chip address: 0x5
15:54:52:ST3_emu:INFO: Chip address: 0x6
15:54:52:ST3_emu:INFO: Chip address: 0x7
15:54:54:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:54:54:febtest:INFO: 0-0 | XA-000-08-002-000-008-097-09 | 15.6 | 1236.2
15:54:54:febtest:INFO: 0-1 | XA-000-08-002-000-008-127-14 | 25.1 | 1218.6
15:54:55:febtest:INFO: 0-2 | XA-000-08-002-000-008-119-14 | 28.2 | 1195.1
15:54:55:febtest:INFO: 0-3 | XA-000-08-002-000-008-124-14 | 31.4 | 1195.1
15:54:55:febtest:INFO: 0-4 | XA-000-08-002-000-008-117-14 | 25.1 | 1218.6
15:54:55:febtest:INFO: 0-5 | XA-000-08-002-000-008-123-14 | 28.2 | 1212.7
15:54:55:febtest:INFO: 0-6 | XA-000-08-002-000-008-115-14 | 28.2 | 1201.0
15:54:56:febtest:INFO: 0-7 | XA-000-08-002-000-008-122-14 | 31.4 | 1189.2
15:54:56:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:55:00:ST3_smx:INFO: chip: 0-0 12.438562 C 1236.187875 mV
15:55:00:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:55:00:ST3_smx:INFO: Electrons
15:55:00:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:55:02:ST3_smx:INFO: ----> Checking Analog response
15:55:02:ST3_smx:INFO: ----> Checking broken channels
15:55:02:ST3_smx:INFO: Total # broken ch: 0
15:55:02:ST3_smx:INFO: List FAST: []
15:55:02:ST3_smx:INFO: List SLOW: []
15:55:02:ST3_smx:INFO: Holes
15:55:02:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:55:04:ST3_smx:INFO: ----> Checking Analog response
15:55:04:ST3_smx:INFO: ----> Checking broken channels
15:55:04:ST3_smx:INFO: Total # broken ch: 0
15:55:04:ST3_smx:INFO: List FAST: []
15:55:04:ST3_smx:INFO: List SLOW: []
15:55:04:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:55:05:febtest:INFO: 0-0 | XA-000-08-002-000-008-097-09 | 15.6 | 1230.3
15:55:05:febtest:INFO: 0-1 | XA-000-08-002-000-008-127-14 | 21.9 | 1212.7
15:55:05:febtest:INFO: 0-2 | XA-000-08-002-000-008-119-14 | 28.2 | 1195.1
15:55:05:febtest:INFO: 0-3 | XA-000-08-002-000-008-124-14 | 31.4 | 1201.0
15:55:06:febtest:INFO: 0-4 | XA-000-08-002-000-008-117-14 | 21.9 | 1218.6
15:55:06:febtest:INFO: 0-5 | XA-000-08-002-000-008-123-14 | 28.2 | 1212.7
15:55:06:febtest:INFO: 0-6 | XA-000-08-002-000-008-115-14 | 28.2 | 1201.0
15:55:06:febtest:INFO: 0-7 | XA-000-08-002-000-008-122-14 | 34.6 | 1189.2
15:55:07:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:55:11:ST3_smx:INFO: chip: 0-1 28.225000 C 1189.190035 mV
15:55:11:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:55:11:ST3_smx:INFO: Electrons
15:55:11:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:55:13:ST3_smx:INFO: ----> Checking Analog response
15:55:13:ST3_smx:INFO: ----> Checking broken channels
15:55:13:ST3_smx:INFO: Total # broken ch: 0
15:55:13:ST3_smx:INFO: List FAST: []
15:55:13:ST3_smx:INFO: List SLOW: []
15:55:13:ST3_smx:INFO: Holes
15:55:13:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:55:15:ST3_smx:INFO: ----> Checking Analog response
15:55:15:ST3_smx:INFO: ----> Checking broken channels
15:55:16:ST3_smx:INFO: Total # broken ch: 0
15:55:16:ST3_smx:INFO: List FAST: []
15:55:16:ST3_smx:INFO: List SLOW: []
15:55:16:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:55:16:febtest:INFO: 0-0 | XA-000-08-002-000-008-097-09 | 12.4 | 1230.3
15:55:16:febtest:INFO: 0-1 | XA-000-08-002-000-008-127-14 | 31.4 | 1183.3
15:55:16:febtest:INFO: 0-2 | XA-000-08-002-000-008-119-14 | 28.2 | 1195.1
15:55:17:febtest:INFO: 0-3 | XA-000-08-002-000-008-124-14 | 28.2 | 1201.0
15:55:17:febtest:INFO: 0-4 | XA-000-08-002-000-008-117-14 | 21.9 | 1218.6
15:55:17:febtest:INFO: 0-5 | XA-000-08-002-000-008-123-14 | 25.1 | 1218.6
15:55:17:febtest:INFO: 0-6 | XA-000-08-002-000-008-115-14 | 28.2 | 1201.0
15:55:17:febtest:INFO: 0-7 | XA-000-08-002-000-008-122-14 | 31.4 | 1189.2
15:55:19:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:55:22:ST3_smx:INFO: chip: 0-2 28.225000 C 1195.082160 mV
15:55:22:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:55:22:ST3_smx:INFO: Electrons
15:55:22:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:55:24:ST3_smx:INFO: ----> Checking Analog response
15:55:24:ST3_smx:INFO: ----> Checking broken channels
15:55:25:ST3_smx:INFO: Total # broken ch: 0
15:55:25:ST3_smx:INFO: List FAST: []
15:55:25:ST3_smx:INFO: List SLOW: []
15:55:25:ST3_smx:INFO: Holes
15:55:25:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:55:27:ST3_smx:INFO: ----> Checking Analog response
15:55:27:ST3_smx:INFO: ----> Checking broken channels
15:55:27:ST3_smx:INFO: Total # broken ch: 0
15:55:27:ST3_smx:INFO: List FAST: []
15:55:27:ST3_smx:INFO: List SLOW: []
15:55:27:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:55:27:febtest:INFO: 0-0 | XA-000-08-002-000-008-097-09 | 12.4 | 1236.2
15:55:27:febtest:INFO: 0-1 | XA-000-08-002-000-008-127-14 | 31.4 | 1183.3
15:55:28:febtest:INFO: 0-2 | XA-000-08-002-000-008-119-14 | 28.2 | 1189.2
15:55:28:febtest:INFO: 0-3 | XA-000-08-002-000-008-124-14 | 28.2 | 1201.0
15:55:28:febtest:INFO: 0-4 | XA-000-08-002-000-008-117-14 | 21.9 | 1218.6
15:55:28:febtest:INFO: 0-5 | XA-000-08-002-000-008-123-14 | 25.1 | 1212.7
15:55:29:febtest:INFO: 0-6 | XA-000-08-002-000-008-115-14 | 28.2 | 1201.0
15:55:29:febtest:INFO: 0-7 | XA-000-08-002-000-008-122-14 | 31.4 | 1189.2
15:55:30:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:55:34:ST3_smx:INFO: chip: 0-3 31.389742 C 1177.390875 mV
15:55:34:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:55:34:ST3_smx:INFO: Electrons
15:55:34:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:55:36:ST3_smx:INFO: ----> Checking Analog response
15:55:36:ST3_smx:INFO: ----> Checking broken channels
15:55:36:ST3_smx:INFO: Total # broken ch: 0
15:55:36:ST3_smx:INFO: List FAST: []
15:55:36:ST3_smx:INFO: List SLOW: []
15:55:36:ST3_smx:INFO: Holes
15:55:36:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:55:38:ST3_smx:INFO: ----> Checking Analog response
15:55:38:ST3_smx:INFO: ----> Checking broken channels
15:55:38:ST3_smx:INFO: Total # broken ch: 0
15:55:38:ST3_smx:INFO: List FAST: []
15:55:38:ST3_smx:INFO: List SLOW: []
15:55:38:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:55:38:febtest:INFO: 0-0 | XA-000-08-002-000-008-097-09 | 12.4 | 1236.2
15:55:39:febtest:INFO: 0-1 | XA-000-08-002-000-008-127-14 | 28.2 | 1183.3
15:55:39:febtest:INFO: 0-2 | XA-000-08-002-000-008-119-14 | 28.2 | 1189.2
15:55:39:febtest:INFO: 0-3 | XA-000-08-002-000-008-124-14 | 34.6 | 1177.4
15:55:39:febtest:INFO: 0-4 | XA-000-08-002-000-008-117-14 | 21.9 | 1218.6
15:55:39:febtest:INFO: 0-5 | XA-000-08-002-000-008-123-14 | 25.1 | 1212.7
15:55:40:febtest:INFO: 0-6 | XA-000-08-002-000-008-115-14 | 25.1 | 1206.9
15:55:40:febtest:INFO: 0-7 | XA-000-08-002-000-008-122-14 | 31.4 | 1189.2
15:55:41:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:55:45:ST3_smx:INFO: chip: 0-4 25.062742 C 1200.969315 mV
15:55:45:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:55:45:ST3_smx:INFO: Electrons
15:55:45:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:55:47:ST3_smx:INFO: ----> Checking Analog response
15:55:47:ST3_smx:INFO: ----> Checking broken channels
15:55:47:ST3_smx:INFO: Total # broken ch: 0
15:55:47:ST3_smx:INFO: List FAST: []
15:55:47:ST3_smx:INFO: List SLOW: []
15:55:47:ST3_smx:INFO: Holes
15:55:47:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:55:49:ST3_smx:INFO: ----> Checking Analog response
15:55:49:ST3_smx:INFO: ----> Checking broken channels
15:55:49:ST3_smx:INFO: Total # broken ch: 0
15:55:49:ST3_smx:INFO: List FAST: []
15:55:49:ST3_smx:INFO: List SLOW: []
15:55:49:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:55:49:febtest:INFO: 0-0 | XA-000-08-002-000-008-097-09 | 12.4 | 1230.3
15:55:50:febtest:INFO: 0-1 | XA-000-08-002-000-008-127-14 | 28.2 | 1183.3
15:55:50:febtest:INFO: 0-2 | XA-000-08-002-000-008-119-14 | 28.2 | 1189.2
15:55:50:febtest:INFO: 0-3 | XA-000-08-002-000-008-124-14 | 31.4 | 1177.4
15:55:50:febtest:INFO: 0-4 | XA-000-08-002-000-008-117-14 | 25.1 | 1195.1
15:55:51:febtest:INFO: 0-5 | XA-000-08-002-000-008-123-14 | 25.1 | 1212.7
15:55:51:febtest:INFO: 0-6 | XA-000-08-002-000-008-115-14 | 25.1 | 1206.9
15:55:51:febtest:INFO: 0-7 | XA-000-08-002-000-008-122-14 | 31.4 | 1189.2
15:55:52:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:55:56:ST3_smx:INFO: chip: 0-5 31.389742 C 1177.390875 mV
15:55:56:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:55:56:ST3_smx:INFO: Electrons
15:55:56:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:55:58:ST3_smx:INFO: ----> Checking Analog response
15:55:58:ST3_smx:INFO: ----> Checking broken channels
15:55:58:ST3_smx:INFO: Total # broken ch: 0
15:55:58:ST3_smx:INFO: List FAST: []
15:55:58:ST3_smx:INFO: List SLOW: []
15:55:58:ST3_smx:INFO: Holes
15:55:58:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:56:00:ST3_smx:INFO: ----> Checking Analog response
15:56:00:ST3_smx:INFO: ----> Checking broken channels
15:56:00:ST3_smx:INFO: Total # broken ch: 0
15:56:00:ST3_smx:INFO: List FAST: []
15:56:00:ST3_smx:INFO: List SLOW: []
15:56:00:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:56:00:febtest:INFO: 0-0 | XA-000-08-002-000-008-097-09 | 12.4 | 1236.2
15:56:01:febtest:INFO: 0-1 | XA-000-08-002-000-008-127-14 | 28.2 | 1183.3
15:56:01:febtest:INFO: 0-2 | XA-000-08-002-000-008-119-14 | 28.2 | 1195.1
15:56:01:febtest:INFO: 0-3 | XA-000-08-002-000-008-124-14 | 31.4 | 1177.4
15:56:01:febtest:INFO: 0-4 | XA-000-08-002-000-008-117-14 | 25.1 | 1195.1
15:56:02:febtest:INFO: 0-5 | XA-000-08-002-000-008-123-14 | 34.6 | 1177.4
15:56:02:febtest:INFO: 0-6 | XA-000-08-002-000-008-115-14 | 25.1 | 1206.9
15:56:02:febtest:INFO: 0-7 | XA-000-08-002-000-008-122-14 | 31.4 | 1189.2
15:56:03:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:56:07:ST3_smx:INFO: chip: 0-6 28.225000 C 1183.292940 mV
15:56:07:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:56:07:ST3_smx:INFO: Electrons
15:56:07:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:56:09:ST3_smx:INFO: ----> Checking Analog response
15:56:09:ST3_smx:INFO: ----> Checking broken channels
15:56:09:ST3_smx:INFO: Total # broken ch: 0
15:56:09:ST3_smx:INFO: List FAST: []
15:56:09:ST3_smx:INFO: List SLOW: []
15:56:09:ST3_smx:INFO: Holes
15:56:09:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:56:11:ST3_smx:INFO: ----> Checking Analog response
15:56:11:ST3_smx:INFO: ----> Checking broken channels
15:56:11:ST3_smx:INFO: Total # broken ch: 0
15:56:11:ST3_smx:INFO: List FAST: []
15:56:11:ST3_smx:INFO: List SLOW: []
15:56:11:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:56:12:febtest:INFO: 0-0 | XA-000-08-002-000-008-097-09 | 12.4 | 1236.2
15:56:12:febtest:INFO: 0-1 | XA-000-08-002-000-008-127-14 | 28.2 | 1183.3
15:56:12:febtest:INFO: 0-2 | XA-000-08-002-000-008-119-14 | 28.2 | 1195.1
15:56:12:febtest:INFO: 0-3 | XA-000-08-002-000-008-124-14 | 31.4 | 1183.3
15:56:13:febtest:INFO: 0-4 | XA-000-08-002-000-008-117-14 | 25.1 | 1195.1
15:56:13:febtest:INFO: 0-5 | XA-000-08-002-000-008-123-14 | 31.4 | 1177.4
15:56:13:febtest:INFO: 0-6 | XA-000-08-002-000-008-115-14 | 28.2 | 1183.3
15:56:13:febtest:INFO: 0-7 | XA-000-08-002-000-008-122-14 | 31.4 | 1189.2
15:56:14:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:56:18:ST3_smx:INFO: chip: 0-7 34.556970 C 1165.571835 mV
15:56:18:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:56:18:ST3_smx:INFO: Electrons
15:56:18:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:56:20:ST3_smx:INFO: ----> Checking Analog response
15:56:20:ST3_smx:INFO: ----> Checking broken channels
15:56:20:ST3_smx:INFO: Total # broken ch: 0
15:56:20:ST3_smx:INFO: List FAST: []
15:56:20:ST3_smx:INFO: List SLOW: []
15:56:20:ST3_smx:INFO: Holes
15:56:20:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:56:22:ST3_smx:INFO: ----> Checking Analog response
15:56:22:ST3_smx:INFO: ----> Checking broken channels
15:56:23:ST3_smx:INFO: Total # broken ch: 0
15:56:23:ST3_smx:INFO: List FAST: []
15:56:23:ST3_smx:INFO: List SLOW: []
15:56:23:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:56:23:febtest:INFO: 0-0 | XA-000-08-002-000-008-097-09 | 12.4 | 1236.2
15:56:23:febtest:INFO: 0-1 | XA-000-08-002-000-008-127-14 | 28.2 | 1183.3
15:56:23:febtest:INFO: 0-2 | XA-000-08-002-000-008-119-14 | 25.1 | 1195.1
15:56:23:febtest:INFO: 0-3 | XA-000-08-002-000-008-124-14 | 31.4 | 1183.3
15:56:24:febtest:INFO: 0-4 | XA-000-08-002-000-008-117-14 | 25.1 | 1201.0
15:56:24:febtest:INFO: 0-5 | XA-000-08-002-000-008-123-14 | 31.4 | 1177.4
15:56:24:febtest:INFO: 0-6 | XA-000-08-002-000-008-115-14 | 28.2 | 1183.3
15:56:24:febtest:INFO: 0-7 | XA-000-08-002-000-008-122-14 | 37.7 | 1165.6
############################################################
# S U M M A R Y #
############################################################
{'TEST_NAME': 'FEB-ASIC', 'TEST_DATE': '2023_07_10-15_54_39', 'OPERATOR': 'Robert V.; Irakli K.; ', 'PROJECT': 'Production', 'SITE': 'GSI', 'SETUP': 'GSI_TEST_SETUP_1', 'ASIC_ID': 'XA-000-08-002-000-008-122-14', 'FUSED_ID': 6359364699116570542, 'HW_ADDR': 7, 'VERS_NO': '2.2', 'CABLE_SET_ID': '', 'IC_TEMP': '0', 'VDDM': '0', 'AUX': '0', 'CSABIAS': '0', 'VDDM_INT': '0', 'ADC_Chi2': 0.0, 'ADC_NDF': 0, 'ADC_P0': 0.0, 'ADC_P1': 0.006824, 'ADC_P2': -2.485e-06, 'ADC_P0err': 0.001, 'ADC_P1err': 0.001, 'ADC_P2err': 1e-05, 'ADC_VREF_P': 58, 'ADC_VREF_N': 30, 'ADC_VREF_T': 128, 'ADC_VREF_TR': 122, 'THR2_GLB': 30, 'LOOP__PLS': 100, 'CALIB_PLS': 250, 'SnsLoop': 5, 'IFED': 31, 'CSA_BIAS': 15, 'CSA_Chi2': 0.0, 'CSA_NDF': 0, 'CSA_P0': 0.0, 'CSA_P1': 0.0, 'CSA_P2': 0.0, 'CSA_P0err': 0.0, 'CSA_P1err': 0.0, 'CSA_P2err': 0.0, 'CONF_FAIL_REG': 0, 'N_BROKEN_DISC': 0, 'N_BROKEN_FAST': '[]', 'N_BROKEN_SLOW': '[]', 'P_BROKEN_DISC': 0, 'P_BROKEN_FAST': '[]', 'P_BROKEN_SLOW': '[]', 'ASIC_QA_category': '', 'N_BROKEN_CABLE': 0, 'LIST_OF_BROKEN_CABLES': 0, 'VI_bInit': ['0.000', '0.0000', '2.500', '1.4240', '2.199', '2.3600', '7.001', '1.5430'], 'VI_aInit': ['0', '0', '0', '0', '0', '0'], 'VI_atEnd': ['0', '0', '0', '0', '0', '0'], 'AMP_CAL': 200, 'PlsLoop': 3, 'N_ANA_PRESENT': 'Analog response OK', 'N_DISC_FAIL_CH': 0, 'N_ANA_FAIL_CH': '0', 'P_ANA_PRESENT': 'Analog response OK', 'P_DISC_FAIL_CH': 0, 'P_ANA_FAIL_CH': '0'}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
15:56:51:ST3_Shared:INFO: /home/cbm/public_html/Test_LogDir//FEB/FEB_2001/B//TestDate_2023_07_10-15_54_39/