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FEB_2002 23.05.24 17:49:40
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17:49:40:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
17:49:40:ST3_Shared:INFO: FEB-ASIC
17:49:40:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
17:49:40:febtest:INFO: Testing FEB with SN 2002
17:49:42:smx_tester:INFO: Scanning setup
17:49:42:elinks:INFO: Disabling clock on downlink 0
17:49:42:elinks:INFO: Disabling clock on downlink 1
17:49:42:elinks:INFO: Disabling clock on downlink 2
17:49:42:elinks:INFO: Disabling clock on downlink 3
17:49:42:elinks:INFO: Disabling clock on downlink 4
17:49:42:setup_element:INFO: Checking SOS, encoding_mode: SOS
17:49:42:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
17:49:42:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
17:49:42:elinks:INFO: Disabling clock on downlink 0
17:49:42:elinks:INFO: Disabling clock on downlink 1
17:49:42:elinks:INFO: Disabling clock on downlink 2
17:49:42:elinks:INFO: Disabling clock on downlink 3
17:49:42:elinks:INFO: Disabling clock on downlink 4
17:49:42:setup_element:INFO: Checking SOS, encoding_mode: SOS
17:49:42:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
17:49:42:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
17:49:42:elinks:INFO: Disabling clock on downlink 0
17:49:42:elinks:INFO: Disabling clock on downlink 1
17:49:42:elinks:INFO: Disabling clock on downlink 2
17:49:42:elinks:INFO: Disabling clock on downlink 3
17:49:42:elinks:INFO: Disabling clock on downlink 4
17:49:42:setup_element:INFO: Checking SOS, encoding_mode: SOS
17:49:42:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
17:49:42:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 16
17:49:42:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 17
17:49:42:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 18
17:49:42:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 19
17:49:42:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 20
17:49:42:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 21
17:49:42:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 22
17:49:42:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 23
17:49:42:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24
17:49:42:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25
17:49:42:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26
17:49:42:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27
17:49:42:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28
17:49:42:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29
17:49:42:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30
17:49:42:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31
17:49:42:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
17:49:42:elinks:INFO: Disabling clock on downlink 0
17:49:42:elinks:INFO: Disabling clock on downlink 1
17:49:42:elinks:INFO: Disabling clock on downlink 2
17:49:42:elinks:INFO: Disabling clock on downlink 3
17:49:42:elinks:INFO: Disabling clock on downlink 4
17:49:42:setup_element:INFO: Checking SOS, encoding_mode: SOS
17:49:42:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
17:49:42:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
17:49:42:elinks:INFO: Disabling clock on downlink 0
17:49:42:elinks:INFO: Disabling clock on downlink 1
17:49:42:elinks:INFO: Disabling clock on downlink 2
17:49:42:elinks:INFO: Disabling clock on downlink 3
17:49:42:elinks:INFO: Disabling clock on downlink 4
17:49:42:setup_element:INFO: Checking SOS, encoding_mode: SOS
17:49:42:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
17:49:42:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
17:49:42:setup_element:INFO: Scanning clock phase
17:49:42:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
17:49:42:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
17:49:43:setup_element:INFO: Clock phase scan results for group 0, downlink 2
17:49:43:setup_element:INFO: Eye window for uplink 16: __________________________________________________________________________XXXXXX
Clock Delay: 36
17:49:43:setup_element:INFO: Eye window for uplink 17: __________________________________________________________________________XXXXXX
Clock Delay: 36
17:49:43:setup_element:INFO: Eye window for uplink 18: _________________________________________________________________________XXXXXXX
Clock Delay: 36
17:49:43:setup_element:INFO: Eye window for uplink 19: _________________________________________________________________________XXXXXXX
Clock Delay: 36
17:49:43:setup_element:INFO: Eye window for uplink 20: ________________________________________________________________________XXXXXXXX
Clock Delay: 35
17:49:43:setup_element:INFO: Eye window for uplink 21: ________________________________________________________________________XXXXXXXX
Clock Delay: 35
17:49:43:setup_element:INFO: Eye window for uplink 22: _________________________________________________________________________XXXXXXX
Clock Delay: 36
17:49:43:setup_element:INFO: Eye window for uplink 23: _________________________________________________________________________XXXXXXX
Clock Delay: 36
17:49:43:setup_element:INFO: Eye window for uplink 24: __________________________________________________________________________XXXXX_
Clock Delay: 36
17:49:43:setup_element:INFO: Eye window for uplink 25: __________________________________________________________________________XXXXX_
Clock Delay: 36
17:49:43:setup_element:INFO: Eye window for uplink 26: _________________________________________________________________________XXXXXX_
Clock Delay: 35
17:49:43:setup_element:INFO: Eye window for uplink 27: _________________________________________________________________________XXXXXX_
Clock Delay: 35
17:49:43:setup_element:INFO: Eye window for uplink 28: __________________________________________________________________________XXXXXX
Clock Delay: 36
17:49:43:setup_element:INFO: Eye window for uplink 29: __________________________________________________________________________XXXXXX
Clock Delay: 36
17:49:43:setup_element:INFO: Eye window for uplink 30: XX_________________________________________________________________________XXXXX
Clock Delay: 38
17:49:43:setup_element:INFO: Eye window for uplink 31: XX_________________________________________________________________________XXXXX
Clock Delay: 38
17:49:43:setup_element:INFO: Setting the clock phase to 36 for group 0, downlink 2
17:49:43:setup_element:INFO: Scanning data phases
17:49:43:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
17:49:43:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
17:49:48:setup_element:INFO: Data phase scan results for group 0, downlink 2
17:49:48:setup_element:INFO: Eye window for uplink 16: __________________________________XXXXX_
Data delay found: 16
17:49:48:setup_element:INFO: Eye window for uplink 17: _______________________________XXXXX____
Data delay found: 13
17:49:48:setup_element:INFO: Eye window for uplink 18: _________________________________XXXXX__
Data delay found: 15
17:49:48:setup_element:INFO: Eye window for uplink 19: _______________________________XXXXXX___
Data delay found: 13
17:49:48:setup_element:INFO: Eye window for uplink 20: _______________________________XXXXXX___
Data delay found: 13
17:49:48:setup_element:INFO: Eye window for uplink 21: _______________________________XXXXX____
Data delay found: 13
17:49:48:setup_element:INFO: Eye window for uplink 22: _________________________________XXXXXX_
Data delay found: 15
17:49:48:setup_element:INFO: Eye window for uplink 23: ________________________________XXXXX___
Data delay found: 14
17:49:48:setup_element:INFO: Eye window for uplink 24: ___XXXX________________XXXXXXXXXXXXXXXXX
Data delay found: 14
17:49:48:setup_element:INFO: Eye window for uplink 25: ____XXXXX_X____________XXXXXXXXXXXXXXXXX
Data delay found: 16
17:49:48:setup_element:INFO: Eye window for uplink 26: ___XXXX_________________________________
Data delay found: 24
17:49:48:setup_element:INFO: Eye window for uplink 27: ______XXXX______________________________
Data delay found: 27
17:49:48:setup_element:INFO: Eye window for uplink 28: ________XXXXX___________________________
Data delay found: 30
17:49:48:setup_element:INFO: Eye window for uplink 29: ________XXXXXX__________________________
Data delay found: 30
17:49:48:setup_element:INFO: Eye window for uplink 30: ______________XXXXXX____________________
Data delay found: 36
17:49:48:setup_element:INFO: Eye window for uplink 31: ___________XXXXXX_______________________
Data delay found: 33
17:49:48:setup_element:INFO: Setting the data phase to 16 for uplink 16
17:49:48:setup_element:INFO: Setting the data phase to 13 for uplink 17
17:49:48:setup_element:INFO: Setting the data phase to 15 for uplink 18
17:49:48:setup_element:INFO: Setting the data phase to 13 for uplink 19
17:49:48:setup_element:INFO: Setting the data phase to 13 for uplink 20
17:49:48:setup_element:INFO: Setting the data phase to 13 for uplink 21
17:49:48:setup_element:INFO: Setting the data phase to 15 for uplink 22
17:49:48:setup_element:INFO: Setting the data phase to 14 for uplink 23
17:49:48:setup_element:INFO: Setting the data phase to 14 for uplink 24
17:49:48:setup_element:INFO: Setting the data phase to 16 for uplink 25
17:49:48:setup_element:INFO: Setting the data phase to 24 for uplink 26
17:49:48:setup_element:INFO: Setting the data phase to 27 for uplink 27
17:49:48:setup_element:INFO: Setting the data phase to 30 for uplink 28
17:49:48:setup_element:INFO: Setting the data phase to 30 for uplink 29
17:49:48:setup_element:INFO: Setting the data phase to 36 for uplink 30
17:49:48:setup_element:INFO: Setting the data phase to 33 for uplink 31
17:49:48:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 36
Window Length: 70
Eye Windows:
Uplink 16: __________________________________________________________________________XXXXXX
Uplink 17: __________________________________________________________________________XXXXXX
Uplink 18: _________________________________________________________________________XXXXXXX
Uplink 19: _________________________________________________________________________XXXXXXX
Uplink 20: ________________________________________________________________________XXXXXXXX
Uplink 21: ________________________________________________________________________XXXXXXXX
Uplink 22: _________________________________________________________________________XXXXXXX
Uplink 23: _________________________________________________________________________XXXXXXX
Uplink 24: __________________________________________________________________________XXXXX_
Uplink 25: __________________________________________________________________________XXXXX_
Uplink 26: _________________________________________________________________________XXXXXX_
Uplink 27: _________________________________________________________________________XXXXXX_
Uplink 28: __________________________________________________________________________XXXXXX
Uplink 29: __________________________________________________________________________XXXXXX
Uplink 30: XX_________________________________________________________________________XXXXX
Uplink 31: XX_________________________________________________________________________XXXXX
Data phase characteristics:
Uplink 16:
Optimal Phase: 16
Window Length: 35
Eye Window: __________________________________XXXXX_
Uplink 17:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 18:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
Uplink 19:
Optimal Phase: 13
Window Length: 34
Eye Window: _______________________________XXXXXX___
Uplink 20:
Optimal Phase: 13
Window Length: 34
Eye Window: _______________________________XXXXXX___
Uplink 21:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 22:
Optimal Phase: 15
Window Length: 34
Eye Window: _________________________________XXXXXX_
Uplink 23:
Optimal Phase: 14
Window Length: 35
Eye Window: ________________________________XXXXX___
Uplink 24:
Optimal Phase: 14
Window Length: 16
Eye Window: ___XXXX________________XXXXXXXXXXXXXXXXX
Uplink 25:
Optimal Phase: 16
Window Length: 12
Eye Window: ____XXXXX_X____________XXXXXXXXXXXXXXXXX
Uplink 26:
Optimal Phase: 24
Window Length: 36
Eye Window: ___XXXX_________________________________
Uplink 27:
Optimal Phase: 27
Window Length: 36
Eye Window: ______XXXX______________________________
Uplink 28:
Optimal Phase: 30
Window Length: 35
Eye Window: ________XXXXX___________________________
Uplink 29:
Optimal Phase: 30
Window Length: 34
Eye Window: ________XXXXXX__________________________
Uplink 30:
Optimal Phase: 36
Window Length: 34
Eye Window: ______________XXXXXX____________________
Uplink 31:
Optimal Phase: 33
Window Length: 34
Eye Window: ___________XXXXXX_______________________
]
17:49:48:setup_element:INFO: Beginning SMX ASICs map scan
17:49:48:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
17:49:48:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
17:49:48:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
17:49:48:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
17:49:48:uplink:INFO: Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
17:49:48:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 23
17:49:48:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 22
17:49:48:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 30
17:49:48:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 31
17:49:49:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 21
17:49:49:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 20
17:49:49:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28
17:49:49:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 29
17:49:49:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 19
17:49:49:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 18
17:49:49:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26
17:49:49:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 27
17:49:49:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 17
17:49:49:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 16
17:49:49:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 24
17:49:49:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 25
17:49:51:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 23), (1, 22)
ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
ASIC address 0x2: (ASIC uplink, uplink): (0, 21), (1, 20)
ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
ASIC address 0x4: (ASIC uplink, uplink): (0, 19), (1, 18)
ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
ASIC address 0x6: (ASIC uplink, uplink): (0, 17), (1, 16)
ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
Clock Phase Characteristic:
Optimal Phase: 36
Window Length: 70
Eye Windows:
Uplink 16: __________________________________________________________________________XXXXXX
Uplink 17: __________________________________________________________________________XXXXXX
Uplink 18: _________________________________________________________________________XXXXXXX
Uplink 19: _________________________________________________________________________XXXXXXX
Uplink 20: ________________________________________________________________________XXXXXXXX
Uplink 21: ________________________________________________________________________XXXXXXXX
Uplink 22: _________________________________________________________________________XXXXXXX
Uplink 23: _________________________________________________________________________XXXXXXX
Uplink 24: __________________________________________________________________________XXXXX_
Uplink 25: __________________________________________________________________________XXXXX_
Uplink 26: _________________________________________________________________________XXXXXX_
Uplink 27: _________________________________________________________________________XXXXXX_
Uplink 28: __________________________________________________________________________XXXXXX
Uplink 29: __________________________________________________________________________XXXXXX
Uplink 30: XX_________________________________________________________________________XXXXX
Uplink 31: XX_________________________________________________________________________XXXXX
Data phase characteristics:
Uplink 16:
Optimal Phase: 16
Window Length: 35
Eye Window: __________________________________XXXXX_
Uplink 17:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 18:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
Uplink 19:
Optimal Phase: 13
Window Length: 34
Eye Window: _______________________________XXXXXX___
Uplink 20:
Optimal Phase: 13
Window Length: 34
Eye Window: _______________________________XXXXXX___
Uplink 21:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 22:
Optimal Phase: 15
Window Length: 34
Eye Window: _________________________________XXXXXX_
Uplink 23:
Optimal Phase: 14
Window Length: 35
Eye Window: ________________________________XXXXX___
Uplink 24:
Optimal Phase: 14
Window Length: 16
Eye Window: ___XXXX________________XXXXXXXXXXXXXXXXX
Uplink 25:
Optimal Phase: 16
Window Length: 12
Eye Window: ____XXXXX_X____________XXXXXXXXXXXXXXXXX
Uplink 26:
Optimal Phase: 24
Window Length: 36
Eye Window: ___XXXX_________________________________
Uplink 27:
Optimal Phase: 27
Window Length: 36
Eye Window: ______XXXX______________________________
Uplink 28:
Optimal Phase: 30
Window Length: 35
Eye Window: ________XXXXX___________________________
Uplink 29:
Optimal Phase: 30
Window Length: 34
Eye Window: ________XXXXXX__________________________
Uplink 30:
Optimal Phase: 36
Window Length: 34
Eye Window: ______________XXXXXX____________________
Uplink 31:
Optimal Phase: 33
Window Length: 34
Eye Window: ___________XXXXXX_______________________
17:49:51:setup_element:INFO: Performing Elink synchronization
17:49:51:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
17:49:51:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
17:49:51:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
17:49:51:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
17:49:51:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2
17:49:51:uplink:INFO: Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
17:49:51:ST3_emu:INFO: Number of chips: 8
addr | upli | dwnli | grp | uplinks | uplinks_map
0 | [0] | 2 | 0 | [23] | [(0, 23), (1, 22)]
1 | [0] | 2 | 0 | [30] | [(0, 30), (1, 31)]
2 | [0] | 2 | 0 | [21] | [(0, 21), (1, 20)]
3 | [0] | 2 | 0 | [28] | [(0, 28), (1, 29)]
4 | [0] | 2 | 0 | [19] | [(0, 19), (1, 18)]
5 | [0] | 2 | 0 | [26] | [(0, 26), (1, 27)]
6 | [0] | 2 | 0 | [17] | [(0, 17), (1, 16)]
7 | [0] | 2 | 0 | [24] | [(0, 24), (1, 25)]
17:49:51:febtest:INFO: Init all SMX (CSA): 30
17:50:04:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
17:50:04:febtest:INFO: 23-00 | XA-000-08-002-000-008-134-08 | 37.7 | 1153.7
17:50:04:febtest:INFO: 30-01 | XA-000-08-002-000-008-129-08 | 37.7 | 1153.7
17:50:04:febtest:INFO: 21-02 | XA-000-08-002-000-008-133-08 | 40.9 | 1135.9
17:50:05:febtest:INFO: 28-03 | XA-000-08-002-000-008-111-09 | 37.7 | 1159.7
17:50:05:febtest:INFO: 19-04 | XA-000-08-002-000-008-114-14 | 44.1 | 1135.9
17:50:05:febtest:INFO: 26-05 | XA-000-08-002-000-008-125-14 | 44.1 | 1135.9
17:50:05:febtest:INFO: 17-06 | XA-000-08-002-000-008-132-08 | 25.1 | 1183.3
17:50:06:febtest:INFO: 24-07 | XA-000-08-002-000-008-126-14 | 44.1 | 1130.0
17:50:07:febtest:INFO: Set all CSA to ZERO
FEB type: B FEB_A: 0 FEB_B: 1
17:50:08:ST3_smx:INFO: chip: 30-1 37.726682 C 1177.390875 mV
17:50:08:ST3_smx:INFO: Electrons
17:50:08:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
17:50:15:ST3_smx:INFO: ----> Checking Analog response
17:50:15:ST3_smx:INFO: ----> Checking broken channels
17:50:18:ST3_smx:INFO: Total # broken ch: 0
17:50:18:ST3_smx:INFO: List FAST: []
17:50:18:ST3_smx:INFO: List SLOW: []
17:50:18:ST3_smx:INFO: Holes
17:50:18:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
17:50:25:ST3_smx:INFO: ----> Checking Analog response
17:50:25:ST3_smx:INFO: ----> Checking broken channels
17:50:29:ST3_smx:INFO: Total # broken ch: 0
17:50:29:ST3_smx:INFO: List FAST: []
17:50:29:ST3_smx:INFO: List SLOW: []
17:50:30:ST3_smx:INFO: chip: 28-3 34.556970 C 1177.390875 mV
17:50:30:ST3_smx:INFO: Electrons
17:50:30:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
17:50:37:ST3_smx:INFO: ----> Checking Analog response
17:50:37:ST3_smx:INFO: ----> Checking broken channels
17:50:39:ST3_smx:INFO: Total # broken ch: 1
17:50:39:ST3_smx:INFO: List FAST: []
17:50:39:ST3_smx:INFO: List SLOW: [40]
17:50:39:ST3_smx:INFO: Holes
17:50:39:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
17:50:46:ST3_smx:INFO: ----> Checking Analog response
17:50:46:ST3_smx:INFO: ----> Checking broken channels
17:50:49:ST3_smx:INFO: Total # broken ch: 1
17:50:49:ST3_smx:INFO: List FAST: []
17:50:49:ST3_smx:INFO: List SLOW: [40]
17:50:51:ST3_smx:INFO: chip: 26-5 44.073563 C 1147.806000 mV
17:50:51:ST3_smx:INFO: Electrons
17:50:51:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
17:50:58:ST3_smx:INFO: ----> Checking Analog response
17:50:58:ST3_smx:INFO: ----> Checking broken channels
17:51:00:ST3_smx:INFO: Total # broken ch: 0
17:51:00:ST3_smx:INFO: List FAST: []
17:51:00:ST3_smx:INFO: List SLOW: []
17:51:00:ST3_smx:INFO: Holes
17:51:00:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
17:51:07:ST3_smx:INFO: ----> Checking Analog response
17:51:07:ST3_smx:INFO: ----> Checking broken channels
17:51:10:ST3_smx:INFO: Total # broken ch: 0
17:51:10:ST3_smx:INFO: List FAST: []
17:51:10:ST3_smx:INFO: List SLOW: []
17:51:12:ST3_smx:INFO: chip: 24-7 44.073563 C 1147.806000 mV
17:51:12:ST3_smx:INFO: Electrons
17:51:12:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
17:51:18:ST3_smx:INFO: ----> Checking Analog response
17:51:18:ST3_smx:INFO: ----> Checking broken channels
17:51:21:ST3_smx:INFO: Total # broken ch: 0
17:51:21:ST3_smx:INFO: List FAST: []
17:51:21:ST3_smx:INFO: List SLOW: []
17:51:21:ST3_smx:INFO: Holes
17:51:21:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
17:51:28:ST3_smx:INFO: ----> Checking Analog response
17:51:28:ST3_smx:INFO: ----> Checking broken channels
17:51:31:ST3_smx:INFO: Total # broken ch: 0
17:51:31:ST3_smx:INFO: List FAST: []
17:51:31:ST3_smx:INFO: List SLOW: []
17:51:31:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
17:51:31:febtest:INFO: 23-00 | XA-000-08-002-000-008-134-08 | 37.7 | 1195.1
17:51:32:febtest:INFO: 30-01 | XA-000-08-002-000-008-129-08 | 40.9 | 1195.1
17:51:32:febtest:INFO: 21-02 | XA-000-08-002-000-008-133-08 | 44.1 | 1177.4
17:51:32:febtest:INFO: 28-03 | XA-000-08-002-000-008-111-09 | 37.7 | 1201.0
17:51:32:febtest:INFO: 19-04 | XA-000-08-002-000-008-114-14 | 44.1 | 1177.4
17:51:32:febtest:INFO: 26-05 | XA-000-08-002-000-008-125-14 | 47.3 | 1165.6
17:51:33:febtest:INFO: 17-06 | XA-000-08-002-000-008-132-08 | 28.2 | 1224.5
17:51:33:febtest:INFO: 24-07 | XA-000-08-002-000-008-126-14 | 44.1 | 1171.5
############################################################
# S U M M A R Y #
############################################################
{'CSA_FRONT': 1, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 1, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 1, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 1, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 1, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 1, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 1, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 1, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 1, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 1, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 1, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 1, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 1, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 1, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 1, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 1, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-ASIC
TEST_DATE : 24_05_23-17_49_40
OPERATOR : Alois Alzheimer
SITE : GSI | SETUP : TEST_SETUP_3
------------------------------------------------------------
| FEB_SN : 2002| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_B
------------------------------------------------------------
MODULE_NAME
------------------------------------------------------------
VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.800', '1.6690', '2.199', '2.7270']
VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.800', '1.9950', '2.200', '2.5210']
VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.800', '1.9710', '2.200', '0.2330']