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FEB_2003 10.07.23 16:08:53
Info
16:08:01:ST3_hmp4040:INFO: ROHDE&SCHWARZ,HMP4040,106569,HW50020003/SW2.62
16:08:32:ST3_Shared:INFO: Listo of operators:Robert V.;
16:08:33:ST3_Shared:INFO: Listo of operators:Robert V.; Irakli K.;
16:08:40:febtest:INFO: FEB8.2 selected
16:08:40:smx_tester:INFO: Setting Elink clock mode to 160 MHz
16:08:53:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
16:08:53:ST3_Shared:INFO: --------------------------FEB-ASIC--------------------------
16:08:53:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
16:08:54:febtest:INFO: Tsting FEB with SN 2003
16:08:56:smx_tester:INFO: Scanning setup
16:08:56:elinks:INFO: Disabling clock on downlink 0
16:08:56:elinks:INFO: Disabling clock on downlink 1
16:08:56:elinks:INFO: Disabling clock on downlink 2
16:08:56:elinks:INFO: Disabling clock on downlink 3
16:08:56:elinks:INFO: Disabling clock on downlink 4
16:08:56:setup_element:INFO: Checking SOS, encoding_mode: SOS
16:08:56:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
16:08:56:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
16:08:56:elinks:INFO: Disabling clock on downlink 0
16:08:56:elinks:INFO: Disabling clock on downlink 1
16:08:56:elinks:INFO: Disabling clock on downlink 2
16:08:56:elinks:INFO: Disabling clock on downlink 3
16:08:56:elinks:INFO: Disabling clock on downlink 4
16:08:56:setup_element:INFO: Checking SOS, encoding_mode: SOS
16:08:56:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
16:08:56:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
16:08:56:elinks:INFO: Disabling clock on downlink 0
16:08:56:elinks:INFO: Disabling clock on downlink 1
16:08:56:elinks:INFO: Disabling clock on downlink 2
16:08:56:elinks:INFO: Disabling clock on downlink 3
16:08:56:elinks:INFO: Disabling clock on downlink 4
16:08:56:setup_element:INFO: Checking SOS, encoding_mode: SOS
16:08:56:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
16:08:56:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 16
16:08:56:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 17
16:08:56:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 18
16:08:56:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 19
16:08:56:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 20
16:08:56:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 21
16:08:56:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 22
16:08:56:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 23
16:08:56:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24
16:08:56:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25
16:08:56:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26
16:08:56:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28
16:08:56:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29
16:08:56:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30
16:08:56:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31
16:08:56:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
16:08:56:elinks:INFO: Disabling clock on downlink 0
16:08:56:elinks:INFO: Disabling clock on downlink 1
16:08:56:elinks:INFO: Disabling clock on downlink 2
16:08:57:elinks:INFO: Disabling clock on downlink 3
16:08:57:elinks:INFO: Disabling clock on downlink 4
16:08:57:setup_element:INFO: Checking SOS, encoding_mode: SOS
16:08:57:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
16:08:57:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
16:08:57:elinks:INFO: Disabling clock on downlink 0
16:08:57:elinks:INFO: Disabling clock on downlink 1
16:08:57:elinks:INFO: Disabling clock on downlink 2
16:08:57:elinks:INFO: Disabling clock on downlink 3
16:08:57:elinks:INFO: Disabling clock on downlink 4
16:08:57:setup_element:INFO: Checking SOS, encoding_mode: SOS
16:08:57:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
16:08:57:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
16:08:57:setup_element:INFO: Scanning clock phase
16:08:57:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
16:08:57:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
16:08:57:setup_element:INFO: Clock phase scan results for group 0, downlink 2
16:08:57:setup_element:INFO: Eye window for uplink 16: ________________________________________________________________________XXXXXX__
Clock Delay: 34
16:08:57:setup_element:INFO: Eye window for uplink 17: ________________________________________________________________________XXXXXX__
Clock Delay: 34
16:08:57:setup_element:INFO: Eye window for uplink 18: XXXX_____________________________________________________________XXXXXXXXXXXXXXX
Clock Delay: 34
16:08:57:setup_element:INFO: Eye window for uplink 19: XXXX_____________________________________________________________XXXXXXXXXXXXXXX
Clock Delay: 34
16:08:57:setup_element:INFO: Eye window for uplink 20: ___________________________________________________________________XXXXXXXXXX___
Clock Delay: 31
16:08:57:setup_element:INFO: Eye window for uplink 21: ___________________________________________________________________XXXXXXXXXX___
Clock Delay: 31
16:08:57:setup_element:INFO: Eye window for uplink 22: _________________________________________________________________XXXXXXXXXX_____
Clock Delay: 29
16:08:57:setup_element:INFO: Eye window for uplink 23: _________________________________________________________________XXXXXXXXXX_____
Clock Delay: 29
16:08:57:setup_element:INFO: Eye window for uplink 24: ______________________________________________________________XXXXXXXXXXXXXXXXXX
Clock Delay: 30
16:08:57:setup_element:INFO: Eye window for uplink 25: ______________________________________________________________XXXXXXXXXXXXXXXXXX
Clock Delay: 30
16:08:57:setup_element:INFO: Eye window for uplink 26: ________________________________________________________________________X_X_____
Clock Delay: 33
16:08:57:setup_element:INFO: Eye window for uplink 28: __________________________________________________________________XXXXXXXXXX____
Clock Delay: 30
16:08:57:setup_element:INFO: Eye window for uplink 29: __________________________________________________________________XXXXXXXXXX____
Clock Delay: 30
16:08:57:setup_element:INFO: Eye window for uplink 30: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
16:08:57:setup_element:INFO: Eye window for uplink 31: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
16:08:57:setup_element:INFO: Setting the clock phase to 32 for group 0, downlink 2
16:08:57:setup_element:INFO: Scanning data phases
16:08:57:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
16:08:57:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
16:09:03:setup_element:INFO: Data phase scan results for group 0, downlink 2
16:09:03:setup_element:INFO: Eye window for uplink 16: XXXXX______________________________XXXXX
Data delay found: 19
16:09:03:setup_element:INFO: Eye window for uplink 17: X______________________________XXXXXXXXX
Data delay found: 15
16:09:03:setup_element:INFO: Eye window for uplink 18: XXXXX__________________________XXXXXXXXX
Data delay found: 17
16:09:03:setup_element:INFO: Eye window for uplink 19: XXX__________________________XXXXXXXXXXX
Data delay found: 15
16:09:03:setup_element:INFO: Eye window for uplink 20: X________________________________XXXXXXX
Data delay found: 16
16:09:03:setup_element:INFO: Eye window for uplink 21: ________________________________XXXXXXXX
Data delay found: 15
16:09:03:setup_element:INFO: Eye window for uplink 22: __________________________________XXXX__
Data delay found: 15
16:09:03:setup_element:INFO: Eye window for uplink 23: ________________________________XXXXX___
Data delay found: 14
16:09:03:setup_element:INFO: Eye window for uplink 24: ____XXXXXX______________________________
Data delay found: 26
16:09:03:setup_element:INFO: Eye window for uplink 25: _______XXXXX____________________________
Data delay found: 29
16:09:03:setup_element:INFO: Eye window for uplink 26: ____XXXXXX______________________________
Data delay found: 26
16:09:03:setup_element:INFO: Eye window for uplink 28: __________________XXXXX_________________
Data delay found: 0
16:09:03:setup_element:INFO: Eye window for uplink 29: ____________________XXXXX_______________
Data delay found: 2
16:09:03:setup_element:INFO: Eye window for uplink 30: ____________________XXXXXX______________
Data delay found: 2
16:09:03:setup_element:INFO: Eye window for uplink 31: __________________XXXXXX________________
Data delay found: 0
16:09:03:setup_element:INFO: Setting the data phase to 19 for uplink 16
16:09:03:setup_element:INFO: Setting the data phase to 15 for uplink 17
16:09:03:setup_element:INFO: Setting the data phase to 17 for uplink 18
16:09:03:setup_element:INFO: Setting the data phase to 15 for uplink 19
16:09:03:setup_element:INFO: Setting the data phase to 16 for uplink 20
16:09:03:setup_element:INFO: Setting the data phase to 15 for uplink 21
16:09:03:setup_element:INFO: Setting the data phase to 15 for uplink 22
16:09:03:setup_element:INFO: Setting the data phase to 14 for uplink 23
16:09:03:setup_element:INFO: Setting the data phase to 26 for uplink 24
16:09:03:setup_element:INFO: Setting the data phase to 29 for uplink 25
16:09:03:setup_element:INFO: Setting the data phase to 26 for uplink 26
16:09:03:setup_element:INFO: Setting the data phase to 0 for uplink 28
16:09:03:setup_element:INFO: Setting the data phase to 2 for uplink 29
16:09:03:setup_element:INFO: Setting the data phase to 2 for uplink 30
16:09:03:setup_element:INFO: Setting the data phase to 0 for uplink 31
16:09:03:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 28, 29, 30, 31]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 32
Window Length: 58
Eye Windows:
Uplink 16: ________________________________________________________________________XXXXXX__
Uplink 17: ________________________________________________________________________XXXXXX__
Uplink 18: XXXX_____________________________________________________________XXXXXXXXXXXXXXX
Uplink 19: XXXX_____________________________________________________________XXXXXXXXXXXXXXX
Uplink 20: ___________________________________________________________________XXXXXXXXXX___
Uplink 21: ___________________________________________________________________XXXXXXXXXX___
Uplink 22: _________________________________________________________________XXXXXXXXXX_____
Uplink 23: _________________________________________________________________XXXXXXXXXX_____
Uplink 24: ______________________________________________________________XXXXXXXXXXXXXXXXXX
Uplink 25: ______________________________________________________________XXXXXXXXXXXXXXXXXX
Uplink 26: ________________________________________________________________________X_X_____
Uplink 28: __________________________________________________________________XXXXXXXXXX____
Uplink 29: __________________________________________________________________XXXXXXXXXX____
Uplink 30: ____________________________________________________________________XXXXXXXX____
Uplink 31: ____________________________________________________________________XXXXXXXX____
Data phase characteristics:
Uplink 16:
Optimal Phase: 19
Window Length: 30
Eye Window: XXXXX______________________________XXXXX
Uplink 17:
Optimal Phase: 15
Window Length: 30
Eye Window: X______________________________XXXXXXXXX
Uplink 18:
Optimal Phase: 17
Window Length: 26
Eye Window: XXXXX__________________________XXXXXXXXX
Uplink 19:
Optimal Phase: 15
Window Length: 26
Eye Window: XXX__________________________XXXXXXXXXXX
Uplink 20:
Optimal Phase: 16
Window Length: 32
Eye Window: X________________________________XXXXXXX
Uplink 21:
Optimal Phase: 15
Window Length: 32
Eye Window: ________________________________XXXXXXXX
Uplink 22:
Optimal Phase: 15
Window Length: 36
Eye Window: __________________________________XXXX__
Uplink 23:
Optimal Phase: 14
Window Length: 35
Eye Window: ________________________________XXXXX___
Uplink 24:
Optimal Phase: 26
Window Length: 34
Eye Window: ____XXXXXX______________________________
Uplink 25:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 26:
Optimal Phase: 26
Window Length: 34
Eye Window: ____XXXXXX______________________________
Uplink 28:
Optimal Phase: 0
Window Length: 35
Eye Window: __________________XXXXX_________________
Uplink 29:
Optimal Phase: 2
Window Length: 35
Eye Window: ____________________XXXXX_______________
Uplink 30:
Optimal Phase: 2
Window Length: 34
Eye Window: ____________________XXXXXX______________
Uplink 31:
Optimal Phase: 0
Window Length: 34
Eye Window: __________________XXXXXX________________
]
16:09:03:setup_element:INFO: Beginning SMX ASICs map scan
16:09:03:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
16:09:03:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
16:09:03:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
16:09:03:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
16:09:03:uplink:INFO: Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 28, 29, 30, 31]
16:09:03:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 23
16:09:03:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 22
16:09:03:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 30
16:09:03:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 31
16:09:03:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 21
16:09:03:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 20
16:09:03:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28
16:09:04:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 29
16:09:04:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 19
16:09:04:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 18
16:09:04:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26
16:09:04:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 17
16:09:04:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 16
16:09:04:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 24
16:09:04:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 25
16:09:06:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 28, 29, 30, 31]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 23), (1, 22)
ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
ASIC address 0x2: (ASIC uplink, uplink): (0, 21), (1, 20)
ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
ASIC address 0x4: (ASIC uplink, uplink): (0, 19), (1, 18)
ASIC address 0x5: (ASIC uplink, uplink): (0, 26)
ASIC address 0x6: (ASIC uplink, uplink): (0, 17), (1, 16)
ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
Clock Phase Characteristic:
Optimal Phase: 32
Window Length: 58
Eye Windows:
Uplink 16: ________________________________________________________________________XXXXXX__
Uplink 17: ________________________________________________________________________XXXXXX__
Uplink 18: XXXX_____________________________________________________________XXXXXXXXXXXXXXX
Uplink 19: XXXX_____________________________________________________________XXXXXXXXXXXXXXX
Uplink 20: ___________________________________________________________________XXXXXXXXXX___
Uplink 21: ___________________________________________________________________XXXXXXXXXX___
Uplink 22: _________________________________________________________________XXXXXXXXXX_____
Uplink 23: _________________________________________________________________XXXXXXXXXX_____
Uplink 24: ______________________________________________________________XXXXXXXXXXXXXXXXXX
Uplink 25: ______________________________________________________________XXXXXXXXXXXXXXXXXX
Uplink 26: ________________________________________________________________________X_X_____
Uplink 28: __________________________________________________________________XXXXXXXXXX____
Uplink 29: __________________________________________________________________XXXXXXXXXX____
Uplink 30: ____________________________________________________________________XXXXXXXX____
Uplink 31: ____________________________________________________________________XXXXXXXX____
Data phase characteristics:
Uplink 16:
Optimal Phase: 19
Window Length: 30
Eye Window: XXXXX______________________________XXXXX
Uplink 17:
Optimal Phase: 15
Window Length: 30
Eye Window: X______________________________XXXXXXXXX
Uplink 18:
Optimal Phase: 17
Window Length: 26
Eye Window: XXXXX__________________________XXXXXXXXX
Uplink 19:
Optimal Phase: 15
Window Length: 26
Eye Window: XXX__________________________XXXXXXXXXXX
Uplink 20:
Optimal Phase: 16
Window Length: 32
Eye Window: X________________________________XXXXXXX
Uplink 21:
Optimal Phase: 15
Window Length: 32
Eye Window: ________________________________XXXXXXXX
Uplink 22:
Optimal Phase: 15
Window Length: 36
Eye Window: __________________________________XXXX__
Uplink 23:
Optimal Phase: 14
Window Length: 35
Eye Window: ________________________________XXXXX___
Uplink 24:
Optimal Phase: 26
Window Length: 34
Eye Window: ____XXXXXX______________________________
Uplink 25:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 26:
Optimal Phase: 26
Window Length: 34
Eye Window: ____XXXXXX______________________________
Uplink 28:
Optimal Phase: 0
Window Length: 35
Eye Window: __________________XXXXX_________________
Uplink 29:
Optimal Phase: 2
Window Length: 35
Eye Window: ____________________XXXXX_______________
Uplink 30:
Optimal Phase: 2
Window Length: 34
Eye Window: ____________________XXXXXX______________
Uplink 31:
Optimal Phase: 0
Window Length: 34
Eye Window: __________________XXXXXX________________
16:09:06:setup_element:INFO: Performing Elink synchronization
16:09:06:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
16:09:06:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
16:09:06:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
16:09:06:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
16:09:06:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2
16:09:06:uplink:INFO: Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 28, 29, 30, 31]
16:09:06:ST3_emu:INFO: Number of chips: 8
16:09:06:ST3_emu:INFO: Chip address: 0x0
16:09:06:ST3_emu:INFO: Chip address: 0x1
16:09:06:ST3_emu:INFO: Chip address: 0x2
16:09:06:ST3_emu:INFO: Chip address: 0x3
16:09:06:ST3_emu:INFO: Chip address: 0x4
16:09:06:ST3_emu:INFO: Chip address: 0x5
16:09:06:ST3_emu:INFO: Chip address: 0x6
16:09:06:ST3_emu:INFO: Chip address: 0x7
16:09:08:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:09:08:febtest:INFO: 0-0 | XA-000-08-002-000-008-098-09 | 25.1 | 1224.5
16:09:08:febtest:INFO: 0-1 | XA-000-08-002-000-008-109-09 | 25.1 | 1230.3
16:09:08:febtest:INFO: 0-2 | XA-000-08-002-000-008-100-09 | 34.6 | 1201.0
16:09:09:febtest:INFO: 0-3 | XA-000-08-002-000-008-106-09 | 28.2 | 1218.6
16:09:09:febtest:INFO: 0-4 | XA-000-08-002-000-008-102-09 | 25.1 | 1242.0
16:09:09:febtest:INFO: 0-5 | XA-000-08-002-000-008-113-14 | 34.6 | 1189.2
16:09:09:febtest:INFO: 0-6 | XA-000-08-002-000-008-103-09 | 28.2 | 1224.5
16:09:10:febtest:INFO: 0-7 | XA-000-08-002-000-008-108-09 | 18.7 | 1247.9
16:09:10:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:09:13:ST3_smx:INFO: chip: 0-0 25.062742 C 1212.728715 mV
16:09:13:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
16:09:13:ST3_smx:INFO: Electrons
16:09:13:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
16:09:15:ST3_smx:INFO: ----> Checking Analog response
16:09:15:ST3_smx:INFO: ----> Checking broken channels
16:09:16:ST3_smx:INFO: Total # broken ch: 0
16:09:16:ST3_smx:INFO: List FAST: []
16:09:16:ST3_smx:INFO: List SLOW: []
16:09:16:ST3_smx:INFO: Holes
16:09:16:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
16:09:18:ST3_smx:INFO: ----> Checking Analog response
16:09:18:ST3_smx:INFO: ----> Checking broken channels
16:09:18:ST3_smx:INFO: Total # broken ch: 0
16:09:18:ST3_smx:INFO: List FAST: []
16:09:18:ST3_smx:INFO: List SLOW: []
16:09:18:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:09:18:febtest:INFO: 0-0 | XA-000-08-002-000-008-098-09 | 28.2 | 1212.7
16:09:18:febtest:INFO: 0-1 | XA-000-08-002-000-008-109-09 | 21.9 | 1230.3
16:09:19:febtest:INFO: 0-2 | XA-000-08-002-000-008-100-09 | 34.6 | 1201.0
16:09:19:febtest:INFO: 0-3 | XA-000-08-002-000-008-106-09 | 28.2 | 1218.6
16:09:19:febtest:INFO: 0-4 | XA-000-08-002-000-008-102-09 | 25.1 | 1236.2
16:09:19:febtest:INFO: 0-5 | XA-000-08-002-000-008-113-14 | 34.6 | 1189.2
16:09:20:febtest:INFO: 0-6 | XA-000-08-002-000-008-103-09 | 28.2 | 1218.6
16:09:20:febtest:INFO: 0-7 | XA-000-08-002-000-008-108-09 | 18.7 | 1247.9
16:09:21:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:09:25:ST3_smx:INFO: chip: 0-1 21.902970 C 1218.600960 mV
16:09:25:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
16:09:25:ST3_smx:INFO: Electrons
16:09:25:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
16:09:27:ST3_smx:INFO: ----> Checking Analog response
16:09:27:ST3_smx:INFO: ----> Checking broken channels
16:09:27:ST3_smx:INFO: Total # broken ch: 0
16:09:27:ST3_smx:INFO: List FAST: []
16:09:27:ST3_smx:INFO: List SLOW: []
16:09:27:ST3_smx:INFO: Holes
16:09:27:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
16:09:29:ST3_smx:INFO: ----> Checking Analog response
16:09:29:ST3_smx:INFO: ----> Checking broken channels
16:09:29:ST3_smx:INFO: Total # broken ch: 0
16:09:29:ST3_smx:INFO: List FAST: []
16:09:29:ST3_smx:INFO: List SLOW: []
16:09:29:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:09:29:febtest:INFO: 0-0 | XA-000-08-002-000-008-098-09 | 28.2 | 1206.9
16:09:30:febtest:INFO: 0-1 | XA-000-08-002-000-008-109-09 | 25.1 | 1212.7
16:09:30:febtest:INFO: 0-2 | XA-000-08-002-000-008-100-09 | 34.6 | 1195.1
16:09:30:febtest:INFO: 0-3 | XA-000-08-002-000-008-106-09 | 28.2 | 1212.7
16:09:30:febtest:INFO: 0-4 | XA-000-08-002-000-008-102-09 | 25.1 | 1236.2
16:09:31:febtest:INFO: 0-5 | XA-000-08-002-000-008-113-14 | 34.6 | 1183.3
16:09:31:febtest:INFO: 0-6 | XA-000-08-002-000-008-103-09 | 28.2 | 1218.6
16:09:31:febtest:INFO: 0-7 | XA-000-08-002-000-008-108-09 | 18.7 | 1247.9
16:09:32:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:09:36:ST3_smx:INFO: chip: 0-2 37.726682 C 1171.483840 mV
16:09:36:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
16:09:36:ST3_smx:INFO: Electrons
16:09:36:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
16:09:38:ST3_smx:INFO: ----> Checking Analog response
16:09:38:ST3_smx:INFO: ----> Checking broken channels
16:09:38:ST3_smx:INFO: Total # broken ch: 0
16:09:38:ST3_smx:INFO: List FAST: []
16:09:38:ST3_smx:INFO: List SLOW: []
16:09:38:ST3_smx:INFO: Holes
16:09:38:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
16:09:40:ST3_smx:INFO: ----> Checking Analog response
16:09:40:ST3_smx:INFO: ----> Checking broken channels
16:09:40:ST3_smx:INFO: Total # broken ch: 0
16:09:40:ST3_smx:INFO: List FAST: []
16:09:40:ST3_smx:INFO: List SLOW: []
16:09:40:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:09:41:febtest:INFO: 0-0 | XA-000-08-002-000-008-098-09 | 28.2 | 1206.9
16:09:41:febtest:INFO: 0-1 | XA-000-08-002-000-008-109-09 | 25.1 | 1212.7
16:09:41:febtest:INFO: 0-2 | XA-000-08-002-000-008-100-09 | 40.9 | 1165.6
16:09:41:febtest:INFO: 0-3 | XA-000-08-002-000-008-106-09 | 28.2 | 1218.6
16:09:42:febtest:INFO: 0-4 | XA-000-08-002-000-008-102-09 | 25.1 | 1236.2
16:09:42:febtest:INFO: 0-5 | XA-000-08-002-000-008-113-14 | 34.6 | 1189.2
16:09:42:febtest:INFO: 0-6 | XA-000-08-002-000-008-103-09 | 28.2 | 1218.6
16:09:42:febtest:INFO: 0-7 | XA-000-08-002-000-008-108-09 | 18.7 | 1247.9
16:09:44:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:09:47:ST3_smx:INFO: chip: 0-3 28.225000 C 1206.851500 mV
16:09:47:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
16:09:47:ST3_smx:INFO: Electrons
16:09:47:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
16:09:49:ST3_smx:INFO: ----> Checking Analog response
16:09:49:ST3_smx:INFO: ----> Checking broken channels
16:09:49:ST3_smx:INFO: Total # broken ch: 0
16:09:49:ST3_smx:INFO: List FAST: []
16:09:49:ST3_smx:INFO: List SLOW: []
16:09:49:ST3_smx:INFO: Holes
16:09:49:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
16:09:51:ST3_smx:INFO: ----> Checking Analog response
16:09:51:ST3_smx:INFO: ----> Checking broken channels
16:09:52:ST3_smx:INFO: Total # broken ch: 0
16:09:52:ST3_smx:INFO: List FAST: []
16:09:52:ST3_smx:INFO: List SLOW: []
16:09:52:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:09:52:febtest:INFO: 0-0 | XA-000-08-002-000-008-098-09 | 28.2 | 1206.9
16:09:52:febtest:INFO: 0-1 | XA-000-08-002-000-008-109-09 | 25.1 | 1212.7
16:09:52:febtest:INFO: 0-2 | XA-000-08-002-000-008-100-09 | 40.9 | 1165.6
16:09:53:febtest:INFO: 0-3 | XA-000-08-002-000-008-106-09 | 31.4 | 1201.0
16:09:53:febtest:INFO: 0-4 | XA-000-08-002-000-008-102-09 | 25.1 | 1236.2
16:09:53:febtest:INFO: 0-5 | XA-000-08-002-000-008-113-14 | 34.6 | 1183.3
16:09:53:febtest:INFO: 0-6 | XA-000-08-002-000-008-103-09 | 31.4 | 1212.7
16:09:54:febtest:INFO: 0-7 | XA-000-08-002-000-008-108-09 | 18.7 | 1247.9
16:09:55:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:09:58:ST3_smx:INFO: chip: 0-4 28.225000 C 1206.851500 mV
16:09:58:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
16:09:58:ST3_smx:INFO: Electrons
16:09:58:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
16:10:00:ST3_smx:INFO: ----> Checking Analog response
16:10:00:ST3_smx:INFO: ----> Checking broken channels
16:10:00:ST3_smx:INFO: Total # broken ch: 0
16:10:00:ST3_smx:INFO: List FAST: []
16:10:00:ST3_smx:INFO: List SLOW: []
16:10:00:ST3_smx:INFO: Holes
16:10:01:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
16:10:02:ST3_smx:INFO: ----> Checking Analog response
16:10:02:ST3_smx:INFO: ----> Checking broken channels
16:10:03:ST3_smx:INFO: Total # broken ch: 0
16:10:03:ST3_smx:INFO: List FAST: []
16:10:03:ST3_smx:INFO: List SLOW: []
16:10:03:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:10:03:febtest:INFO: 0-0 | XA-000-08-002-000-008-098-09 | 25.1 | 1206.9
16:10:03:febtest:INFO: 0-1 | XA-000-08-002-000-008-109-09 | 25.1 | 1218.6
16:10:03:febtest:INFO: 0-2 | XA-000-08-002-000-008-100-09 | 37.7 | 1171.5
16:10:04:febtest:INFO: 0-3 | XA-000-08-002-000-008-106-09 | 28.2 | 1201.0
16:10:04:febtest:INFO: 0-4 | XA-000-08-002-000-008-102-09 | 31.4 | 1201.0
16:10:04:febtest:INFO: 0-5 | XA-000-08-002-000-008-113-14 | 34.6 | 1189.2
16:10:04:febtest:INFO: 0-6 | XA-000-08-002-000-008-103-09 | 31.4 | 1218.6
16:10:04:febtest:INFO: 0-7 | XA-000-08-002-000-008-108-09 | 18.7 | 1247.9
16:10:06:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:10:09:ST3_smx:INFO: chip: 0-5 31.389742 C 1189.190035 mV
16:10:09:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
16:10:09:ST3_smx:INFO: Electrons
16:10:09:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
16:10:11:ST3_smx:INFO: ----> Checking Analog response
16:10:11:ST3_smx:INFO: ----> Checking broken channels
16:10:11:ST3_smx:INFO: Total # broken ch: 0
16:10:11:ST3_smx:INFO: List FAST: []
16:10:11:ST3_smx:INFO: List SLOW: []
16:10:11:ST3_smx:INFO: Holes
16:10:11:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
16:10:13:ST3_smx:INFO: ----> Checking Analog response
16:10:13:ST3_smx:INFO: ----> Checking broken channels
16:10:14:ST3_smx:INFO: Total # broken ch: 0
16:10:14:ST3_smx:INFO: List FAST: []
16:10:14:ST3_smx:INFO: List SLOW: []
16:10:14:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:10:14:febtest:INFO: 0-0 | XA-000-08-002-000-008-098-09 | 25.1 | 1206.9
16:10:14:febtest:INFO: 0-1 | XA-000-08-002-000-008-109-09 | 21.9 | 1212.7
16:10:14:febtest:INFO: 0-2 | XA-000-08-002-000-008-100-09 | 40.9 | 1165.6
16:10:15:febtest:INFO: 0-3 | XA-000-08-002-000-008-106-09 | 28.2 | 1201.0
16:10:15:febtest:INFO: 0-4 | XA-000-08-002-000-008-102-09 | 31.4 | 1201.0
16:10:15:febtest:INFO: 0-5 | XA-000-08-002-000-008-113-14 | 31.4 | 1183.3
16:10:15:febtest:INFO: 0-6 | XA-000-08-002-000-008-103-09 | 28.2 | 1212.7
16:10:16:febtest:INFO: 0-7 | XA-000-08-002-000-008-108-09 | 18.7 | 1242.0
16:10:17:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:10:20:ST3_smx:INFO: chip: 0-6 34.556970 C 1183.292940 mV
16:10:20:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
16:10:20:ST3_smx:INFO: Electrons
16:10:21:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
16:10:22:ST3_smx:INFO: ----> Checking Analog response
16:10:22:ST3_smx:INFO: ----> Checking broken channels
16:10:23:ST3_smx:INFO: Total # broken ch: 0
16:10:23:ST3_smx:INFO: List FAST: []
16:10:23:ST3_smx:INFO: List SLOW: []
16:10:23:ST3_smx:INFO: Holes
16:10:23:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
16:10:25:ST3_smx:INFO: ----> Checking Analog response
16:10:25:ST3_smx:INFO: ----> Checking broken channels
16:10:25:ST3_smx:INFO: Total # broken ch: 0
16:10:25:ST3_smx:INFO: List FAST: []
16:10:25:ST3_smx:INFO: List SLOW: []
16:10:25:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:10:25:febtest:INFO: 0-0 | XA-000-08-002-000-008-098-09 | 25.1 | 1206.9
16:10:25:febtest:INFO: 0-1 | XA-000-08-002-000-008-109-09 | 21.9 | 1218.6
16:10:26:febtest:INFO: 0-2 | XA-000-08-002-000-008-100-09 | 37.7 | 1171.5
16:10:26:febtest:INFO: 0-3 | XA-000-08-002-000-008-106-09 | 28.2 | 1206.9
16:10:26:febtest:INFO: 0-4 | XA-000-08-002-000-008-102-09 | 28.2 | 1206.9
16:10:26:febtest:INFO: 0-5 | XA-000-08-002-000-008-113-14 | 31.4 | 1189.2
16:10:27:febtest:INFO: 0-6 | XA-000-08-002-000-008-103-09 | 37.7 | 1177.4
16:10:27:febtest:INFO: 0-7 | XA-000-08-002-000-008-108-09 | 18.7 | 1247.9
16:10:28:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:10:31:ST3_smx:INFO: chip: 0-7 25.062742 C 1212.728715 mV
16:10:31:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
16:10:31:ST3_smx:INFO: Electrons
16:10:31:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
16:10:33:ST3_smx:INFO: ----> Checking Analog response
16:10:33:ST3_smx:INFO: ----> Checking broken channels
16:10:34:ST3_smx:INFO: Total # broken ch: 0
16:10:34:ST3_smx:INFO: List FAST: []
16:10:34:ST3_smx:INFO: List SLOW: []
16:10:34:ST3_smx:INFO: Holes
16:10:34:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
16:10:36:ST3_smx:INFO: ----> Checking Analog response
16:10:36:ST3_smx:INFO: ----> Checking broken channels
16:10:36:ST3_smx:INFO: Total # broken ch: 0
16:10:36:ST3_smx:INFO: List FAST: []
16:10:36:ST3_smx:INFO: List SLOW: []
16:10:36:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:10:36:febtest:INFO: 0-0 | XA-000-08-002-000-008-098-09 | 25.1 | 1212.7
16:10:36:febtest:INFO: 0-1 | XA-000-08-002-000-008-109-09 | 18.7 | 1218.6
16:10:37:febtest:INFO: 0-2 | XA-000-08-002-000-008-100-09 | 37.7 | 1171.5
16:10:37:febtest:INFO: 0-3 | XA-000-08-002-000-008-106-09 | 25.1 | 1206.9
16:10:37:febtest:INFO: 0-4 | XA-000-08-002-000-008-102-09 | 28.2 | 1206.9
16:10:37:febtest:INFO: 0-5 | XA-000-08-002-000-008-113-14 | 28.2 | 1189.2
16:10:38:febtest:INFO: 0-6 | XA-000-08-002-000-008-103-09 | 34.6 | 1183.3
16:10:38:febtest:INFO: 0-7 | XA-000-08-002-000-008-108-09 | 25.1 | 1206.9
############################################################
# S U M M A R Y #
############################################################
{'TEST_NAME': 'FEB-ASIC', 'TEST_DATE': '2023_07_10-16_08_53', 'OPERATOR': 'Robert V.; Irakli K.; ', 'PROJECT': 'Test', 'SITE': 'GSI', 'SETUP': 'GSI_TEST_SETUP_1', 'ASIC_ID': 'XA-000-08-002-000-008-108-09', 'FUSED_ID': 6359364699116570313, 'HW_ADDR': 7, 'VERS_NO': '2.2', 'CABLE_SET_ID': '', 'IC_TEMP': '0', 'VDDM': '0', 'AUX': '0', 'CSABIAS': '0', 'VDDM_INT': '0', 'ADC_Chi2': 0.0, 'ADC_NDF': 0, 'ADC_P0': 0.0, 'ADC_P1': 0.006824, 'ADC_P2': -2.485e-06, 'ADC_P0err': 0.001, 'ADC_P1err': 0.001, 'ADC_P2err': 1e-05, 'ADC_VREF_P': 58, 'ADC_VREF_N': 30, 'ADC_VREF_T': 128, 'ADC_VREF_TR': 122, 'THR2_GLB': 30, 'LOOP__PLS': 100, 'CALIB_PLS': 250, 'SnsLoop': 5, 'IFED': 31, 'CSA_BIAS': 15, 'CSA_Chi2': 0.0, 'CSA_NDF': 0, 'CSA_P0': 0.0, 'CSA_P1': 0.0, 'CSA_P2': 0.0, 'CSA_P0err': 0.0, 'CSA_P1err': 0.0, 'CSA_P2err': 0.0, 'CONF_FAIL_REG': 0, 'N_BROKEN_DISC': 0, 'N_BROKEN_FAST': '[]', 'N_BROKEN_SLOW': '[]', 'P_BROKEN_DISC': 0, 'P_BROKEN_FAST': '[]', 'P_BROKEN_SLOW': '[]', 'ASIC_QA_category': '', 'N_BROKEN_CABLE': 0, 'LIST_OF_BROKEN_CABLES': 0, 'VI_bInit': ['0.000', '0.0000', '2.499', '1.7960', '2.198', '2.6390', '7.001', '1.5610'], 'VI_aInit': ['0', '0', '0', '0', '0', '0'], 'VI_atEnd': ['0', '0', '0', '0', '0', '0'], 'AMP_CAL': 200, 'PlsLoop': 3, 'N_ANA_PRESENT': 'Analog response OK', 'N_DISC_FAIL_CH': 0, 'N_ANA_FAIL_CH': '0', 'P_ANA_PRESENT': 'Analog response OK', 'P_DISC_FAIL_CH': 0, 'P_ANA_FAIL_CH': '0'}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
16:11:04:ST3_Shared:INFO: /home/cbm/public_html/Test_LogDir//FEB/FEB_2003/B//TestDate_2023_07_10-16_08_53/