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FEB_2004 11.07.23 11:10:47
Info
11:10:21:ST3_hmp4040:INFO: ROHDE&SCHWARZ,HMP4040,106569,HW50020003/SW2.62
11:10:30:ST3_Shared:INFO: Listo of operators:Robert V.;
11:10:33:febtest:INFO: FEB8.2 selected
11:10:33:smx_tester:INFO: Setting Elink clock mode to 160 MHz
11:10:47:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
11:10:47:ST3_Shared:INFO: --------------------------FEB-ASIC--------------------------
11:10:47:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
11:10:48:febtest:INFO: Tsting FEB with SN 2004
11:10:50:smx_tester:INFO: Scanning setup
11:10:50:elinks:INFO: Disabling clock on downlink 0
11:10:50:elinks:INFO: Disabling clock on downlink 1
11:10:50:elinks:INFO: Disabling clock on downlink 2
11:10:50:elinks:INFO: Disabling clock on downlink 3
11:10:50:elinks:INFO: Disabling clock on downlink 4
11:10:50:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:10:50:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
11:10:51:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:10:51:elinks:INFO: Disabling clock on downlink 0
11:10:51:elinks:INFO: Disabling clock on downlink 1
11:10:51:elinks:INFO: Disabling clock on downlink 2
11:10:51:elinks:INFO: Disabling clock on downlink 3
11:10:51:elinks:INFO: Disabling clock on downlink 4
11:10:51:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:10:51:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
11:10:51:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:10:51:elinks:INFO: Disabling clock on downlink 0
11:10:51:elinks:INFO: Disabling clock on downlink 1
11:10:51:elinks:INFO: Disabling clock on downlink 2
11:10:51:elinks:INFO: Disabling clock on downlink 3
11:10:51:elinks:INFO: Disabling clock on downlink 4
11:10:51:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:10:51:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
11:10:51:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 16
11:10:51:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 17
11:10:51:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 18
11:10:51:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 19
11:10:51:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 20
11:10:51:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 21
11:10:51:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 22
11:10:51:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 23
11:10:51:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24
11:10:51:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25
11:10:51:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26
11:10:51:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27
11:10:51:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28
11:10:51:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29
11:10:51:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30
11:10:51:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31
11:10:51:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:10:51:elinks:INFO: Disabling clock on downlink 0
11:10:51:elinks:INFO: Disabling clock on downlink 1
11:10:51:elinks:INFO: Disabling clock on downlink 2
11:10:51:elinks:INFO: Disabling clock on downlink 3
11:10:51:elinks:INFO: Disabling clock on downlink 4
11:10:51:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:10:51:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
11:10:51:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:10:51:elinks:INFO: Disabling clock on downlink 0
11:10:51:elinks:INFO: Disabling clock on downlink 1
11:10:51:elinks:INFO: Disabling clock on downlink 2
11:10:51:elinks:INFO: Disabling clock on downlink 3
11:10:51:elinks:INFO: Disabling clock on downlink 4
11:10:51:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:10:51:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
11:10:51:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:10:51:setup_element:INFO: Scanning clock phase
11:10:51:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
11:10:51:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
11:10:52:setup_element:INFO: Clock phase scan results for group 0, downlink 2
11:10:52:setup_element:INFO: Eye window for uplink 16: _______________________________________________________________________XXXXXXXXX
Clock Delay: 35
11:10:52:setup_element:INFO: Eye window for uplink 17: _______________________________________________________________________XXXXXXXXX
Clock Delay: 35
11:10:52:setup_element:INFO: Eye window for uplink 18: ________________________________________________________________________XXXXXXXX
Clock Delay: 35
11:10:52:setup_element:INFO: Eye window for uplink 19: ________________________________________________________________________XXXXXXXX
Clock Delay: 35
11:10:52:setup_element:INFO: Eye window for uplink 20: X_______________________________________________________________________XXXXXXXX
Clock Delay: 36
11:10:52:setup_element:INFO: Eye window for uplink 21: X_______________________________________________________________________XXXXXXXX
Clock Delay: 36
11:10:52:setup_element:INFO: Eye window for uplink 22: X_______________________________________________________________________XXXXXXXX
Clock Delay: 36
11:10:52:setup_element:INFO: Eye window for uplink 23: X_______________________________________________________________________XXXXXXXX
Clock Delay: 36
11:10:52:setup_element:INFO: Eye window for uplink 24: _______________________________________________________________________XXXXXXXXX
Clock Delay: 35
11:10:52:setup_element:INFO: Eye window for uplink 25: _______________________________________________________________________XXXXXXXXX
Clock Delay: 35
11:10:52:setup_element:INFO: Eye window for uplink 26: ________________________________________________________________________XXXXXXXX
Clock Delay: 35
11:10:52:setup_element:INFO: Eye window for uplink 27: ________________________________________________________________________XXXXXXXX
Clock Delay: 35
11:10:52:setup_element:INFO: Eye window for uplink 28: ________________________________________________________________________XXXXXXXX
Clock Delay: 35
11:10:52:setup_element:INFO: Eye window for uplink 29: ________________________________________________________________________XXXXXXXX
Clock Delay: 35
11:10:52:setup_element:INFO: Eye window for uplink 30: _________________________________________________________________________XXXXXXX
Clock Delay: 36
11:10:52:setup_element:INFO: Eye window for uplink 31: _________________________________________________________________________XXXXXXX
Clock Delay: 36
11:10:52:setup_element:INFO: Setting the clock phase to 35 for group 0, downlink 2
11:10:52:setup_element:INFO: Scanning data phases
11:10:52:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
11:10:52:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
11:10:57:setup_element:INFO: Data phase scan results for group 0, downlink 2
11:10:57:setup_element:INFO: Eye window for uplink 16: XX___________________________________XXX
Data delay found: 19
11:10:57:setup_element:INFO: Eye window for uplink 17: _________________________________XXXXX__
Data delay found: 15
11:10:57:setup_element:INFO: Eye window for uplink 18: XX__________________________________XXXX
Data delay found: 18
11:10:57:setup_element:INFO: Eye window for uplink 19: _________________________________XXXXXX_
Data delay found: 15
11:10:57:setup_element:INFO: Eye window for uplink 20: XX___________________________________XXX
Data delay found: 19
11:10:57:setup_element:INFO: Eye window for uplink 21: X___________________________________XXXX
Data delay found: 18
11:10:57:setup_element:INFO: Eye window for uplink 22: XX__________________________________XXXX
Data delay found: 18
11:10:57:setup_element:INFO: Eye window for uplink 23: _________________________________XXXXXX_
Data delay found: 15
11:10:57:setup_element:INFO: Eye window for uplink 24: ______XXXXX_____________________________
Data delay found: 28
11:10:57:setup_element:INFO: Eye window for uplink 25: ________XXXXXX__________________________
Data delay found: 30
11:10:57:setup_element:INFO: Eye window for uplink 26: _______XXXXX____________________________
Data delay found: 29
11:10:57:setup_element:INFO: Eye window for uplink 27: __________XXXXXX________________________
Data delay found: 32
11:10:57:setup_element:INFO: Eye window for uplink 28: ____________XXXXX_______________________
Data delay found: 34
11:10:57:setup_element:INFO: Eye window for uplink 29: _____________XXXXXX_____________________
Data delay found: 35
11:10:57:setup_element:INFO: Eye window for uplink 30: _______________XXXXXX___________________
Data delay found: 37
11:10:57:setup_element:INFO: Eye window for uplink 31: ______________XXXX______________________
Data delay found: 35
11:10:57:setup_element:INFO: Setting the data phase to 19 for uplink 16
11:10:57:setup_element:INFO: Setting the data phase to 15 for uplink 17
11:10:57:setup_element:INFO: Setting the data phase to 18 for uplink 18
11:10:57:setup_element:INFO: Setting the data phase to 15 for uplink 19
11:10:57:setup_element:INFO: Setting the data phase to 19 for uplink 20
11:10:57:setup_element:INFO: Setting the data phase to 18 for uplink 21
11:10:57:setup_element:INFO: Setting the data phase to 18 for uplink 22
11:10:57:setup_element:INFO: Setting the data phase to 15 for uplink 23
11:10:57:setup_element:INFO: Setting the data phase to 28 for uplink 24
11:10:57:setup_element:INFO: Setting the data phase to 30 for uplink 25
11:10:57:setup_element:INFO: Setting the data phase to 29 for uplink 26
11:10:57:setup_element:INFO: Setting the data phase to 32 for uplink 27
11:10:57:setup_element:INFO: Setting the data phase to 34 for uplink 28
11:10:58:setup_element:INFO: Setting the data phase to 35 for uplink 29
11:10:58:setup_element:INFO: Setting the data phase to 37 for uplink 30
11:10:58:setup_element:INFO: Setting the data phase to 35 for uplink 31
11:10:58:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 35
Window Length: 70
Eye Windows:
Uplink 16: _______________________________________________________________________XXXXXXXXX
Uplink 17: _______________________________________________________________________XXXXXXXXX
Uplink 18: ________________________________________________________________________XXXXXXXX
Uplink 19: ________________________________________________________________________XXXXXXXX
Uplink 20: X_______________________________________________________________________XXXXXXXX
Uplink 21: X_______________________________________________________________________XXXXXXXX
Uplink 22: X_______________________________________________________________________XXXXXXXX
Uplink 23: X_______________________________________________________________________XXXXXXXX
Uplink 24: _______________________________________________________________________XXXXXXXXX
Uplink 25: _______________________________________________________________________XXXXXXXXX
Uplink 26: ________________________________________________________________________XXXXXXXX
Uplink 27: ________________________________________________________________________XXXXXXXX
Uplink 28: ________________________________________________________________________XXXXXXXX
Uplink 29: ________________________________________________________________________XXXXXXXX
Uplink 30: _________________________________________________________________________XXXXXXX
Uplink 31: _________________________________________________________________________XXXXXXX
Data phase characteristics:
Uplink 16:
Optimal Phase: 19
Window Length: 35
Eye Window: XX___________________________________XXX
Uplink 17:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
Uplink 18:
Optimal Phase: 18
Window Length: 34
Eye Window: XX__________________________________XXXX
Uplink 19:
Optimal Phase: 15
Window Length: 34
Eye Window: _________________________________XXXXXX_
Uplink 20:
Optimal Phase: 19
Window Length: 35
Eye Window: XX___________________________________XXX
Uplink 21:
Optimal Phase: 18
Window Length: 35
Eye Window: X___________________________________XXXX
Uplink 22:
Optimal Phase: 18
Window Length: 34
Eye Window: XX__________________________________XXXX
Uplink 23:
Optimal Phase: 15
Window Length: 34
Eye Window: _________________________________XXXXXX_
Uplink 24:
Optimal Phase: 28
Window Length: 35
Eye Window: ______XXXXX_____________________________
Uplink 25:
Optimal Phase: 30
Window Length: 34
Eye Window: ________XXXXXX__________________________
Uplink 26:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 27:
Optimal Phase: 32
Window Length: 34
Eye Window: __________XXXXXX________________________
Uplink 28:
Optimal Phase: 34
Window Length: 35
Eye Window: ____________XXXXX_______________________
Uplink 29:
Optimal Phase: 35
Window Length: 34
Eye Window: _____________XXXXXX_____________________
Uplink 30:
Optimal Phase: 37
Window Length: 34
Eye Window: _______________XXXXXX___________________
Uplink 31:
Optimal Phase: 35
Window Length: 36
Eye Window: ______________XXXX______________________
]
11:10:58:setup_element:INFO: Beginning SMX ASICs map scan
11:10:58:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
11:10:58:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
11:10:58:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
11:10:58:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
11:10:58:uplink:INFO: Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
11:10:58:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 23
11:10:58:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 22
11:10:58:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 30
11:10:58:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 31
11:10:58:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 21
11:10:58:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 20
11:10:58:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28
11:10:58:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 29
11:10:58:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 19
11:10:58:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 18
11:10:59:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26
11:10:59:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 27
11:10:59:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 17
11:10:59:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 16
11:10:59:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 24
11:10:59:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 25
11:11:00:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 23), (1, 22)
ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
ASIC address 0x2: (ASIC uplink, uplink): (0, 21), (1, 20)
ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
ASIC address 0x4: (ASIC uplink, uplink): (0, 19), (1, 18)
ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
ASIC address 0x6: (ASIC uplink, uplink): (0, 17), (1, 16)
ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
Clock Phase Characteristic:
Optimal Phase: 35
Window Length: 70
Eye Windows:
Uplink 16: _______________________________________________________________________XXXXXXXXX
Uplink 17: _______________________________________________________________________XXXXXXXXX
Uplink 18: ________________________________________________________________________XXXXXXXX
Uplink 19: ________________________________________________________________________XXXXXXXX
Uplink 20: X_______________________________________________________________________XXXXXXXX
Uplink 21: X_______________________________________________________________________XXXXXXXX
Uplink 22: X_______________________________________________________________________XXXXXXXX
Uplink 23: X_______________________________________________________________________XXXXXXXX
Uplink 24: _______________________________________________________________________XXXXXXXXX
Uplink 25: _______________________________________________________________________XXXXXXXXX
Uplink 26: ________________________________________________________________________XXXXXXXX
Uplink 27: ________________________________________________________________________XXXXXXXX
Uplink 28: ________________________________________________________________________XXXXXXXX
Uplink 29: ________________________________________________________________________XXXXXXXX
Uplink 30: _________________________________________________________________________XXXXXXX
Uplink 31: _________________________________________________________________________XXXXXXX
Data phase characteristics:
Uplink 16:
Optimal Phase: 19
Window Length: 35
Eye Window: XX___________________________________XXX
Uplink 17:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
Uplink 18:
Optimal Phase: 18
Window Length: 34
Eye Window: XX__________________________________XXXX
Uplink 19:
Optimal Phase: 15
Window Length: 34
Eye Window: _________________________________XXXXXX_
Uplink 20:
Optimal Phase: 19
Window Length: 35
Eye Window: XX___________________________________XXX
Uplink 21:
Optimal Phase: 18
Window Length: 35
Eye Window: X___________________________________XXXX
Uplink 22:
Optimal Phase: 18
Window Length: 34
Eye Window: XX__________________________________XXXX
Uplink 23:
Optimal Phase: 15
Window Length: 34
Eye Window: _________________________________XXXXXX_
Uplink 24:
Optimal Phase: 28
Window Length: 35
Eye Window: ______XXXXX_____________________________
Uplink 25:
Optimal Phase: 30
Window Length: 34
Eye Window: ________XXXXXX__________________________
Uplink 26:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 27:
Optimal Phase: 32
Window Length: 34
Eye Window: __________XXXXXX________________________
Uplink 28:
Optimal Phase: 34
Window Length: 35
Eye Window: ____________XXXXX_______________________
Uplink 29:
Optimal Phase: 35
Window Length: 34
Eye Window: _____________XXXXXX_____________________
Uplink 30:
Optimal Phase: 37
Window Length: 34
Eye Window: _______________XXXXXX___________________
Uplink 31:
Optimal Phase: 35
Window Length: 36
Eye Window: ______________XXXX______________________
11:11:00:setup_element:INFO: Performing Elink synchronization
11:11:00:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
11:11:00:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
11:11:00:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
11:11:00:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
11:11:00:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2
11:11:00:uplink:INFO: Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
11:11:01:ST3_emu:INFO: Number of chips: 8
11:11:01:ST3_emu:INFO: Chip address: 0x0
11:11:01:ST3_emu:INFO: Chip address: 0x1
11:11:01:ST3_emu:INFO: Chip address: 0x2
11:11:01:ST3_emu:INFO: Chip address: 0x3
11:11:01:ST3_emu:INFO: Chip address: 0x4
11:11:01:ST3_emu:INFO: Chip address: 0x5
11:11:01:ST3_emu:INFO: Chip address: 0x6
11:11:01:ST3_emu:INFO: Chip address: 0x7
11:11:02:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
11:11:03:febtest:INFO: 0-0 | XA-000-08-002-001-006-183-00 | 21.9 | 1212.7
11:11:03:febtest:INFO: 0-1 | XA-000-08-002-001-006-191-00 | 25.1 | 1195.1
11:11:03:febtest:INFO: 0-2 | XA-000-08-002-001-006-184-00 | 21.9 | 1206.9
11:11:03:febtest:INFO: 0-3 | XA-000-08-002-001-006-193-12 | 18.7 | 1212.7
11:11:04:febtest:INFO: 0-4 | XA-000-08-002-001-006-187-00 | 31.4 | 1171.5
11:11:04:febtest:INFO: 0-5 | XA-000-08-002-001-006-195-12 | 6.1 | 1259.6
11:11:04:febtest:INFO: 0-6 | XA-000-08-002-001-006-189-00 | 25.1 | 1189.2
11:11:04:febtest:INFO: 0-7 | XA-000-08-002-001-006-196-12 | 21.9 | 1212.7
11:11:04:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
11:11:08:ST3_smx:INFO: chip: 0-0 21.902970 C 1195.082160 mV
11:11:08:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
11:11:08:ST3_smx:INFO: Electrons
11:11:08:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:11:10:ST3_smx:INFO: ----> Checking Analog response
11:11:10:ST3_smx:INFO: ----> Checking broken channels
11:11:11:ST3_smx:INFO: Total # broken ch: 0
11:11:11:ST3_smx:INFO: List FAST: []
11:11:11:ST3_smx:INFO: List SLOW: []
11:11:11:ST3_smx:INFO: Holes
11:11:11:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:11:13:ST3_smx:INFO: ----> Checking Analog response
11:11:13:ST3_smx:INFO: ----> Checking broken channels
11:11:13:ST3_smx:INFO: Total # broken ch: 0
11:11:13:ST3_smx:INFO: List FAST: []
11:11:13:ST3_smx:INFO: List SLOW: []
11:11:13:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
11:11:13:febtest:INFO: 0-0 | XA-000-08-002-001-006-183-00 | 21.9 | 1195.1
11:11:13:febtest:INFO: 0-1 | XA-000-08-002-001-006-191-00 | 21.9 | 1195.1
11:11:13:febtest:INFO: 0-2 | XA-000-08-002-001-006-184-00 | 21.9 | 1206.9
11:11:14:febtest:INFO: 0-3 | XA-000-08-002-001-006-193-12 | 15.6 | 1218.6
11:11:14:febtest:INFO: 0-4 | XA-000-08-002-001-006-187-00 | 31.4 | 1171.5
11:11:14:febtest:INFO: 0-5 | XA-000-08-002-001-006-195-12 | 3.0 | 1259.6
11:11:14:febtest:INFO: 0-6 | XA-000-08-002-001-006-189-00 | 25.1 | 1189.2
11:11:15:febtest:INFO: 0-7 | XA-000-08-002-001-006-196-12 | 18.7 | 1212.7
11:11:16:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
11:11:20:ST3_smx:INFO: chip: 0-1 34.556970 C 1141.874115 mV
11:11:20:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
11:11:20:ST3_smx:INFO: Electrons
11:11:20:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:11:22:ST3_smx:INFO: ----> Checking Analog response
11:11:22:ST3_smx:INFO: ----> Checking broken channels
11:11:22:ST3_smx:INFO: Total # broken ch: 0
11:11:22:ST3_smx:INFO: List FAST: []
11:11:22:ST3_smx:INFO: List SLOW: []
11:11:22:ST3_smx:INFO: Holes
11:11:22:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:11:24:ST3_smx:INFO: ----> Checking Analog response
11:11:24:ST3_smx:INFO: ----> Checking broken channels
11:11:24:ST3_smx:INFO: Total # broken ch: 0
11:11:24:ST3_smx:INFO: List FAST: []
11:11:24:ST3_smx:INFO: List SLOW: []
11:11:24:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
11:11:24:febtest:INFO: 0-0 | XA-000-08-002-001-006-183-00 | 21.9 | 1195.1
11:11:25:febtest:INFO: 0-1 | XA-000-08-002-001-006-191-00 | 37.7 | 1135.9
11:11:25:febtest:INFO: 0-2 | XA-000-08-002-001-006-184-00 | 18.7 | 1212.7
11:11:25:febtest:INFO: 0-3 | XA-000-08-002-001-006-193-12 | 15.6 | 1218.6
11:11:25:febtest:INFO: 0-4 | XA-000-08-002-001-006-187-00 | 28.2 | 1177.4
11:11:26:febtest:INFO: 0-5 | XA-000-08-002-001-006-195-12 | 3.0 | 1259.6
11:11:26:febtest:INFO: 0-6 | XA-000-08-002-001-006-189-00 | 25.1 | 1195.1
11:11:26:febtest:INFO: 0-7 | XA-000-08-002-001-006-196-12 | 18.7 | 1212.7
11:11:27:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
11:11:31:ST3_smx:INFO: chip: 0-2 18.745682 C 1200.969315 mV
11:11:31:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
11:11:31:ST3_smx:INFO: Electrons
11:11:31:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:11:33:ST3_smx:INFO: ----> Checking Analog response
11:11:33:ST3_smx:INFO: ----> Checking broken channels
11:11:33:ST3_smx:INFO: Total # broken ch: 0
11:11:33:ST3_smx:INFO: List FAST: []
11:11:33:ST3_smx:INFO: List SLOW: []
11:11:33:ST3_smx:INFO: Holes
11:11:33:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:11:35:ST3_smx:INFO: ----> Checking Analog response
11:11:35:ST3_smx:INFO: ----> Checking broken channels
11:11:35:ST3_smx:INFO: Total # broken ch: 0
11:11:35:ST3_smx:INFO: List FAST: []
11:11:35:ST3_smx:INFO: List SLOW: []
11:11:35:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
11:11:36:febtest:INFO: 0-0 | XA-000-08-002-001-006-183-00 | 21.9 | 1195.1
11:11:36:febtest:INFO: 0-1 | XA-000-08-002-001-006-191-00 | 40.9 | 1135.9
11:11:36:febtest:INFO: 0-2 | XA-000-08-002-001-006-184-00 | 18.7 | 1201.0
11:11:36:febtest:INFO: 0-3 | XA-000-08-002-001-006-193-12 | 18.7 | 1218.6
11:11:36:febtest:INFO: 0-4 | XA-000-08-002-001-006-187-00 | 31.4 | 1177.4
11:11:37:febtest:INFO: 0-5 | XA-000-08-002-001-006-195-12 | 3.0 | 1259.6
11:11:37:febtest:INFO: 0-6 | XA-000-08-002-001-006-189-00 | 25.1 | 1195.1
11:11:37:febtest:INFO: 0-7 | XA-000-08-002-001-006-196-12 | 18.7 | 1212.7
11:11:38:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
11:11:42:ST3_smx:INFO: chip: 0-3 25.062742 C 1183.292940 mV
11:11:42:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
11:11:42:ST3_smx:INFO: Electrons
11:11:42:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:11:44:ST3_smx:INFO: ----> Checking Analog response
11:11:44:ST3_smx:INFO: ----> Checking broken channels
11:11:44:ST3_smx:INFO: Total # broken ch: 0
11:11:44:ST3_smx:INFO: List FAST: []
11:11:44:ST3_smx:INFO: List SLOW: []
11:11:44:ST3_smx:INFO: Holes
11:11:44:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:11:46:ST3_smx:INFO: ----> Checking Analog response
11:11:46:ST3_smx:INFO: ----> Checking broken channels
11:11:47:ST3_smx:INFO: Total # broken ch: 0
11:11:47:ST3_smx:INFO: List FAST: []
11:11:47:ST3_smx:INFO: List SLOW: []
11:11:47:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
11:11:47:febtest:INFO: 0-0 | XA-000-08-002-001-006-183-00 | 25.1 | 1195.1
11:11:47:febtest:INFO: 0-1 | XA-000-08-002-001-006-191-00 | 40.9 | 1141.9
11:11:47:febtest:INFO: 0-2 | XA-000-08-002-001-006-184-00 | 18.7 | 1201.0
11:11:48:febtest:INFO: 0-3 | XA-000-08-002-001-006-193-12 | 28.2 | 1177.4
11:11:48:febtest:INFO: 0-4 | XA-000-08-002-001-006-187-00 | 28.2 | 1183.3
11:11:48:febtest:INFO: 0-5 | XA-000-08-002-001-006-195-12 | 3.0 | 1265.4
11:11:48:febtest:INFO: 0-6 | XA-000-08-002-001-006-189-00 | 21.9 | 1195.1
11:11:49:febtest:INFO: 0-7 | XA-000-08-002-001-006-196-12 | 18.7 | 1212.7
11:11:50:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
11:11:53:ST3_smx:INFO: chip: 0-4 25.062742 C 1195.082160 mV
11:11:53:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
11:11:53:ST3_smx:INFO: Electrons
11:11:53:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:11:55:ST3_smx:INFO: ----> Checking Analog response
11:11:55:ST3_smx:INFO: ----> Checking broken channels
11:11:56:ST3_smx:INFO: Total # broken ch: 0
11:11:56:ST3_smx:INFO: List FAST: []
11:11:56:ST3_smx:INFO: List SLOW: []
11:11:56:ST3_smx:INFO: Holes
11:11:56:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:11:58:ST3_smx:INFO: ----> Checking Analog response
11:11:58:ST3_smx:INFO: ----> Checking broken channels
11:11:58:ST3_smx:INFO: Total # broken ch: 0
11:11:58:ST3_smx:INFO: List FAST: []
11:11:58:ST3_smx:INFO: List SLOW: []
11:11:58:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
11:11:58:febtest:INFO: 0-0 | XA-000-08-002-001-006-183-00 | 25.1 | 1195.1
11:11:58:febtest:INFO: 0-1 | XA-000-08-002-001-006-191-00 | 40.9 | 1135.9
11:11:59:febtest:INFO: 0-2 | XA-000-08-002-001-006-184-00 | 21.9 | 1201.0
11:11:59:febtest:INFO: 0-3 | XA-000-08-002-001-006-193-12 | 28.2 | 1177.4
11:11:59:febtest:INFO: 0-4 | XA-000-08-002-001-006-187-00 | 25.1 | 1189.2
11:11:59:febtest:INFO: 0-5 | XA-000-08-002-001-006-195-12 | 3.0 | 1259.6
11:11:59:febtest:INFO: 0-6 | XA-000-08-002-001-006-189-00 | 21.9 | 1195.1
11:12:00:febtest:INFO: 0-7 | XA-000-08-002-001-006-196-12 | 18.7 | 1218.6
11:12:01:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
11:12:04:ST3_smx:INFO: chip: 0-5 12.438562 C 1218.600960 mV
11:12:04:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
11:12:04:ST3_smx:INFO: Electrons
11:12:04:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:12:06:ST3_smx:INFO: ----> Checking Analog response
11:12:06:ST3_smx:INFO: ----> Checking broken channels
11:12:07:ST3_smx:INFO: Total # broken ch: 0
11:12:07:ST3_smx:INFO: List FAST: []
11:12:07:ST3_smx:INFO: List SLOW: []
11:12:07:ST3_smx:INFO: Holes
11:12:07:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:12:09:ST3_smx:INFO: ----> Checking Analog response
11:12:09:ST3_smx:INFO: ----> Checking broken channels
11:12:09:ST3_smx:INFO: Total # broken ch: 0
11:12:09:ST3_smx:INFO: List FAST: []
11:12:09:ST3_smx:INFO: List SLOW: []
11:12:09:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
11:12:09:febtest:INFO: 0-0 | XA-000-08-002-001-006-183-00 | 21.9 | 1201.0
11:12:09:febtest:INFO: 0-1 | XA-000-08-002-001-006-191-00 | 40.9 | 1141.9
11:12:10:febtest:INFO: 0-2 | XA-000-08-002-001-006-184-00 | 18.7 | 1206.9
11:12:10:febtest:INFO: 0-3 | XA-000-08-002-001-006-193-12 | 28.2 | 1183.3
11:12:10:febtest:INFO: 0-4 | XA-000-08-002-001-006-187-00 | 25.1 | 1195.1
11:12:10:febtest:INFO: 0-5 | XA-000-08-002-001-006-195-12 | 15.6 | 1212.7
11:12:11:febtest:INFO: 0-6 | XA-000-08-002-001-006-189-00 | 21.9 | 1195.1
11:12:11:febtest:INFO: 0-7 | XA-000-08-002-001-006-196-12 | 18.7 | 1218.6
11:12:12:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
11:12:16:ST3_smx:INFO: chip: 0-6 28.225000 C 1171.483840 mV
11:12:16:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
11:12:16:ST3_smx:INFO: Electrons
11:12:16:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:12:18:ST3_smx:INFO: ----> Checking Analog response
11:12:18:ST3_smx:INFO: ----> Checking broken channels
11:12:18:ST3_smx:INFO: Total # broken ch: 0
11:12:18:ST3_smx:INFO: List FAST: []
11:12:18:ST3_smx:INFO: List SLOW: []
11:12:18:ST3_smx:INFO: Holes
11:12:18:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:12:20:ST3_smx:INFO: ----> Checking Analog response
11:12:20:ST3_smx:INFO: ----> Checking broken channels
11:12:20:ST3_smx:INFO: Total # broken ch: 0
11:12:20:ST3_smx:INFO: List FAST: []
11:12:20:ST3_smx:INFO: List SLOW: []
11:12:20:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
11:12:20:febtest:INFO: 0-0 | XA-000-08-002-001-006-183-00 | 18.7 | 1201.0
11:12:21:febtest:INFO: 0-1 | XA-000-08-002-001-006-191-00 | 34.6 | 1141.9
11:12:21:febtest:INFO: 0-2 | XA-000-08-002-001-006-184-00 | 18.7 | 1206.9
11:12:21:febtest:INFO: 0-3 | XA-000-08-002-001-006-193-12 | 25.1 | 1183.3
11:12:21:febtest:INFO: 0-4 | XA-000-08-002-001-006-187-00 | 25.1 | 1195.1
11:12:22:febtest:INFO: 0-5 | XA-000-08-002-001-006-195-12 | 12.4 | 1218.6
11:12:22:febtest:INFO: 0-6 | XA-000-08-002-001-006-189-00 | 28.2 | 1171.5
11:12:22:febtest:INFO: 0-7 | XA-000-08-002-001-006-196-12 | 18.7 | 1218.6
11:12:23:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
11:12:27:ST3_smx:INFO: chip: 0-7 25.062742 C 1183.292940 mV
11:12:27:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
11:12:27:ST3_smx:INFO: Electrons
11:12:27:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:12:29:ST3_smx:INFO: ----> Checking Analog response
11:12:29:ST3_smx:INFO: ----> Checking broken channels
11:12:29:ST3_smx:INFO: Total # broken ch: 0
11:12:29:ST3_smx:INFO: List FAST: []
11:12:29:ST3_smx:INFO: List SLOW: []
11:12:29:ST3_smx:INFO: Holes
11:12:29:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:12:31:ST3_smx:INFO: ----> Checking Analog response
11:12:31:ST3_smx:INFO: ----> Checking broken channels
11:12:32:ST3_smx:INFO: Total # broken ch: 0
11:12:32:ST3_smx:INFO: List FAST: []
11:12:32:ST3_smx:INFO: List SLOW: []
11:12:32:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
11:12:32:febtest:INFO: 0-0 | XA-000-08-002-001-006-183-00 | 18.7 | 1206.9
11:12:32:febtest:INFO: 0-1 | XA-000-08-002-001-006-191-00 | 34.6 | 1147.8
11:12:32:febtest:INFO: 0-2 | XA-000-08-002-001-006-184-00 | 15.6 | 1212.7
11:12:33:febtest:INFO: 0-3 | XA-000-08-002-001-006-193-12 | 21.9 | 1183.3
11:12:33:febtest:INFO: 0-4 | XA-000-08-002-001-006-187-00 | 21.9 | 1201.0
11:12:33:febtest:INFO: 0-5 | XA-000-08-002-001-006-195-12 | 12.4 | 1218.6
11:12:33:febtest:INFO: 0-6 | XA-000-08-002-001-006-189-00 | 28.2 | 1177.4
11:12:34:febtest:INFO: 0-7 | XA-000-08-002-001-006-196-12 | 28.2 | 1183.3
############################################################
# S U M M A R Y #
############################################################
{'TEST_NAME': 'FEB-ASIC', 'TEST_DATE': '2023_07_11-11_10_47', 'OPERATOR': 'Robert V.; ', 'PROJECT': 'Production', 'SITE': 'GSI', 'SETUP': 'GSI_TEST_SETUP_1', 'ASIC_ID': 'XA-000-08-002-001-006-196-12', 'FUSED_ID': 6359364699117612108, 'HW_ADDR': 7, 'VERS_NO': '2.2', 'CABLE_SET_ID': '', 'IC_TEMP': '0', 'VDDM': '0', 'AUX': '0', 'CSABIAS': '0', 'VDDM_INT': '0', 'ADC_Chi2': 0.0, 'ADC_NDF': 0, 'ADC_P0': 0.0, 'ADC_P1': 0.006824, 'ADC_P2': -2.485e-06, 'ADC_P0err': 0.001, 'ADC_P1err': 0.001, 'ADC_P2err': 1e-05, 'ADC_VREF_P': 58, 'ADC_VREF_N': 30, 'ADC_VREF_T': 128, 'ADC_VREF_TR': 122, 'THR2_GLB': 30, 'LOOP__PLS': 100, 'CALIB_PLS': 250, 'SnsLoop': 5, 'IFED': 31, 'CSA_BIAS': 15, 'CSA_Chi2': 0.0, 'CSA_NDF': 0, 'CSA_P0': 0.0, 'CSA_P1': 0.0, 'CSA_P2': 0.0, 'CSA_P0err': 0.0, 'CSA_P1err': 0.0, 'CSA_P2err': 0.0, 'CONF_FAIL_REG': 0, 'N_BROKEN_DISC': 0, 'N_BROKEN_FAST': '[]', 'N_BROKEN_SLOW': '[]', 'P_BROKEN_DISC': 0, 'P_BROKEN_FAST': '[]', 'P_BROKEN_SLOW': '[]', 'ASIC_QA_category': '', 'N_BROKEN_CABLE': 0, 'LIST_OF_BROKEN_CABLES': 0, 'VI_bInit': ['0.000', '0.0000', '2.499', '1.7080', '2.199', '2.1350', '7.001', '1.5610'], 'VI_aInit': ['0', '0', '0', '0', '0', '0'], 'VI_atEnd': ['0', '0', '0', '0', '0', '0'], 'AMP_CAL': 200, 'PlsLoop': 3, 'N_ANA_PRESENT': 'Analog response OK', 'N_DISC_FAIL_CH': 0, 'N_ANA_FAIL_CH': '0', 'P_ANA_PRESENT': 'Analog response OK', 'P_DISC_FAIL_CH': 0, 'P_ANA_FAIL_CH': '0'}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
11:12:52:ST3_Shared:INFO: /home/cbm/public_html/Test_LogDir//FEB/FEB_2004/B//TestDate_2023_07_11-11_10_47/