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FEB_2005 20.07.23 15:54:40
TextEdit.txt
15:54:33:ST3_hmp4040:INFO: HAMEG,HMP2030,017836163,HW50010002/SW2.30
15:54:33:febtest:INFO: FEB8.2 selected
15:54:33:smx_tester:INFO: Setting Elink clock mode to 160 MHz
15:54:33:febtest:INFO: FEB8.2 selected
15:54:33:smx_tester:INFO: Setting Elink clock mode to 160 MHz
15:54:40:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
15:54:40:ST3_Shared:INFO: --------------------------FEB-ASIC--------------------------
15:54:40:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
15:54:41:febtest:INFO: Tsting FEB with SN 2005
15:54:42:smx_tester:INFO: Scanning setup
15:54:42:elinks:INFO: Disabling clock on downlink 0
15:54:42:elinks:INFO: Disabling clock on downlink 1
15:54:42:elinks:INFO: Disabling clock on downlink 2
15:54:42:elinks:INFO: Disabling clock on downlink 3
15:54:42:elinks:INFO: Disabling clock on downlink 4
15:54:42:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:54:42:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
15:54:42:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:54:42:elinks:INFO: Disabling clock on downlink 0
15:54:42:elinks:INFO: Disabling clock on downlink 1
15:54:42:elinks:INFO: Disabling clock on downlink 2
15:54:42:elinks:INFO: Disabling clock on downlink 3
15:54:42:elinks:INFO: Disabling clock on downlink 4
15:54:42:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:54:42:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
15:54:42:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:54:42:elinks:INFO: Disabling clock on downlink 0
15:54:42:elinks:INFO: Disabling clock on downlink 1
15:54:42:elinks:INFO: Disabling clock on downlink 2
15:54:42:elinks:INFO: Disabling clock on downlink 3
15:54:42:elinks:INFO: Disabling clock on downlink 4
15:54:42:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:54:42:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:54:42:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24
15:54:42:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25
15:54:42:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26
15:54:42:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27
15:54:42:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28
15:54:42:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29
15:54:42:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30
15:54:42:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31
15:54:42:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:54:42:elinks:INFO: Disabling clock on downlink 0
15:54:42:elinks:INFO: Disabling clock on downlink 1
15:54:42:elinks:INFO: Disabling clock on downlink 2
15:54:42:elinks:INFO: Disabling clock on downlink 3
15:54:42:elinks:INFO: Disabling clock on downlink 4
15:54:42:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:54:42:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
15:54:42:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:54:42:elinks:INFO: Disabling clock on downlink 0
15:54:42:elinks:INFO: Disabling clock on downlink 1
15:54:42:elinks:INFO: Disabling clock on downlink 2
15:54:42:elinks:INFO: Disabling clock on downlink 3
15:54:42:elinks:INFO: Disabling clock on downlink 4
15:54:43:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:54:43:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
15:54:43:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:54:43:setup_element:INFO: Scanning clock phase
15:54:43:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:54:43:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
15:54:43:setup_element:INFO: Clock phase scan results for group 0, downlink 2
15:54:43:setup_element:INFO: Eye window for uplink 24: ______________________________________________________________________XXXXXXXXX_
Clock Delay: 34
15:54:43:setup_element:INFO: Eye window for uplink 25: ______________________________________________________________________XXXXXXXXX_
Clock Delay: 34
15:54:43:setup_element:INFO: Eye window for uplink 26: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
15:54:43:setup_element:INFO: Eye window for uplink 27: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
15:54:43:setup_element:INFO: Eye window for uplink 28: ______________________________________________________________________XXXXXXXXX_
Clock Delay: 34
15:54:43:setup_element:INFO: Eye window for uplink 29: ______________________________________________________________________XXXXXXXXX_
Clock Delay: 34
15:54:43:setup_element:INFO: Eye window for uplink 30: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
15:54:43:setup_element:INFO: Eye window for uplink 31: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
15:54:43:setup_element:INFO: Setting the clock phase to 34 for group 0, downlink 2
15:54:43:setup_element:INFO: Scanning data phases
15:54:43:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:54:43:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
15:54:48:setup_element:INFO: Data phase scan results for group 0, downlink 2
15:54:48:setup_element:INFO: Eye window for uplink 24: _______XXXXX____________________________
Data delay found: 29
15:54:48:setup_element:INFO: Eye window for uplink 25: _________XXXXX__________________________
Data delay found: 31
15:54:48:setup_element:INFO: Eye window for uplink 26: _______XXXXX____________________________
Data delay found: 29
15:54:48:setup_element:INFO: Eye window for uplink 27: __________XXXXX_________________________
Data delay found: 32
15:54:48:setup_element:INFO: Eye window for uplink 28: _____________XXXXX______________________
Data delay found: 35
15:54:48:setup_element:INFO: Eye window for uplink 29: _______________XXXXX____________________
Data delay found: 37
15:54:48:setup_element:INFO: Eye window for uplink 30: _______________XXXXX____________________
Data delay found: 37
15:54:48:setup_element:INFO: Eye window for uplink 31: _____________XXXXX______________________
Data delay found: 35
15:54:48:setup_element:INFO: Setting the data phase to 29 for uplink 24
15:54:48:setup_element:INFO: Setting the data phase to 31 for uplink 25
15:54:48:setup_element:INFO: Setting the data phase to 29 for uplink 26
15:54:48:setup_element:INFO: Setting the data phase to 32 for uplink 27
15:54:48:setup_element:INFO: Setting the data phase to 35 for uplink 28
15:54:48:setup_element:INFO: Setting the data phase to 37 for uplink 29
15:54:48:setup_element:INFO: Setting the data phase to 37 for uplink 30
15:54:48:setup_element:INFO: Setting the data phase to 35 for uplink 31
15:54:48:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 2
Uplinks: [24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 34
Window Length: 71
Eye Windows:
Uplink 24: ______________________________________________________________________XXXXXXXXX_
Uplink 25: ______________________________________________________________________XXXXXXXXX_
Uplink 26: ______________________________________________________________________XXXXXXXX__
Uplink 27: ______________________________________________________________________XXXXXXXX__
Uplink 28: ______________________________________________________________________XXXXXXXXX_
Uplink 29: ______________________________________________________________________XXXXXXXXX_
Uplink 30: ______________________________________________________________________XXXXXXXX__
Uplink 31: ______________________________________________________________________XXXXXXXX__
Data phase characteristics:
Uplink 24:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 25:
Optimal Phase: 31
Window Length: 35
Eye Window: _________XXXXX__________________________
Uplink 26:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 27:
Optimal Phase: 32
Window Length: 35
Eye Window: __________XXXXX_________________________
Uplink 28:
Optimal Phase: 35
Window Length: 35
Eye Window: _____________XXXXX______________________
Uplink 29:
Optimal Phase: 37
Window Length: 35
Eye Window: _______________XXXXX____________________
Uplink 30:
Optimal Phase: 37
Window Length: 35
Eye Window: _______________XXXXX____________________
Uplink 31:
Optimal Phase: 35
Window Length: 35
Eye Window: _____________XXXXX______________________
]
15:54:48:setup_element:INFO: Beginning SMX ASICs map scan
15:54:48:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:54:48:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
15:54:48:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
15:54:48:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
15:54:48:uplink:INFO: Setting uplinks mask [24, 25, 26, 27, 28, 29, 30, 31]
15:54:49:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 30
15:54:49:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 31
15:54:49:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28
15:54:49:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 29
15:54:49:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26
15:54:49:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 27
15:54:50:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 24
15:54:50:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 25
15:54:51:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 2
Uplinks: [24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map:
ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
Clock Phase Characteristic:
Optimal Phase: 34
Window Length: 71
Eye Windows:
Uplink 24: ______________________________________________________________________XXXXXXXXX_
Uplink 25: ______________________________________________________________________XXXXXXXXX_
Uplink 26: ______________________________________________________________________XXXXXXXX__
Uplink 27: ______________________________________________________________________XXXXXXXX__
Uplink 28: ______________________________________________________________________XXXXXXXXX_
Uplink 29: ______________________________________________________________________XXXXXXXXX_
Uplink 30: ______________________________________________________________________XXXXXXXX__
Uplink 31: ______________________________________________________________________XXXXXXXX__
Data phase characteristics:
Uplink 24:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 25:
Optimal Phase: 31
Window Length: 35
Eye Window: _________XXXXX__________________________
Uplink 26:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 27:
Optimal Phase: 32
Window Length: 35
Eye Window: __________XXXXX_________________________
Uplink 28:
Optimal Phase: 35
Window Length: 35
Eye Window: _____________XXXXX______________________
Uplink 29:
Optimal Phase: 37
Window Length: 35
Eye Window: _______________XXXXX____________________
Uplink 30:
Optimal Phase: 37
Window Length: 35
Eye Window: _______________XXXXX____________________
Uplink 31:
Optimal Phase: 35
Window Length: 35
Eye Window: _____________XXXXX______________________
15:54:51:setup_element:INFO: Performing Elink synchronization
15:54:51:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:54:51:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
15:54:51:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
15:54:51:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
15:54:51:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2
15:54:51:uplink:INFO: Enabling uplinks [24, 25, 26, 27, 28, 29, 30, 31]
15:54:51:ST3_emu:INFO: Number of chips: 4
15:54:51:ST3_emu:INFO: Chip address: 0x1
15:54:51:ST3_emu:INFO: Chip address: 0x3
15:54:51:ST3_emu:INFO: Chip address: 0x5
15:54:51:ST3_emu:INFO: Chip address: 0x7
15:54:52:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:54:52:febtest:INFO: 0-1 | XA-000-08-002-000-005-178-06 | 18.7 | 1242.0
15:54:53:febtest:INFO: 0-3 | XA-000-08-002-000-005-170-01 | 28.2 | 1218.6
15:54:53:febtest:INFO: 0-5 | XA-000-08-002-000-005-167-01 | 25.1 | 1224.5
15:54:53:febtest:INFO: 0-7 | XA-000-08-002-000-005-175-01 | 40.9 | 1171.5
15:54:53:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:54:57:ST3_smx:INFO: chip: 0-1 25.062742 C 1206.851500 mV
15:54:57:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:54:57:ST3_smx:INFO: Electrons
15:54:57:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:54:59:ST3_smx:INFO: ----> Checking Analog response
15:54:59:ST3_smx:INFO: ----> Checking broken channels
15:54:59:ST3_smx:INFO: Total # broken ch: 3
15:54:59:ST3_smx:INFO: List FAST: [1, 25, 114]
15:54:59:ST3_smx:INFO: List SLOW: []
15:54:59:ST3_smx:INFO: Holes
15:54:59:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:55:01:ST3_smx:INFO: ----> Checking Analog response
15:55:01:ST3_smx:INFO: ----> Checking broken channels
15:55:02:ST3_smx:INFO: Total # broken ch: 3
15:55:02:ST3_smx:INFO: List FAST: [1, 25, 114]
15:55:02:ST3_smx:INFO: List SLOW: []
15:55:02:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:55:02:febtest:INFO: 0-1 | XA-000-08-002-000-005-178-06 | 28.2 | 1206.9
15:55:02:febtest:INFO: 0-3 | XA-000-08-002-000-005-170-01 | 28.2 | 1218.6
15:55:02:febtest:INFO: 0-5 | XA-000-08-002-000-005-167-01 | 28.2 | 1218.6
15:55:03:febtest:INFO: 0-7 | XA-000-08-002-000-005-175-01 | 40.9 | 1165.6
15:55:03:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:55:06:ST3_smx:INFO: chip: 0-3 37.726682 C 1165.571835 mV
15:55:06:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:55:06:ST3_smx:INFO: Electrons
15:55:06:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:55:09:ST3_smx:INFO: ----> Checking Analog response
15:55:09:ST3_smx:INFO: ----> Checking broken channels
15:55:09:ST3_smx:INFO: Total # broken ch: 2
15:55:09:ST3_smx:INFO: List FAST: [46, 88]
15:55:09:ST3_smx:INFO: List SLOW: []
15:55:09:ST3_smx:INFO: Holes
15:55:09:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:55:11:ST3_smx:INFO: ----> Checking Analog response
15:55:11:ST3_smx:INFO: ----> Checking broken channels
15:55:11:ST3_smx:INFO: Total # broken ch: 2
15:55:11:ST3_smx:INFO: List FAST: [46, 88]
15:55:11:ST3_smx:INFO: List SLOW: []
15:55:11:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:55:11:febtest:INFO: 0-1 | XA-000-08-002-000-005-178-06 | 28.2 | 1201.0
15:55:12:febtest:INFO: 0-3 | XA-000-08-002-000-005-170-01 | 40.9 | 1159.7
15:55:12:febtest:INFO: 0-5 | XA-000-08-002-000-005-167-01 | 28.2 | 1218.6
15:55:12:febtest:INFO: 0-7 | XA-000-08-002-000-005-175-01 | 40.9 | 1165.6
15:55:12:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:55:16:ST3_smx:INFO: chip: 0-5 25.062742 C 1218.600960 mV
15:55:16:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:55:16:ST3_smx:INFO: Electrons
15:55:16:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:55:18:ST3_smx:INFO: ----> Checking Analog response
15:55:18:ST3_smx:INFO: ----> Checking broken channels
15:55:18:ST3_smx:INFO: Total # broken ch: 9
15:55:18:ST3_smx:INFO: List FAST: [1, 9, 65, 76, 87, 96, 103, 110]
15:55:18:ST3_smx:INFO: List SLOW: [1]
15:55:18:ST3_smx:INFO: Holes
15:55:18:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:55:20:ST3_smx:INFO: ----> Checking Analog response
15:55:20:ST3_smx:INFO: ----> Checking broken channels
15:55:21:ST3_smx:INFO: Total # broken ch: 9
15:55:21:ST3_smx:INFO: List FAST: [1, 9, 65, 76, 87, 96, 103, 110]
15:55:21:ST3_smx:INFO: List SLOW: [1]
15:55:21:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:55:21:febtest:INFO: 0-1 | XA-000-08-002-000-005-178-06 | 28.2 | 1201.0
15:55:21:febtest:INFO: 0-3 | XA-000-08-002-000-005-170-01 | 40.9 | 1159.7
15:55:21:febtest:INFO: 0-5 | XA-000-08-002-000-005-167-01 | 28.2 | 1212.7
15:55:21:febtest:INFO: 0-7 | XA-000-08-002-000-005-175-01 | 40.9 | 1165.6
15:55:22:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:55:25:ST3_smx:INFO: chip: 0-7 37.726682 C 1171.483840 mV
15:55:25:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:55:25:ST3_smx:INFO: Electrons
15:55:25:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:55:27:ST3_smx:INFO: ----> Checking Analog response
15:55:27:ST3_smx:INFO: ----> Checking broken channels
15:55:28:ST3_smx:INFO: Total # broken ch: 6
15:55:28:ST3_smx:INFO: List FAST: [2, 12, 34, 109, 114, 123]
15:55:28:ST3_smx:INFO: List SLOW: []
15:55:28:ST3_smx:INFO: Holes
15:55:28:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:55:29:ST3_smx:INFO: ----> Checking Analog response
15:55:29:ST3_smx:INFO: ----> Checking broken channels
15:55:30:ST3_smx:INFO: Total # broken ch: 6
15:55:30:ST3_smx:INFO: List FAST: [2, 12, 34, 109, 114, 123]
15:55:30:ST3_smx:INFO: List SLOW: []
15:55:30:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:55:30:febtest:INFO: 0-1 | XA-000-08-002-000-005-178-06 | 31.4 | 1195.1
15:55:30:febtest:INFO: 0-3 | XA-000-08-002-000-005-170-01 | 40.9 | 1159.7
15:55:31:febtest:INFO: 0-5 | XA-000-08-002-000-005-167-01 | 28.2 | 1212.7
15:55:31:febtest:INFO: 0-7 | XA-000-08-002-000-005-175-01 | 37.7 | 1171.5
############################################################
# S U M M A R Y #
############################################################
{'TEST_NAME': 'FEB-ASIC', 'TEST_DATE': '2023_07_20-15_54_40', 'OPERATOR': 'Alois Alzheimer', 'PROJECT': 'Production', 'SITE': 'GSI', 'SETUP': 'GSI_TEST_SETUP_1', 'ASIC_ID': 'XA-000-08-002-000-005-175-01', 'FUSED_ID': 6359364699116559089, 'HW_ADDR': 7, 'VERS_NO': '2.2', 'CABLE_SET_ID': '', 'IC_TEMP': '0', 'VDDM': '0', 'AUX': '0', 'CSABIAS': '0', 'VDDM_INT': '0', 'ADC_Chi2': 0.0, 'ADC_NDF': 0, 'ADC_P0': 0.0, 'ADC_P1': 0.006824, 'ADC_P2': -2.485e-06, 'ADC_P0err': 0.001, 'ADC_P1err': 0.001, 'ADC_P2err': 1e-05, 'ADC_VREF_P': 58, 'ADC_VREF_N': 30, 'ADC_VREF_T': 128, 'ADC_VREF_TR': 122, 'THR2_GLB': 30, 'LOOP__PLS': 100, 'CALIB_PLS': 250, 'SnsLoop': 5, 'IFED': 31, 'CSA_BIAS': 15, 'CSA_Chi2': 0.0, 'CSA_NDF': 0, 'CSA_P0': 0.0, 'CSA_P1': 0.0, 'CSA_P2': 0.0, 'CSA_P0err': 0.0, 'CSA_P1err': 0.0, 'CSA_P2err': 0.0, 'CONF_FAIL_REG': 0, 'N_BROKEN_DISC': 6, 'N_BROKEN_FAST': '[2, 12, 34, 109, 114, 123]', 'N_BROKEN_SLOW': '[]', 'P_BROKEN_DISC': 6, 'P_BROKEN_FAST': '[2, 12, 34, 109, 114, 123]', 'P_BROKEN_SLOW': '[]', 'ASIC_QA_category': '', 'N_BROKEN_CABLE': 0, 'LIST_OF_BROKEN_CABLES': 0, 'VI_bInit': ['2.448', '0.7597', '1.848', '0.8355', '7.001', '1.5210', '7.001', '1.5210'], 'VI_aInit': ['0', '0', '0', '0', '0', '0'], 'VI_atEnd': ['0', '0', '0', '0', '0', '0'], 'AMP_CAL': 200, 'PlsLoop': 3, 'N_ANA_PRESENT': 'Analog response OK', 'N_DISC_FAIL_CH': 0, 'N_ANA_FAIL_CH': '0', 'P_ANA_PRESENT': 'Analog response OK', 'P_DISC_FAIL_CH': '58 FAST ', 'P_ANA_FAIL_CH': '1'}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
15:56:03:ST3_Shared:INFO: /home/cbm/public_html/Production_LogDir//FEB/FEB_2005/B//TestDate_2023_07_20-15_54_40/