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FEB_2005 21.07.23 10:48:10
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10:47:43:ST3_hmp4040:INFO:
10:47:44:febtest:INFO: FEB8.2 selected
10:47:44:febtest:INFO: FEB8.2 selected
10:47:59:smx_tester:INFO: Setting Elink clock mode to 160 MHz
10:47:59:ST3_emu:ERROR: device described in file: ../ST3_BASE/config/feb8_2_devices.xml not found!!!
10:48:02:smx_tester:INFO: Setting Elink clock mode to 160 MHz
10:48:05:ST3_Shared:INFO: Listo of operators:Oleksandr S.;
10:48:05:ST3_Shared:INFO: Listo of operators:Oleksandr S.; Robert V.;
10:48:10:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
10:48:10:ST3_Shared:INFO: --------------------------FEB-ASIC--------------------------
10:48:10:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
10:48:10:febtest:INFO: Tsting FEB with SN 2005
10:48:11:smx_tester:INFO: Scanning setup
10:48:11:elinks:INFO: Disabling clock on downlink 0
10:48:11:elinks:INFO: Disabling clock on downlink 1
10:48:11:elinks:INFO: Disabling clock on downlink 2
10:48:11:elinks:INFO: Disabling clock on downlink 3
10:48:11:elinks:INFO: Disabling clock on downlink 4
10:48:11:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:48:11:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
10:48:12:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:48:12:elinks:INFO: Disabling clock on downlink 0
10:48:12:elinks:INFO: Disabling clock on downlink 1
10:48:12:elinks:INFO: Disabling clock on downlink 2
10:48:12:elinks:INFO: Disabling clock on downlink 3
10:48:12:elinks:INFO: Disabling clock on downlink 4
10:48:12:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:48:12:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
10:48:12:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:48:12:elinks:INFO: Disabling clock on downlink 0
10:48:12:elinks:INFO: Disabling clock on downlink 1
10:48:12:elinks:INFO: Disabling clock on downlink 2
10:48:12:elinks:INFO: Disabling clock on downlink 3
10:48:12:elinks:INFO: Disabling clock on downlink 4
10:48:12:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:48:12:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
10:48:12:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 16
10:48:12:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 17
10:48:12:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 18
10:48:12:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 19
10:48:12:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 20
10:48:12:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 21
10:48:12:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 22
10:48:12:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 23
10:48:12:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24
10:48:12:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25
10:48:12:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26
10:48:12:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27
10:48:12:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28
10:48:12:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29
10:48:12:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30
10:48:12:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31
10:48:12:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:48:12:elinks:INFO: Disabling clock on downlink 0
10:48:12:elinks:INFO: Disabling clock on downlink 1
10:48:12:elinks:INFO: Disabling clock on downlink 2
10:48:12:elinks:INFO: Disabling clock on downlink 3
10:48:12:elinks:INFO: Disabling clock on downlink 4
10:48:12:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:48:12:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
10:48:12:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:48:12:elinks:INFO: Disabling clock on downlink 0
10:48:12:elinks:INFO: Disabling clock on downlink 1
10:48:12:elinks:INFO: Disabling clock on downlink 2
10:48:12:elinks:INFO: Disabling clock on downlink 3
10:48:12:elinks:INFO: Disabling clock on downlink 4
10:48:12:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:48:12:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
10:48:12:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:48:12:setup_element:INFO: Scanning clock phase
10:48:12:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
10:48:12:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
10:48:13:setup_element:INFO: Clock phase scan results for group 0, downlink 2
10:48:13:setup_element:INFO: Eye window for uplink 16: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
10:48:13:setup_element:INFO: Eye window for uplink 17: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
10:48:13:setup_element:INFO: Eye window for uplink 18: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
10:48:13:setup_element:INFO: Eye window for uplink 19: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
10:48:13:setup_element:INFO: Eye window for uplink 20: _____________________________________________________________________XXXXXXXXX__
Clock Delay: 33
10:48:13:setup_element:INFO: Eye window for uplink 21: _____________________________________________________________________XXXXXXXXX__
Clock Delay: 33
10:48:13:setup_element:INFO: Eye window for uplink 22: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
10:48:13:setup_element:INFO: Eye window for uplink 23: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
10:48:13:setup_element:INFO: Eye window for uplink 24: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
10:48:13:setup_element:INFO: Eye window for uplink 25: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
10:48:13:setup_element:INFO: Eye window for uplink 26: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
10:48:13:setup_element:INFO: Eye window for uplink 27: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
10:48:13:setup_element:INFO: Eye window for uplink 28: ________________________________________________________________________XXXXXXXX
Clock Delay: 35
10:48:13:setup_element:INFO: Eye window for uplink 29: ________________________________________________________________________XXXXXXXX
Clock Delay: 35
10:48:13:setup_element:INFO: Eye window for uplink 30: _________________________________________________________________________XXXXXXX
Clock Delay: 36
10:48:13:setup_element:INFO: Eye window for uplink 31: _________________________________________________________________________XXXXXXX
Clock Delay: 36
10:48:13:setup_element:INFO: Setting the clock phase to 34 for group 0, downlink 2
10:48:13:setup_element:INFO: Scanning data phases
10:48:13:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
10:48:13:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
10:48:18:setup_element:INFO: Data phase scan results for group 0, downlink 2
10:48:18:setup_element:INFO: Eye window for uplink 16: X___________________________________XXXX
Data delay found: 18
10:48:18:setup_element:INFO: Eye window for uplink 17: ________________________________XXXXX___
Data delay found: 14
10:48:18:setup_element:INFO: Eye window for uplink 18: __________________________________XXXXX_
Data delay found: 16
10:48:18:setup_element:INFO: Eye window for uplink 19: _______________________________XXXXX____
Data delay found: 13
10:48:18:setup_element:INFO: Eye window for uplink 20: ___________________________________XXXX_
Data delay found: 16
10:48:18:setup_element:INFO: Eye window for uplink 21: __________________________________XXXXX_
Data delay found: 16
10:48:18:setup_element:INFO: Eye window for uplink 22: __________________________________XXXX__
Data delay found: 15
10:48:18:setup_element:INFO: Eye window for uplink 23: ________________________________XXXXX___
Data delay found: 14
10:48:18:setup_element:INFO: Eye window for uplink 24: ______XXXXX_____________________________
Data delay found: 28
10:48:18:setup_element:INFO: Eye window for uplink 25: _________XXXXX__________________________
Data delay found: 31
10:48:18:setup_element:INFO: Eye window for uplink 26: _____XXXXXX_____________________________
Data delay found: 27
10:48:18:setup_element:INFO: Eye window for uplink 27: _________XXXXX__________________________
Data delay found: 31
10:48:18:setup_element:INFO: Eye window for uplink 28: ______________XXXXX_____________________
Data delay found: 36
10:48:18:setup_element:INFO: Eye window for uplink 29: _______________XXXXXX___________________
Data delay found: 37
10:48:18:setup_element:INFO: Eye window for uplink 30: ________________XXXXXXX_________________
Data delay found: 39
10:48:18:setup_element:INFO: Eye window for uplink 31: _______________XXXX_XX__________________
Data delay found: 38
10:48:18:setup_element:INFO: Setting the data phase to 18 for uplink 16
10:48:18:setup_element:INFO: Setting the data phase to 14 for uplink 17
10:48:18:setup_element:INFO: Setting the data phase to 16 for uplink 18
10:48:18:setup_element:INFO: Setting the data phase to 13 for uplink 19
10:48:18:setup_element:INFO: Setting the data phase to 16 for uplink 20
10:48:18:setup_element:INFO: Setting the data phase to 16 for uplink 21
10:48:18:setup_element:INFO: Setting the data phase to 15 for uplink 22
10:48:18:setup_element:INFO: Setting the data phase to 14 for uplink 23
10:48:18:setup_element:INFO: Setting the data phase to 28 for uplink 24
10:48:18:setup_element:INFO: Setting the data phase to 31 for uplink 25
10:48:18:setup_element:INFO: Setting the data phase to 27 for uplink 26
10:48:18:setup_element:INFO: Setting the data phase to 31 for uplink 27
10:48:18:setup_element:INFO: Setting the data phase to 36 for uplink 28
10:48:18:setup_element:INFO: Setting the data phase to 37 for uplink 29
10:48:18:setup_element:INFO: Setting the data phase to 39 for uplink 30
10:48:18:setup_element:INFO: Setting the data phase to 38 for uplink 31
10:48:18:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 34
Window Length: 69
Eye Windows:
Uplink 16: _______________________________________________________________________XXXXXXXX_
Uplink 17: _______________________________________________________________________XXXXXXXX_
Uplink 18: ______________________________________________________________________XXXXXXXX__
Uplink 19: ______________________________________________________________________XXXXXXXX__
Uplink 20: _____________________________________________________________________XXXXXXXXX__
Uplink 21: _____________________________________________________________________XXXXXXXXX__
Uplink 22: ______________________________________________________________________XXXXXXXX__
Uplink 23: ______________________________________________________________________XXXXXXXX__
Uplink 24: _______________________________________________________________________XXXXXXXX_
Uplink 25: _______________________________________________________________________XXXXXXXX_
Uplink 26: _______________________________________________________________________XXXXXXXX_
Uplink 27: _______________________________________________________________________XXXXXXXX_
Uplink 28: ________________________________________________________________________XXXXXXXX
Uplink 29: ________________________________________________________________________XXXXXXXX
Uplink 30: _________________________________________________________________________XXXXXXX
Uplink 31: _________________________________________________________________________XXXXXXX
Data phase characteristics:
Uplink 16:
Optimal Phase: 18
Window Length: 35
Eye Window: X___________________________________XXXX
Uplink 17:
Optimal Phase: 14
Window Length: 35
Eye Window: ________________________________XXXXX___
Uplink 18:
Optimal Phase: 16
Window Length: 35
Eye Window: __________________________________XXXXX_
Uplink 19:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 20:
Optimal Phase: 16
Window Length: 36
Eye Window: ___________________________________XXXX_
Uplink 21:
Optimal Phase: 16
Window Length: 35
Eye Window: __________________________________XXXXX_
Uplink 22:
Optimal Phase: 15
Window Length: 36
Eye Window: __________________________________XXXX__
Uplink 23:
Optimal Phase: 14
Window Length: 35
Eye Window: ________________________________XXXXX___
Uplink 24:
Optimal Phase: 28
Window Length: 35
Eye Window: ______XXXXX_____________________________
Uplink 25:
Optimal Phase: 31
Window Length: 35
Eye Window: _________XXXXX__________________________
Uplink 26:
Optimal Phase: 27
Window Length: 34
Eye Window: _____XXXXXX_____________________________
Uplink 27:
Optimal Phase: 31
Window Length: 35
Eye Window: _________XXXXX__________________________
Uplink 28:
Optimal Phase: 36
Window Length: 35
Eye Window: ______________XXXXX_____________________
Uplink 29:
Optimal Phase: 37
Window Length: 34
Eye Window: _______________XXXXXX___________________
Uplink 30:
Optimal Phase: 39
Window Length: 33
Eye Window: ________________XXXXXXX_________________
Uplink 31:
Optimal Phase: 38
Window Length: 33
Eye Window: _______________XXXX_XX__________________
]
10:48:18:setup_element:INFO: Beginning SMX ASICs map scan
10:48:18:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
10:48:18:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
10:48:18:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
10:48:18:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
10:48:18:uplink:INFO: Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
10:48:18:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 23
10:48:18:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 22
10:48:19:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 30
10:48:19:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 31
10:48:19:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 21
10:48:19:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 20
10:48:19:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28
10:48:19:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 29
10:48:19:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 19
10:48:19:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 18
10:48:19:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26
10:48:19:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 27
10:48:19:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 17
10:48:19:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 16
10:48:20:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 24
10:48:20:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 25
10:48:21:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 23), (1, 22)
ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
ASIC address 0x2: (ASIC uplink, uplink): (0, 21), (1, 20)
ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
ASIC address 0x4: (ASIC uplink, uplink): (0, 19), (1, 18)
ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
ASIC address 0x6: (ASIC uplink, uplink): (0, 17), (1, 16)
ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
Clock Phase Characteristic:
Optimal Phase: 34
Window Length: 69
Eye Windows:
Uplink 16: _______________________________________________________________________XXXXXXXX_
Uplink 17: _______________________________________________________________________XXXXXXXX_
Uplink 18: ______________________________________________________________________XXXXXXXX__
Uplink 19: ______________________________________________________________________XXXXXXXX__
Uplink 20: _____________________________________________________________________XXXXXXXXX__
Uplink 21: _____________________________________________________________________XXXXXXXXX__
Uplink 22: ______________________________________________________________________XXXXXXXX__
Uplink 23: ______________________________________________________________________XXXXXXXX__
Uplink 24: _______________________________________________________________________XXXXXXXX_
Uplink 25: _______________________________________________________________________XXXXXXXX_
Uplink 26: _______________________________________________________________________XXXXXXXX_
Uplink 27: _______________________________________________________________________XXXXXXXX_
Uplink 28: ________________________________________________________________________XXXXXXXX
Uplink 29: ________________________________________________________________________XXXXXXXX
Uplink 30: _________________________________________________________________________XXXXXXX
Uplink 31: _________________________________________________________________________XXXXXXX
Data phase characteristics:
Uplink 16:
Optimal Phase: 18
Window Length: 35
Eye Window: X___________________________________XXXX
Uplink 17:
Optimal Phase: 14
Window Length: 35
Eye Window: ________________________________XXXXX___
Uplink 18:
Optimal Phase: 16
Window Length: 35
Eye Window: __________________________________XXXXX_
Uplink 19:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 20:
Optimal Phase: 16
Window Length: 36
Eye Window: ___________________________________XXXX_
Uplink 21:
Optimal Phase: 16
Window Length: 35
Eye Window: __________________________________XXXXX_
Uplink 22:
Optimal Phase: 15
Window Length: 36
Eye Window: __________________________________XXXX__
Uplink 23:
Optimal Phase: 14
Window Length: 35
Eye Window: ________________________________XXXXX___
Uplink 24:
Optimal Phase: 28
Window Length: 35
Eye Window: ______XXXXX_____________________________
Uplink 25:
Optimal Phase: 31
Window Length: 35
Eye Window: _________XXXXX__________________________
Uplink 26:
Optimal Phase: 27
Window Length: 34
Eye Window: _____XXXXXX_____________________________
Uplink 27:
Optimal Phase: 31
Window Length: 35
Eye Window: _________XXXXX__________________________
Uplink 28:
Optimal Phase: 36
Window Length: 35
Eye Window: ______________XXXXX_____________________
Uplink 29:
Optimal Phase: 37
Window Length: 34
Eye Window: _______________XXXXXX___________________
Uplink 30:
Optimal Phase: 39
Window Length: 33
Eye Window: ________________XXXXXXX_________________
Uplink 31:
Optimal Phase: 38
Window Length: 33
Eye Window: _______________XXXX_XX__________________
10:48:21:setup_element:INFO: Performing Elink synchronization
10:48:21:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
10:48:21:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
10:48:21:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
10:48:21:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
10:48:21:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2
10:48:21:uplink:INFO: Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
10:48:21:ST3_emu:INFO: Number of chips: 8
10:48:21:ST3_emu:INFO: Chip address: 0x0
10:48:21:ST3_emu:INFO: Chip address: 0x1
10:48:21:ST3_emu:INFO: Chip address: 0x2
10:48:21:ST3_emu:INFO: Chip address: 0x3
10:48:21:ST3_emu:INFO: Chip address: 0x4
10:48:21:ST3_emu:INFO: Chip address: 0x5
10:48:21:ST3_emu:INFO: Chip address: 0x6
10:48:21:ST3_emu:INFO: Chip address: 0x7
10:48:22:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:48:22:febtest:INFO: 0-0 | XA-000-08-002-000-007-130-12 | 25.1 | 1230.3
10:48:23:febtest:INFO: 0-1 | XA-000-08-002-000-005-178-06 | 21.9 | 1242.0
10:48:23:febtest:INFO: 0-2 | XA-000-08-002-000-007-137-12 | 40.9 | 1177.4
10:48:23:febtest:INFO: 0-3 | XA-000-08-002-000-005-170-01 | 25.1 | 1224.5
10:48:23:febtest:INFO: 0-4 | XA-000-08-002-000-007-148-11 | 53.6 | 1130.0
10:48:23:febtest:INFO: 0-5 | XA-000-08-002-000-005-167-01 | 28.2 | 1236.2
10:48:24:febtest:INFO: 0-6 | XA-000-08-002-000-007-147-11 | 37.7 | 1195.1
10:48:24:febtest:INFO: 0-7 | XA-000-08-002-000-005-175-01 | 44.1 | 1171.5
10:48:24:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
10:48:28:ST3_smx:INFO: chip: 0-0 31.389742 C 1195.082160 mV
10:48:28:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
10:48:28:ST3_smx:INFO: Electrons
10:48:28:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
10:48:30:ST3_smx:INFO: ----> Checking Analog response
10:48:30:ST3_smx:INFO: ----> Checking broken channels
10:48:30:ST3_smx:INFO: Total # broken ch: 1
10:48:30:ST3_smx:INFO: List FAST: [74]
10:48:30:ST3_smx:INFO: List SLOW: []
10:48:30:ST3_smx:INFO: Holes
10:48:30:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
10:48:32:ST3_smx:INFO: ----> Checking Analog response
10:48:32:ST3_smx:INFO: ----> Checking broken channels
10:48:33:ST3_smx:INFO: Total # broken ch: 1
10:48:33:ST3_smx:INFO: List FAST: [74]
10:48:33:ST3_smx:INFO: List SLOW: []
10:48:33:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:48:33:febtest:INFO: 0-0 | XA-000-08-002-000-007-130-12 | 34.6 | 1189.2
10:48:33:febtest:INFO: 0-1 | XA-000-08-002-000-005-178-06 | 21.9 | 1236.2
10:48:33:febtest:INFO: 0-2 | XA-000-08-002-000-007-137-12 | 40.9 | 1177.4
10:48:34:febtest:INFO: 0-3 | XA-000-08-002-000-005-170-01 | 25.1 | 1224.5
10:48:34:febtest:INFO: 0-4 | XA-000-08-002-000-007-148-11 | 53.6 | 1130.0
10:48:34:febtest:INFO: 0-5 | XA-000-08-002-000-005-167-01 | 25.1 | 1236.2
10:48:34:febtest:INFO: 0-6 | XA-000-08-002-000-007-147-11 | 37.7 | 1195.1
10:48:34:febtest:INFO: 0-7 | XA-000-08-002-000-005-175-01 | 44.1 | 1171.5
10:48:35:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
10:48:39:ST3_smx:INFO: chip: 0-1 28.225000 C 1200.969315 mV
10:48:39:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
10:48:39:ST3_smx:INFO: Electrons
10:48:39:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
10:48:41:ST3_smx:INFO: ----> Checking Analog response
10:48:41:ST3_smx:INFO: ----> Checking broken channels
10:48:41:ST3_smx:INFO: Total # broken ch: 1
10:48:41:ST3_smx:INFO: List FAST: [18]
10:48:41:ST3_smx:INFO: List SLOW: []
10:48:41:ST3_smx:INFO: Holes
10:48:41:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
10:48:43:ST3_smx:INFO: ----> Checking Analog response
10:48:43:ST3_smx:INFO: ----> Checking broken channels
10:48:43:ST3_smx:INFO: Total # broken ch: 1
10:48:43:ST3_smx:INFO: List FAST: [18]
10:48:43:ST3_smx:INFO: List SLOW: []
10:48:43:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:48:44:febtest:INFO: 0-0 | XA-000-08-002-000-007-130-12 | 34.6 | 1189.2
10:48:44:febtest:INFO: 0-1 | XA-000-08-002-000-005-178-06 | 31.4 | 1195.1
10:48:44:febtest:INFO: 0-2 | XA-000-08-002-000-007-137-12 | 40.9 | 1177.4
10:48:44:febtest:INFO: 0-3 | XA-000-08-002-000-005-170-01 | 28.2 | 1224.5
10:48:44:febtest:INFO: 0-4 | XA-000-08-002-000-007-148-11 | 53.6 | 1130.0
10:48:45:febtest:INFO: 0-5 | XA-000-08-002-000-005-167-01 | 25.1 | 1230.3
10:48:45:febtest:INFO: 0-6 | XA-000-08-002-000-007-147-11 | 37.7 | 1195.1
10:48:45:febtest:INFO: 0-7 | XA-000-08-002-000-005-175-01 | 44.1 | 1171.5
10:48:45:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
10:48:49:ST3_smx:INFO: chip: 0-2 40.898880 C 1159.654860 mV
10:48:49:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
10:48:49:ST3_smx:INFO: Electrons
10:48:49:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
10:48:51:ST3_smx:INFO: ----> Checking Analog response
10:48:51:ST3_smx:INFO: ----> Checking broken channels
10:48:51:ST3_smx:INFO: Total # broken ch: 0
10:48:51:ST3_smx:INFO: List FAST: []
10:48:51:ST3_smx:INFO: List SLOW: []
10:48:51:ST3_smx:INFO: Holes
10:48:51:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
10:48:54:ST3_smx:INFO: ----> Checking Analog response
10:48:54:ST3_smx:INFO: ----> Checking broken channels
10:48:54:ST3_smx:INFO: Total # broken ch: 0
10:48:54:ST3_smx:INFO: List FAST: []
10:48:54:ST3_smx:INFO: List SLOW: []
10:48:54:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:48:54:febtest:INFO: 0-0 | XA-000-08-002-000-007-130-12 | 34.6 | 1189.2
10:48:54:febtest:INFO: 0-1 | XA-000-08-002-000-005-178-06 | 31.4 | 1195.1
10:48:55:febtest:INFO: 0-2 | XA-000-08-002-000-007-137-12 | 44.1 | 1153.7
10:48:55:febtest:INFO: 0-3 | XA-000-08-002-000-005-170-01 | 28.2 | 1224.5
10:48:55:febtest:INFO: 0-4 | XA-000-08-002-000-007-148-11 | 53.6 | 1124.0
10:48:55:febtest:INFO: 0-5 | XA-000-08-002-000-005-167-01 | 28.2 | 1230.3
10:48:55:febtest:INFO: 0-6 | XA-000-08-002-000-007-147-11 | 37.7 | 1189.2
10:48:56:febtest:INFO: 0-7 | XA-000-08-002-000-005-175-01 | 44.1 | 1171.5
10:48:56:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
10:49:00:ST3_smx:INFO: chip: 0-3 37.726682 C 1177.390875 mV
10:49:00:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
10:49:00:ST3_smx:INFO: Electrons
10:49:00:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
10:49:02:ST3_smx:INFO: ----> Checking Analog response
10:49:02:ST3_smx:INFO: ----> Checking broken channels
10:49:02:ST3_smx:INFO: Total # broken ch: 2
10:49:02:ST3_smx:INFO: List FAST: [1]
10:49:02:ST3_smx:INFO: List SLOW: [1]
10:49:02:ST3_smx:INFO: Holes
10:49:02:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
10:49:04:ST3_smx:INFO: ----> Checking Analog response
10:49:04:ST3_smx:INFO: ----> Checking broken channels
10:49:04:ST3_smx:INFO: Total # broken ch: 2
10:49:04:ST3_smx:INFO: List FAST: [1]
10:49:04:ST3_smx:INFO: List SLOW: [1]
10:49:04:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:49:04:febtest:INFO: 0-0 | XA-000-08-002-000-007-130-12 | 34.6 | 1189.2
10:49:05:febtest:INFO: 0-1 | XA-000-08-002-000-005-178-06 | 31.4 | 1195.1
10:49:05:febtest:INFO: 0-2 | XA-000-08-002-000-007-137-12 | 44.1 | 1153.7
10:49:05:febtest:INFO: 0-3 | XA-000-08-002-000-005-170-01 | 40.9 | 1171.5
10:49:05:febtest:INFO: 0-4 | XA-000-08-002-000-007-148-11 | 53.6 | 1124.0
10:49:06:febtest:INFO: 0-5 | XA-000-08-002-000-005-167-01 | 28.2 | 1230.3
10:49:06:febtest:INFO: 0-6 | XA-000-08-002-000-007-147-11 | 37.7 | 1195.1
10:49:06:febtest:INFO: 0-7 | XA-000-08-002-000-005-175-01 | 44.1 | 1171.5
10:49:06:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
10:49:10:ST3_smx:INFO: chip: 0-4 53.612520 C 1118.096875 mV
10:49:10:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
10:49:10:ST3_smx:INFO: Electrons
10:49:10:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
10:49:12:ST3_smx:INFO: ----> Checking Analog response
10:49:12:ST3_smx:INFO: ----> Checking broken channels
10:49:12:ST3_smx:INFO: Total # broken ch: 1
10:49:12:ST3_smx:INFO: List FAST: [99]
10:49:12:ST3_smx:INFO: List SLOW: []
10:49:12:ST3_smx:INFO: Holes
10:49:12:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
10:49:14:ST3_smx:INFO: ----> Checking Analog response
10:49:14:ST3_smx:INFO: ----> Checking broken channels
10:49:15:ST3_smx:INFO: Total # broken ch: 1
10:49:15:ST3_smx:INFO: List FAST: [99]
10:49:15:ST3_smx:INFO: List SLOW: []
10:49:15:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:49:15:febtest:INFO: 0-0 | XA-000-08-002-000-007-130-12 | 34.6 | 1183.3
10:49:15:febtest:INFO: 0-1 | XA-000-08-002-000-005-178-06 | 34.6 | 1189.2
10:49:15:febtest:INFO: 0-2 | XA-000-08-002-000-007-137-12 | 44.1 | 1153.7
10:49:16:febtest:INFO: 0-3 | XA-000-08-002-000-005-170-01 | 40.9 | 1171.5
10:49:16:febtest:INFO: 0-4 | XA-000-08-002-000-007-148-11 | 53.6 | 1112.1
10:49:16:febtest:INFO: 0-5 | XA-000-08-002-000-005-167-01 | 28.2 | 1230.3
10:49:16:febtest:INFO: 0-6 | XA-000-08-002-000-007-147-11 | 37.7 | 1189.2
10:49:16:febtest:INFO: 0-7 | XA-000-08-002-000-005-175-01 | 44.1 | 1171.5
10:49:17:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
10:49:21:ST3_smx:INFO: chip: 0-5 28.225000 C 1224.468235 mV
10:49:21:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
10:49:21:ST3_smx:INFO: Electrons
10:49:21:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
10:49:23:ST3_smx:INFO: ----> Checking Analog response
10:49:23:ST3_smx:INFO: ----> Checking broken channels
10:49:23:ST3_smx:INFO: Total # broken ch: 1
10:49:23:ST3_smx:INFO: List FAST: [92]
10:49:23:ST3_smx:INFO: List SLOW: []
10:49:23:ST3_smx:INFO: Holes
10:49:23:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
10:49:25:ST3_smx:INFO: ----> Checking Analog response
10:49:25:ST3_smx:INFO: ----> Checking broken channels
10:49:25:ST3_smx:INFO: Total # broken ch: 1
10:49:25:ST3_smx:INFO: List FAST: [92]
10:49:25:ST3_smx:INFO: List SLOW: []
10:49:25:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:49:26:febtest:INFO: 0-0 | XA-000-08-002-000-007-130-12 | 34.6 | 1183.3
10:49:26:febtest:INFO: 0-1 | XA-000-08-002-000-005-178-06 | 34.6 | 1189.2
10:49:26:febtest:INFO: 0-2 | XA-000-08-002-000-007-137-12 | 44.1 | 1153.7
10:49:26:febtest:INFO: 0-3 | XA-000-08-002-000-005-170-01 | 44.1 | 1171.5
10:49:26:febtest:INFO: 0-4 | XA-000-08-002-000-007-148-11 | 56.8 | 1118.1
10:49:27:febtest:INFO: 0-5 | XA-000-08-002-000-005-167-01 | 28.2 | 1224.5
10:49:27:febtest:INFO: 0-6 | XA-000-08-002-000-007-147-11 | 37.7 | 1189.2
10:49:27:febtest:INFO: 0-7 | XA-000-08-002-000-005-175-01 | 44.1 | 1171.5
10:49:27:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
10:49:31:ST3_smx:INFO: chip: 0-6 34.556970 C 1189.190035 mV
10:49:31:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
10:49:31:ST3_smx:INFO: Electrons
10:49:31:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
10:49:33:ST3_smx:INFO: ----> Checking Analog response
10:49:33:ST3_smx:INFO: ----> Checking broken channels
10:49:33:ST3_smx:INFO: Total # broken ch: 4
10:49:33:ST3_smx:INFO: List FAST: [64, 86, 96, 110]
10:49:33:ST3_smx:INFO: List SLOW: []
10:49:33:ST3_smx:INFO: Holes
10:49:33:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
10:49:35:ST3_smx:INFO: ----> Checking Analog response
10:49:35:ST3_smx:INFO: ----> Checking broken channels
10:49:36:ST3_smx:INFO: Total # broken ch: 4
10:49:36:ST3_smx:INFO: List FAST: [64, 86, 96, 110]
10:49:36:ST3_smx:INFO: List SLOW: []
10:49:36:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:49:36:febtest:INFO: 0-0 | XA-000-08-002-000-007-130-12 | 37.7 | 1183.3
10:49:36:febtest:INFO: 0-1 | XA-000-08-002-000-005-178-06 | 34.6 | 1195.1
10:49:36:febtest:INFO: 0-2 | XA-000-08-002-000-007-137-12 | 47.3 | 1153.7
10:49:36:febtest:INFO: 0-3 | XA-000-08-002-000-005-170-01 | 44.1 | 1171.5
10:49:37:febtest:INFO: 0-4 | XA-000-08-002-000-007-148-11 | 56.8 | 1112.1
10:49:37:febtest:INFO: 0-5 | XA-000-08-002-000-005-167-01 | 28.2 | 1224.5
10:49:37:febtest:INFO: 0-6 | XA-000-08-002-000-007-147-11 | 37.7 | 1189.2
10:49:37:febtest:INFO: 0-7 | XA-000-08-002-000-005-175-01 | 47.3 | 1171.5
10:49:38:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
10:49:41:ST3_smx:INFO: chip: 0-7 40.898880 C 1165.571835 mV
10:49:41:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
10:49:41:ST3_smx:INFO: Electrons
10:49:41:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
10:49:43:ST3_smx:INFO: ----> Checking Analog response
10:49:43:ST3_smx:INFO: ----> Checking broken channels
10:49:44:ST3_smx:INFO: Total # broken ch: 3
10:49:44:ST3_smx:INFO: List FAST: [14, 58, 66]
10:49:44:ST3_smx:INFO: List SLOW: []
10:49:44:ST3_smx:INFO: Holes
10:49:44:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
10:49:46:ST3_smx:INFO: ----> Checking Analog response
10:49:46:ST3_smx:INFO: ----> Checking broken channels
10:49:46:ST3_smx:INFO: Total # broken ch: 3
10:49:46:ST3_smx:INFO: List FAST: [14, 58, 66]
10:49:46:ST3_smx:INFO: List SLOW: []
10:49:46:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:49:46:febtest:INFO: 0-0 | XA-000-08-002-000-007-130-12 | 37.7 | 1183.3
10:49:46:febtest:INFO: 0-1 | XA-000-08-002-000-005-178-06 | 34.6 | 1189.2
10:49:47:febtest:INFO: 0-2 | XA-000-08-002-000-007-137-12 | 47.3 | 1153.7
10:49:47:febtest:INFO: 0-3 | XA-000-08-002-000-005-170-01 | 44.1 | 1165.6
10:49:47:febtest:INFO: 0-4 | XA-000-08-002-000-007-148-11 | 56.8 | 1112.1
10:49:47:febtest:INFO: 0-5 | XA-000-08-002-000-005-167-01 | 31.4 | 1218.6
10:49:47:febtest:INFO: 0-6 | XA-000-08-002-000-007-147-11 | 37.7 | 1189.2
10:49:48:febtest:INFO: 0-7 | XA-000-08-002-000-005-175-01 | 44.1 | 1165.6
############################################################
# S U M M A R Y #
############################################################
{'TEST_NAME': 'FEB-ASIC', 'TEST_DATE': '2023_07_21-10_48_10', 'OPERATOR': 'Oleksandr S.; Robert V.; ', 'PROJECT': 'Production', 'SITE': 'GSI', 'SETUP': 'GSI_TEST_SETUP_1', 'ASIC_ID': 'XA-000-08-002-000-005-175-01', 'FUSED_ID': 6359364699116559089, 'HW_ADDR': 7, 'VERS_NO': '2.2', 'CABLE_SET_ID': '', 'IC_TEMP': '0', 'VDDM': '0', 'AUX': '0', 'CSABIAS': '0', 'VDDM_INT': '0', 'ADC_Chi2': 0.0, 'ADC_NDF': 0, 'ADC_P0': 0.0, 'ADC_P1': 0.006824, 'ADC_P2': -2.485e-06, 'ADC_P0err': 0.001, 'ADC_P1err': 0.001, 'ADC_P2err': 1e-05, 'ADC_VREF_P': 58, 'ADC_VREF_N': 30, 'ADC_VREF_T': 128, 'ADC_VREF_TR': 122, 'THR2_GLB': 30, 'LOOP__PLS': 100, 'CALIB_PLS': 250, 'SnsLoop': 5, 'IFED': 31, 'CSA_BIAS': 15, 'CSA_Chi2': 0.0, 'CSA_NDF': 0, 'CSA_P0': 0.0, 'CSA_P1': 0.0, 'CSA_P2': 0.0, 'CSA_P0err': 0.0, 'CSA_P1err': 0.0, 'CSA_P2err': 0.0, 'CONF_FAIL_REG': 0, 'N_BROKEN_DISC': 3, 'N_BROKEN_FAST': '[14, 58, 66]', 'N_BROKEN_SLOW': '[]', 'P_BROKEN_DISC': 3, 'P_BROKEN_FAST': '[14, 58, 66]', 'P_BROKEN_SLOW': '[]', 'ASIC_QA_category': '', 'N_BROKEN_CABLE': 0, 'LIST_OF_BROKEN_CABLES': 0, 'VI_bInit': ['2.447', '1.5700', '1.846', '2.0040', '6.999', '1.5330', '7.000', '1.5330'], 'VI_aInit': ['0', '0', '0', '0', '0', '0'], 'VI_atEnd': ['0', '0', '0', '0', '0', '0'], 'AMP_CAL': 200, 'PlsLoop': 3, 'N_ANA_PRESENT': 'Analog response OK', 'N_DISC_FAIL_CH': 0, 'N_ANA_FAIL_CH': '0', 'P_ANA_PRESENT': 'Analog response OK', 'P_DISC_FAIL_CH': 0, 'P_ANA_FAIL_CH': '0'}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
10:49:54:ST3_Shared:INFO: /home/cbm/public_html/Production_LogDir//FEB/FEB_2005/B//TestDate_2023_07_21-10_48_10/