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FEB_2006 02.08.23 15:09:42
TextEdit.txt
15:09:36:smx_tester:INFO: Setting Elink clock mode to 160 MHz
15:09:42:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
15:09:42:ST3_Shared:INFO: --------------------------FEB-ASIC--------------------------
15:09:42:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
15:09:42:febtest:INFO: Tsting FEB with SN 2006
15:09:44:smx_tester:INFO: Scanning setup
15:09:44:elinks:INFO: Disabling clock on downlink 0
15:09:44:elinks:INFO: Disabling clock on downlink 1
15:09:44:elinks:INFO: Disabling clock on downlink 2
15:09:44:elinks:INFO: Disabling clock on downlink 3
15:09:44:elinks:INFO: Disabling clock on downlink 4
15:09:44:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:09:44:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
15:09:44:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:09:44:elinks:INFO: Disabling clock on downlink 0
15:09:44:elinks:INFO: Disabling clock on downlink 1
15:09:44:elinks:INFO: Disabling clock on downlink 2
15:09:44:elinks:INFO: Disabling clock on downlink 3
15:09:44:elinks:INFO: Disabling clock on downlink 4
15:09:44:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:09:44:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
15:09:44:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:09:44:elinks:INFO: Disabling clock on downlink 0
15:09:44:elinks:INFO: Disabling clock on downlink 1
15:09:44:elinks:INFO: Disabling clock on downlink 2
15:09:44:elinks:INFO: Disabling clock on downlink 3
15:09:44:elinks:INFO: Disabling clock on downlink 4
15:09:44:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:09:44:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:09:44:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 16
15:09:44:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 17
15:09:44:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 18
15:09:44:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 19
15:09:44:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 20
15:09:44:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 21
15:09:44:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 22
15:09:44:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 23
15:09:44:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24
15:09:44:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25
15:09:44:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26
15:09:44:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27
15:09:44:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28
15:09:44:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29
15:09:44:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30
15:09:44:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31
15:09:44:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:09:44:elinks:INFO: Disabling clock on downlink 0
15:09:44:elinks:INFO: Disabling clock on downlink 1
15:09:44:elinks:INFO: Disabling clock on downlink 2
15:09:44:elinks:INFO: Disabling clock on downlink 3
15:09:44:elinks:INFO: Disabling clock on downlink 4
15:09:44:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:09:44:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
15:09:44:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:09:44:elinks:INFO: Disabling clock on downlink 0
15:09:44:elinks:INFO: Disabling clock on downlink 1
15:09:44:elinks:INFO: Disabling clock on downlink 2
15:09:44:elinks:INFO: Disabling clock on downlink 3
15:09:44:elinks:INFO: Disabling clock on downlink 4
15:09:44:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:09:44:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
15:09:44:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:09:44:setup_element:INFO: Scanning clock phase
15:09:44:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:09:44:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
15:09:45:setup_element:INFO: Clock phase scan results for group 0, downlink 2
15:09:45:setup_element:INFO: Eye window for uplink 16: ______________________________________________________________________XXXXXXXXX_
Clock Delay: 34
15:09:45:setup_element:INFO: Eye window for uplink 17: ______________________________________________________________________XXXXXXXXX_
Clock Delay: 34
15:09:45:setup_element:INFO: Eye window for uplink 18: ______________________________________________________________________XXXXXXXXX_
Clock Delay: 34
15:09:45:setup_element:INFO: Eye window for uplink 19: ______________________________________________________________________XXXXXXXXX_
Clock Delay: 34
15:09:45:setup_element:INFO: Eye window for uplink 20: ______________________________________________________________________XXXXXXXXX_
Clock Delay: 34
15:09:45:setup_element:INFO: Eye window for uplink 21: ______________________________________________________________________XXXXXXXXX_
Clock Delay: 34
15:09:45:setup_element:INFO: Eye window for uplink 22: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
15:09:45:setup_element:INFO: Eye window for uplink 23: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
15:09:45:setup_element:INFO: Eye window for uplink 24: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
15:09:45:setup_element:INFO: Eye window for uplink 25: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
15:09:45:setup_element:INFO: Eye window for uplink 26: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
15:09:45:setup_element:INFO: Eye window for uplink 27: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
15:09:45:setup_element:INFO: Eye window for uplink 28: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
15:09:45:setup_element:INFO: Eye window for uplink 29: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
15:09:45:setup_element:INFO: Eye window for uplink 30: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
15:09:45:setup_element:INFO: Eye window for uplink 31: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
15:09:45:setup_element:INFO: Setting the clock phase to 34 for group 0, downlink 2
15:09:45:setup_element:INFO: Scanning data phases
15:09:45:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:09:45:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
15:09:50:setup_element:INFO: Data phase scan results for group 0, downlink 2
15:09:50:setup_element:INFO: Eye window for uplink 16: XX__________________________________XXXX
Data delay found: 18
15:09:50:setup_element:INFO: Eye window for uplink 17: _________________________________XXXX___
Data delay found: 14
15:09:50:setup_element:INFO: Eye window for uplink 18: XXX_________________________________XXXX
Data delay found: 19
15:09:50:setup_element:INFO: Eye window for uplink 19: __________________________________XXXXX_
Data delay found: 16
15:09:50:setup_element:INFO: Eye window for uplink 20: X___________________________________XXXX
Data delay found: 18
15:09:50:setup_element:INFO: Eye window for uplink 21: ___________________________________XXXXX
Data delay found: 17
15:09:50:setup_element:INFO: Eye window for uplink 22: _________________________________XXXXXX_
Data delay found: 15
15:09:50:setup_element:INFO: Eye window for uplink 23: ________________________________XXXXX___
Data delay found: 14
15:09:50:setup_element:INFO: Eye window for uplink 24: ____XXXXX_______________________________
Data delay found: 26
15:09:50:setup_element:INFO: Eye window for uplink 25: _______XXXXX____________________________
Data delay found: 29
15:09:50:setup_element:INFO: Eye window for uplink 26: _______XXXX_____________________________
Data delay found: 28
15:09:50:setup_element:INFO: Eye window for uplink 27: _________XXXXX__________________________
Data delay found: 31
15:09:50:setup_element:INFO: Eye window for uplink 28: ___________XXXXX________________________
Data delay found: 33
15:09:50:setup_element:INFO: Eye window for uplink 29: ____________XXXXX_______________________
Data delay found: 34
15:09:50:setup_element:INFO: Eye window for uplink 30: _______________XXXXX____________________
Data delay found: 37
15:09:50:setup_element:INFO: Eye window for uplink 31: _____________XXXXX______________________
Data delay found: 35
15:09:50:setup_element:INFO: Setting the data phase to 18 for uplink 16
15:09:50:setup_element:INFO: Setting the data phase to 14 for uplink 17
15:09:50:setup_element:INFO: Setting the data phase to 19 for uplink 18
15:09:50:setup_element:INFO: Setting the data phase to 16 for uplink 19
15:09:50:setup_element:INFO: Setting the data phase to 18 for uplink 20
15:09:50:setup_element:INFO: Setting the data phase to 17 for uplink 21
15:09:51:setup_element:INFO: Setting the data phase to 15 for uplink 22
15:09:51:setup_element:INFO: Setting the data phase to 14 for uplink 23
15:09:51:setup_element:INFO: Setting the data phase to 26 for uplink 24
15:09:51:setup_element:INFO: Setting the data phase to 29 for uplink 25
15:09:51:setup_element:INFO: Setting the data phase to 28 for uplink 26
15:09:51:setup_element:INFO: Setting the data phase to 31 for uplink 27
15:09:51:setup_element:INFO: Setting the data phase to 33 for uplink 28
15:09:51:setup_element:INFO: Setting the data phase to 34 for uplink 29
15:09:51:setup_element:INFO: Setting the data phase to 37 for uplink 30
15:09:51:setup_element:INFO: Setting the data phase to 35 for uplink 31
15:09:51:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 34
Window Length: 71
Eye Windows:
Uplink 16: ______________________________________________________________________XXXXXXXXX_
Uplink 17: ______________________________________________________________________XXXXXXXXX_
Uplink 18: ______________________________________________________________________XXXXXXXXX_
Uplink 19: ______________________________________________________________________XXXXXXXXX_
Uplink 20: ______________________________________________________________________XXXXXXXXX_
Uplink 21: ______________________________________________________________________XXXXXXXXX_
Uplink 22: ______________________________________________________________________XXXXXXXX__
Uplink 23: ______________________________________________________________________XXXXXXXX__
Uplink 24: ______________________________________________________________________XXXXXXXX__
Uplink 25: ______________________________________________________________________XXXXXXXX__
Uplink 26: ______________________________________________________________________XXXXXXXX__
Uplink 27: ______________________________________________________________________XXXXXXXX__
Uplink 28: _______________________________________________________________________XXXXXXX__
Uplink 29: _______________________________________________________________________XXXXXXX__
Uplink 30: _______________________________________________________________________XXXXXXXX_
Uplink 31: _______________________________________________________________________XXXXXXXX_
Data phase characteristics:
Uplink 16:
Optimal Phase: 18
Window Length: 34
Eye Window: XX__________________________________XXXX
Uplink 17:
Optimal Phase: 14
Window Length: 36
Eye Window: _________________________________XXXX___
Uplink 18:
Optimal Phase: 19
Window Length: 33
Eye Window: XXX_________________________________XXXX
Uplink 19:
Optimal Phase: 16
Window Length: 35
Eye Window: __________________________________XXXXX_
Uplink 20:
Optimal Phase: 18
Window Length: 35
Eye Window: X___________________________________XXXX
Uplink 21:
Optimal Phase: 17
Window Length: 35
Eye Window: ___________________________________XXXXX
Uplink 22:
Optimal Phase: 15
Window Length: 34
Eye Window: _________________________________XXXXXX_
Uplink 23:
Optimal Phase: 14
Window Length: 35
Eye Window: ________________________________XXXXX___
Uplink 24:
Optimal Phase: 26
Window Length: 35
Eye Window: ____XXXXX_______________________________
Uplink 25:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 26:
Optimal Phase: 28
Window Length: 36
Eye Window: _______XXXX_____________________________
Uplink 27:
Optimal Phase: 31
Window Length: 35
Eye Window: _________XXXXX__________________________
Uplink 28:
Optimal Phase: 33
Window Length: 35
Eye Window: ___________XXXXX________________________
Uplink 29:
Optimal Phase: 34
Window Length: 35
Eye Window: ____________XXXXX_______________________
Uplink 30:
Optimal Phase: 37
Window Length: 35
Eye Window: _______________XXXXX____________________
Uplink 31:
Optimal Phase: 35
Window Length: 35
Eye Window: _____________XXXXX______________________
]
15:09:51:setup_element:INFO: Beginning SMX ASICs map scan
15:09:51:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:09:51:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
15:09:51:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
15:09:51:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
15:09:51:uplink:INFO: Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
15:09:51:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 23
15:09:51:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 22
15:09:51:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 30
15:09:51:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 31
15:09:51:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 21
15:09:51:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 20
15:09:51:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28
15:09:51:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 29
15:09:51:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 19
15:09:51:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 18
15:09:51:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26
15:09:52:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 27
15:09:52:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 17
15:09:52:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 16
15:09:52:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 24
15:09:52:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 25
15:09:53:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 23), (1, 22)
ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
ASIC address 0x2: (ASIC uplink, uplink): (0, 21), (1, 20)
ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
ASIC address 0x4: (ASIC uplink, uplink): (0, 19), (1, 18)
ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
ASIC address 0x6: (ASIC uplink, uplink): (0, 17), (1, 16)
ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
Clock Phase Characteristic:
Optimal Phase: 34
Window Length: 71
Eye Windows:
Uplink 16: ______________________________________________________________________XXXXXXXXX_
Uplink 17: ______________________________________________________________________XXXXXXXXX_
Uplink 18: ______________________________________________________________________XXXXXXXXX_
Uplink 19: ______________________________________________________________________XXXXXXXXX_
Uplink 20: ______________________________________________________________________XXXXXXXXX_
Uplink 21: ______________________________________________________________________XXXXXXXXX_
Uplink 22: ______________________________________________________________________XXXXXXXX__
Uplink 23: ______________________________________________________________________XXXXXXXX__
Uplink 24: ______________________________________________________________________XXXXXXXX__
Uplink 25: ______________________________________________________________________XXXXXXXX__
Uplink 26: ______________________________________________________________________XXXXXXXX__
Uplink 27: ______________________________________________________________________XXXXXXXX__
Uplink 28: _______________________________________________________________________XXXXXXX__
Uplink 29: _______________________________________________________________________XXXXXXX__
Uplink 30: _______________________________________________________________________XXXXXXXX_
Uplink 31: _______________________________________________________________________XXXXXXXX_
Data phase characteristics:
Uplink 16:
Optimal Phase: 18
Window Length: 34
Eye Window: XX__________________________________XXXX
Uplink 17:
Optimal Phase: 14
Window Length: 36
Eye Window: _________________________________XXXX___
Uplink 18:
Optimal Phase: 19
Window Length: 33
Eye Window: XXX_________________________________XXXX
Uplink 19:
Optimal Phase: 16
Window Length: 35
Eye Window: __________________________________XXXXX_
Uplink 20:
Optimal Phase: 18
Window Length: 35
Eye Window: X___________________________________XXXX
Uplink 21:
Optimal Phase: 17
Window Length: 35
Eye Window: ___________________________________XXXXX
Uplink 22:
Optimal Phase: 15
Window Length: 34
Eye Window: _________________________________XXXXXX_
Uplink 23:
Optimal Phase: 14
Window Length: 35
Eye Window: ________________________________XXXXX___
Uplink 24:
Optimal Phase: 26
Window Length: 35
Eye Window: ____XXXXX_______________________________
Uplink 25:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 26:
Optimal Phase: 28
Window Length: 36
Eye Window: _______XXXX_____________________________
Uplink 27:
Optimal Phase: 31
Window Length: 35
Eye Window: _________XXXXX__________________________
Uplink 28:
Optimal Phase: 33
Window Length: 35
Eye Window: ___________XXXXX________________________
Uplink 29:
Optimal Phase: 34
Window Length: 35
Eye Window: ____________XXXXX_______________________
Uplink 30:
Optimal Phase: 37
Window Length: 35
Eye Window: _______________XXXXX____________________
Uplink 31:
Optimal Phase: 35
Window Length: 35
Eye Window: _____________XXXXX______________________
15:09:53:setup_element:INFO: Performing Elink synchronization
15:09:53:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:09:53:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
15:09:53:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
15:09:53:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
15:09:53:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2
15:09:53:uplink:INFO: Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
15:09:53:ST3_emu:INFO: Number of chips: 8
15:09:53:ST3_emu:INFO: Chip address: 0x0
15:09:53:ST3_emu:INFO: Chip address: 0x1
15:09:53:ST3_emu:INFO: Chip address: 0x2
15:09:53:ST3_emu:INFO: Chip address: 0x3
15:09:53:ST3_emu:INFO: Chip address: 0x4
15:09:53:ST3_emu:INFO: Chip address: 0x5
15:09:53:ST3_emu:INFO: Chip address: 0x6
15:09:54:ST3_emu:INFO: Chip address: 0x7
15:09:54:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:09:54:febtest:INFO: 0-0 | XA-000-08-002-001-007-068-11 | 31.4 | 1212.7
15:09:54:febtest:INFO: 0-1 | XA-000-08-002-001-007-073-11 | 21.9 | 1224.5
15:09:55:febtest:INFO: 0-2 | XA-000-08-002-001-007-083-12 | 40.9 | 1177.4
15:09:55:febtest:INFO: 0-3 | XA-000-08-002-001-007-080-12 | 12.4 | 1259.6
15:09:55:febtest:INFO: 0-4 | XA-000-08-002-001-007-077-11 | 34.6 | 1189.2
15:09:55:febtest:INFO: 0-5 | XA-000-08-002-001-007-085-12 | 37.7 | 1165.6
15:09:56:febtest:INFO: 0-6 | XA-000-08-002-001-007-071-11 | 47.3 | 1147.8
15:09:56:febtest:INFO: 0-7 | XA-000-08-002-002-007-108-04 | 37.7 | 1165.6
15:09:56:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:10:00:ST3_smx:INFO: chip: 0-0 28.225000 C 1206.851500 mV
15:10:00:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:10:00:ST3_smx:INFO: Electrons
15:10:00:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:10:02:ST3_smx:INFO: ----> Checking Analog response
15:10:02:ST3_smx:INFO: ----> Checking broken channels
15:10:02:ST3_smx:INFO: Total # broken ch: 0
15:10:02:ST3_smx:INFO: List FAST: []
15:10:02:ST3_smx:INFO: List SLOW: []
15:10:02:ST3_smx:INFO: Holes
15:10:02:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:10:04:ST3_smx:INFO: ----> Checking Analog response
15:10:04:ST3_smx:INFO: ----> Checking broken channels
15:10:04:ST3_smx:INFO: Total # broken ch: 0
15:10:04:ST3_smx:INFO: List FAST: []
15:10:04:ST3_smx:INFO: List SLOW: []
15:10:04:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:10:04:febtest:INFO: 0-0 | XA-000-08-002-001-007-068-11 | 28.2 | 1201.0
15:10:05:febtest:INFO: 0-1 | XA-000-08-002-001-007-073-11 | 21.9 | 1218.6
15:10:05:febtest:INFO: 0-2 | XA-000-08-002-001-007-083-12 | 37.7 | 1177.4
15:10:05:febtest:INFO: 0-3 | XA-000-08-002-001-007-080-12 | 12.4 | 1259.6
15:10:05:febtest:INFO: 0-4 | XA-000-08-002-001-007-077-11 | 34.6 | 1189.2
15:10:06:febtest:INFO: 0-5 | XA-000-08-002-001-007-085-12 | 37.7 | 1165.6
15:10:06:febtest:INFO: 0-6 | XA-000-08-002-001-007-071-11 | 47.3 | 1141.9
15:10:06:febtest:INFO: 0-7 | XA-000-08-002-002-007-108-04 | 37.7 | 1165.6
15:10:06:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:10:10:ST3_smx:INFO: chip: 0-1 31.389742 C 1171.483840 mV
15:10:10:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:10:10:ST3_smx:INFO: Electrons
15:10:10:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:10:12:ST3_smx:INFO: ----> Checking Analog response
15:10:12:ST3_smx:INFO: ----> Checking broken channels
15:10:13:ST3_smx:INFO: Total # broken ch: 0
15:10:13:ST3_smx:INFO: List FAST: []
15:10:13:ST3_smx:INFO: List SLOW: []
15:10:13:ST3_smx:INFO: Holes
15:10:13:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:10:15:ST3_smx:INFO: ----> Checking Analog response
15:10:15:ST3_smx:INFO: ----> Checking broken channels
15:10:15:ST3_smx:INFO: Total # broken ch: 0
15:10:15:ST3_smx:INFO: List FAST: []
15:10:15:ST3_smx:INFO: List SLOW: []
15:10:15:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:10:15:febtest:INFO: 0-0 | XA-000-08-002-001-007-068-11 | 28.2 | 1201.0
15:10:15:febtest:INFO: 0-1 | XA-000-08-002-001-007-073-11 | 34.6 | 1165.6
15:10:16:febtest:INFO: 0-2 | XA-000-08-002-001-007-083-12 | 37.7 | 1177.4
15:10:16:febtest:INFO: 0-3 | XA-000-08-002-001-007-080-12 | 12.4 | 1259.6
15:10:16:febtest:INFO: 0-4 | XA-000-08-002-001-007-077-11 | 31.4 | 1189.2
15:10:16:febtest:INFO: 0-5 | XA-000-08-002-001-007-085-12 | 37.7 | 1165.6
15:10:16:febtest:INFO: 0-6 | XA-000-08-002-001-007-071-11 | 47.3 | 1147.8
15:10:17:febtest:INFO: 0-7 | XA-000-08-002-002-007-108-04 | 37.7 | 1165.6
15:10:17:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:10:21:ST3_smx:INFO: chip: 0-2 37.726682 C 1153.732915 mV
15:10:21:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:10:21:ST3_smx:INFO: Electrons
15:10:21:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:10:23:ST3_smx:INFO: ----> Checking Analog response
15:10:23:ST3_smx:INFO: ----> Checking broken channels
15:10:23:ST3_smx:INFO: Total # broken ch: 0
15:10:23:ST3_smx:INFO: List FAST: []
15:10:23:ST3_smx:INFO: List SLOW: []
15:10:23:ST3_smx:INFO: Holes
15:10:23:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:10:25:ST3_smx:INFO: ----> Checking Analog response
15:10:25:ST3_smx:INFO: ----> Checking broken channels
15:10:25:ST3_smx:INFO: Total # broken ch: 0
15:10:25:ST3_smx:INFO: List FAST: []
15:10:25:ST3_smx:INFO: List SLOW: []
15:10:25:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:10:26:febtest:INFO: 0-0 | XA-000-08-002-001-007-068-11 | 28.2 | 1201.0
15:10:26:febtest:INFO: 0-1 | XA-000-08-002-001-007-073-11 | 34.6 | 1165.6
15:10:26:febtest:INFO: 0-2 | XA-000-08-002-001-007-083-12 | 40.9 | 1153.7
15:10:26:febtest:INFO: 0-3 | XA-000-08-002-001-007-080-12 | 12.4 | 1259.6
15:10:26:febtest:INFO: 0-4 | XA-000-08-002-001-007-077-11 | 31.4 | 1183.3
15:10:27:febtest:INFO: 0-5 | XA-000-08-002-001-007-085-12 | 37.7 | 1165.6
15:10:27:febtest:INFO: 0-6 | XA-000-08-002-001-007-071-11 | 47.3 | 1141.9
15:10:27:febtest:INFO: 0-7 | XA-000-08-002-002-007-108-04 | 37.7 | 1165.6
15:10:27:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:10:31:ST3_smx:INFO: chip: 0-3 18.745682 C 1218.600960 mV
15:10:31:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:10:31:ST3_smx:INFO: Electrons
15:10:31:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:10:33:ST3_smx:INFO: ----> Checking Analog response
15:10:33:ST3_smx:INFO: ----> Checking broken channels
15:10:33:ST3_smx:INFO: Total # broken ch: 0
15:10:33:ST3_smx:INFO: List FAST: []
15:10:33:ST3_smx:INFO: List SLOW: []
15:10:33:ST3_smx:INFO: Holes
15:10:33:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:10:36:ST3_smx:INFO: ----> Checking Analog response
15:10:36:ST3_smx:INFO: ----> Checking broken channels
15:10:36:ST3_smx:INFO: Total # broken ch: 0
15:10:36:ST3_smx:INFO: List FAST: []
15:10:36:ST3_smx:INFO: List SLOW: []
15:10:36:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:10:36:febtest:INFO: 0-0 | XA-000-08-002-001-007-068-11 | 28.2 | 1201.0
15:10:36:febtest:INFO: 0-1 | XA-000-08-002-001-007-073-11 | 34.6 | 1165.6
15:10:36:febtest:INFO: 0-2 | XA-000-08-002-001-007-083-12 | 40.9 | 1153.7
15:10:37:febtest:INFO: 0-3 | XA-000-08-002-001-007-080-12 | 21.9 | 1218.6
15:10:37:febtest:INFO: 0-4 | XA-000-08-002-001-007-077-11 | 34.6 | 1189.2
15:10:37:febtest:INFO: 0-5 | XA-000-08-002-001-007-085-12 | 37.7 | 1165.6
15:10:37:febtest:INFO: 0-6 | XA-000-08-002-001-007-071-11 | 47.3 | 1141.9
15:10:38:febtest:INFO: 0-7 | XA-000-08-002-002-007-108-04 | 37.7 | 1159.7
15:10:38:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:10:42:ST3_smx:INFO: chip: 0-4 40.898880 C 1153.732915 mV
15:10:42:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:10:42:ST3_smx:INFO: Electrons
15:10:42:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:10:44:ST3_smx:INFO: ----> Checking Analog response
15:10:44:ST3_smx:INFO: ----> Checking broken channels
15:10:44:ST3_smx:INFO: Total # broken ch: 0
15:10:44:ST3_smx:INFO: List FAST: []
15:10:44:ST3_smx:INFO: List SLOW: []
15:10:44:ST3_smx:INFO: Holes
15:10:44:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:10:46:ST3_smx:INFO: ----> Checking Analog response
15:10:46:ST3_smx:INFO: ----> Checking broken channels
15:10:46:ST3_smx:INFO: Total # broken ch: 0
15:10:46:ST3_smx:INFO: List FAST: []
15:10:46:ST3_smx:INFO: List SLOW: []
15:10:46:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:10:47:febtest:INFO: 0-0 | XA-000-08-002-001-007-068-11 | 28.2 | 1201.0
15:10:47:febtest:INFO: 0-1 | XA-000-08-002-001-007-073-11 | 34.6 | 1165.6
15:10:47:febtest:INFO: 0-2 | XA-000-08-002-001-007-083-12 | 40.9 | 1153.7
15:10:47:febtest:INFO: 0-3 | XA-000-08-002-001-007-080-12 | 21.9 | 1218.6
15:10:47:febtest:INFO: 0-4 | XA-000-08-002-001-007-077-11 | 40.9 | 1153.7
15:10:48:febtest:INFO: 0-5 | XA-000-08-002-001-007-085-12 | 37.7 | 1165.6
15:10:48:febtest:INFO: 0-6 | XA-000-08-002-001-007-071-11 | 47.3 | 1141.9
15:10:48:febtest:INFO: 0-7 | XA-000-08-002-002-007-108-04 | 37.7 | 1159.7
15:10:48:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:10:52:ST3_smx:INFO: chip: 0-5 40.898880 C 1135.937260 mV
15:10:52:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:10:52:ST3_smx:INFO: Electrons
15:10:52:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:10:54:ST3_smx:INFO: ----> Checking Analog response
15:10:54:ST3_smx:INFO: ----> Checking broken channels
15:10:55:ST3_smx:INFO: Total # broken ch: 0
15:10:55:ST3_smx:INFO: List FAST: []
15:10:55:ST3_smx:INFO: List SLOW: []
15:10:55:ST3_smx:INFO: Holes
15:10:55:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:10:57:ST3_smx:INFO: ----> Checking Analog response
15:10:57:ST3_smx:INFO: ----> Checking broken channels
15:10:57:ST3_smx:INFO: Total # broken ch: 0
15:10:57:ST3_smx:INFO: List FAST: []
15:10:57:ST3_smx:INFO: List SLOW: []
15:10:57:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:10:57:febtest:INFO: 0-0 | XA-000-08-002-001-007-068-11 | 28.2 | 1201.0
15:10:57:febtest:INFO: 0-1 | XA-000-08-002-001-007-073-11 | 34.6 | 1165.6
15:10:57:febtest:INFO: 0-2 | XA-000-08-002-001-007-083-12 | 40.9 | 1153.7
15:10:58:febtest:INFO: 0-3 | XA-000-08-002-001-007-080-12 | 21.9 | 1212.7
15:10:58:febtest:INFO: 0-4 | XA-000-08-002-001-007-077-11 | 40.9 | 1153.7
15:10:58:febtest:INFO: 0-5 | XA-000-08-002-001-007-085-12 | 44.1 | 1130.0
15:10:58:febtest:INFO: 0-6 | XA-000-08-002-001-007-071-11 | 50.4 | 1141.9
15:10:59:febtest:INFO: 0-7 | XA-000-08-002-002-007-108-04 | 37.7 | 1159.7
15:10:59:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:11:03:ST3_smx:INFO: chip: 0-6 50.430383 C 1124.048640 mV
15:11:03:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:11:03:ST3_smx:INFO: Electrons
15:11:03:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:11:05:ST3_smx:INFO: ----> Checking Analog response
15:11:05:ST3_smx:INFO: ----> Checking broken channels
15:11:05:ST3_smx:INFO: Total # broken ch: 0
15:11:05:ST3_smx:INFO: List FAST: []
15:11:05:ST3_smx:INFO: List SLOW: []
15:11:05:ST3_smx:INFO: Holes
15:11:05:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:11:07:ST3_smx:INFO: ----> Checking Analog response
15:11:07:ST3_smx:INFO: ----> Checking broken channels
15:11:07:ST3_smx:INFO: Total # broken ch: 0
15:11:07:ST3_smx:INFO: List FAST: []
15:11:07:ST3_smx:INFO: List SLOW: []
15:11:07:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:11:07:febtest:INFO: 0-0 | XA-000-08-002-001-007-068-11 | 28.2 | 1195.1
15:11:08:febtest:INFO: 0-1 | XA-000-08-002-001-007-073-11 | 34.6 | 1165.6
15:11:08:febtest:INFO: 0-2 | XA-000-08-002-001-007-083-12 | 40.9 | 1147.8
15:11:08:febtest:INFO: 0-3 | XA-000-08-002-001-007-080-12 | 21.9 | 1212.7
15:11:08:febtest:INFO: 0-4 | XA-000-08-002-001-007-077-11 | 40.9 | 1153.7
15:11:09:febtest:INFO: 0-5 | XA-000-08-002-001-007-085-12 | 44.1 | 1130.0
15:11:09:febtest:INFO: 0-6 | XA-000-08-002-001-007-071-11 | 50.4 | 1124.0
15:11:09:febtest:INFO: 0-7 | XA-000-08-002-002-007-108-04 | 37.7 | 1159.7
15:11:09:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:11:13:ST3_smx:INFO: chip: 0-7 40.898880 C 1141.874115 mV
15:11:13:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:11:13:ST3_smx:INFO: Electrons
15:11:13:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:11:15:ST3_smx:INFO: ----> Checking Analog response
15:11:15:ST3_smx:INFO: ----> Checking broken channels
15:11:15:ST3_smx:INFO: Total # broken ch: 0
15:11:15:ST3_smx:INFO: List FAST: []
15:11:15:ST3_smx:INFO: List SLOW: []
15:11:15:ST3_smx:INFO: Holes
15:11:15:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:11:17:ST3_smx:INFO: ----> Checking Analog response
15:11:17:ST3_smx:INFO: ----> Checking broken channels
15:11:18:ST3_smx:INFO: Total # broken ch: 0
15:11:18:ST3_smx:INFO: List FAST: []
15:11:18:ST3_smx:INFO: List SLOW: []
15:11:18:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:11:18:febtest:INFO: 0-0 | XA-000-08-002-001-007-068-11 | 28.2 | 1195.1
15:11:18:febtest:INFO: 0-1 | XA-000-08-002-001-007-073-11 | 34.6 | 1159.7
15:11:18:febtest:INFO: 0-2 | XA-000-08-002-001-007-083-12 | 40.9 | 1153.7
15:11:18:febtest:INFO: 0-3 | XA-000-08-002-001-007-080-12 | 21.9 | 1212.7
15:11:19:febtest:INFO: 0-4 | XA-000-08-002-001-007-077-11 | 40.9 | 1153.7
15:11:19:febtest:INFO: 0-5 | XA-000-08-002-001-007-085-12 | 44.1 | 1130.0
15:11:19:febtest:INFO: 0-6 | XA-000-08-002-001-007-071-11 | 53.6 | 1124.0
15:11:19:febtest:INFO: 0-7 | XA-000-08-002-002-007-108-04 | 44.1 | 1135.9
############################################################
# S U M M A R Y #
############################################################
{'TEST_NAME': 'FEB-ASIC', 'TEST_DATE': '2023_08_02-15_09_42', 'OPERATOR': 'Oleksandr S.; Robert V.; ', 'PROJECT': 'Production', 'SITE': 'GSI', 'SETUP': 'GSI_TEST_SETUP_1', 'ASIC_ID': 'XA-000-08-002-002-007-108-04', 'FUSED_ID': 6359364699118663364, 'HW_ADDR': 7, 'VERS_NO': '2.2', 'CABLE_SET_ID': '', 'IC_TEMP': '0', 'VDDM': '0', 'AUX': '0', 'CSABIAS': '0', 'VDDM_INT': '0', 'ADC_Chi2': 0.0, 'ADC_NDF': 0, 'ADC_P0': 0.0, 'ADC_P1': 0.006824, 'ADC_P2': -2.485e-06, 'ADC_P0err': 0.001, 'ADC_P1err': 0.001, 'ADC_P2err': 1e-05, 'ADC_VREF_P': 58, 'ADC_VREF_N': 30, 'ADC_VREF_T': 128, 'ADC_VREF_TR': 122, 'THR2_GLB': 30, 'LOOP__PLS': 100, 'CALIB_PLS': 250, 'SnsLoop': 5, 'IFED': 31, 'CSA_BIAS': 15, 'CSA_Chi2': 0.0, 'CSA_NDF': 0, 'CSA_P0': 0.0, 'CSA_P1': 0.0, 'CSA_P2': 0.0, 'CSA_P0err': 0.0, 'CSA_P1err': 0.0, 'CSA_P2err': 0.0, 'CONF_FAIL_REG': 0, 'N_BROKEN_DISC': 0, 'N_BROKEN_FAST': '[]', 'N_BROKEN_SLOW': '[]', 'P_BROKEN_DISC': 0, 'P_BROKEN_FAST': '[]', 'P_BROKEN_SLOW': '[]', 'ASIC_QA_category': '', 'N_BROKEN_CABLE': 0, 'LIST_OF_BROKEN_CABLES': 0, 'VI_bInit': ['2.448', '1.5850', '1.846', '1.9430', '7.000', '1.5370', '7.000', '1.5370'], 'VI_aInit': ['2.450', '1.9830', '1.850', '1.4710', '7.000', '1.5300', '7.000', '1.5300'], 'VI_atEnd': ['0', '0', '0', '0', '0', '0'], 'AMP_CAL': 200, 'PlsLoop': 3, 'N_ANA_PRESENT': 'Analog response OK', 'N_DISC_FAIL_CH': 0, 'N_ANA_FAIL_CH': '0', 'P_ANA_PRESENT': 'Analog response OK', 'P_DISC_FAIL_CH': 0, 'P_ANA_FAIL_CH': '0'}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
15:11:23:ST3_Shared:INFO: /home/cbm/public_html/Production_LogDir//FEB/FEB_2006/B//TestDate_2023_08_02-15_09_42/