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FEB_2008 02.08.23 15:50:24
TextEdit.txt
15:50:03:smx_tester:INFO: Setting Elink clock mode to 160 MHz
15:50:03:ST3_emu:ERROR: device described in file: ../ST3_BASE/config/feb8_2_devices.xml not found!!!
15:50:09:smx_tester:INFO: Setting Elink clock mode to 160 MHz
15:50:24:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
15:50:24:ST3_Shared:INFO: --------------------------FEB-ASIC--------------------------
15:50:24:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
15:50:24:febtest:INFO: Tsting FEB with SN 2008
15:50:26:smx_tester:INFO: Scanning setup
15:50:26:elinks:INFO: Disabling clock on downlink 0
15:50:26:elinks:INFO: Disabling clock on downlink 1
15:50:26:elinks:INFO: Disabling clock on downlink 2
15:50:26:elinks:INFO: Disabling clock on downlink 3
15:50:26:elinks:INFO: Disabling clock on downlink 4
15:50:26:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:50:26:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
15:50:26:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:50:26:elinks:INFO: Disabling clock on downlink 0
15:50:26:elinks:INFO: Disabling clock on downlink 1
15:50:26:elinks:INFO: Disabling clock on downlink 2
15:50:26:elinks:INFO: Disabling clock on downlink 3
15:50:26:elinks:INFO: Disabling clock on downlink 4
15:50:26:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:50:26:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
15:50:26:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:50:26:elinks:INFO: Disabling clock on downlink 0
15:50:26:elinks:INFO: Disabling clock on downlink 1
15:50:26:elinks:INFO: Disabling clock on downlink 2
15:50:26:elinks:INFO: Disabling clock on downlink 3
15:50:26:elinks:INFO: Disabling clock on downlink 4
15:50:26:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:50:26:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:50:26:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 16
15:50:26:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 17
15:50:26:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 18
15:50:26:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 19
15:50:26:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 20
15:50:26:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 21
15:50:26:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 22
15:50:26:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 23
15:50:26:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24
15:50:26:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25
15:50:26:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26
15:50:26:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27
15:50:26:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28
15:50:26:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29
15:50:26:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30
15:50:26:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31
15:50:26:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:50:26:elinks:INFO: Disabling clock on downlink 0
15:50:26:elinks:INFO: Disabling clock on downlink 1
15:50:26:elinks:INFO: Disabling clock on downlink 2
15:50:26:elinks:INFO: Disabling clock on downlink 3
15:50:26:elinks:INFO: Disabling clock on downlink 4
15:50:26:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:50:26:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
15:50:26:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:50:26:elinks:INFO: Disabling clock on downlink 0
15:50:26:elinks:INFO: Disabling clock on downlink 1
15:50:26:elinks:INFO: Disabling clock on downlink 2
15:50:26:elinks:INFO: Disabling clock on downlink 3
15:50:26:elinks:INFO: Disabling clock on downlink 4
15:50:26:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:50:26:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
15:50:26:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:50:26:setup_element:INFO: Scanning clock phase
15:50:26:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:50:27:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
15:50:27:setup_element:INFO: Clock phase scan results for group 0, downlink 2
15:50:27:setup_element:INFO: Eye window for uplink 16: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
15:50:27:setup_element:INFO: Eye window for uplink 17: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
15:50:27:setup_element:INFO: Eye window for uplink 18: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
15:50:27:setup_element:INFO: Eye window for uplink 19: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
15:50:27:setup_element:INFO: Eye window for uplink 20: ______________________________________________________________________XXXXXXXXX_
Clock Delay: 34
15:50:27:setup_element:INFO: Eye window for uplink 21: ______________________________________________________________________XXXXXXXXX_
Clock Delay: 34
15:50:27:setup_element:INFO: Eye window for uplink 22: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
15:50:27:setup_element:INFO: Eye window for uplink 23: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
15:50:27:setup_element:INFO: Eye window for uplink 24: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
15:50:27:setup_element:INFO: Eye window for uplink 25: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
15:50:27:setup_element:INFO: Eye window for uplink 26: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
15:50:27:setup_element:INFO: Eye window for uplink 27: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
15:50:27:setup_element:INFO: Eye window for uplink 28: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
15:50:27:setup_element:INFO: Eye window for uplink 29: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
15:50:27:setup_element:INFO: Eye window for uplink 30: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
15:50:27:setup_element:INFO: Eye window for uplink 31: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
15:50:27:setup_element:INFO: Setting the clock phase to 33 for group 0, downlink 2
15:50:27:setup_element:INFO: Scanning data phases
15:50:27:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:50:27:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
15:50:32:setup_element:INFO: Data phase scan results for group 0, downlink 2
15:50:32:setup_element:INFO: Eye window for uplink 16: XXX___________________________________XX
Data delay found: 20
15:50:32:setup_element:INFO: Eye window for uplink 17: __________________________________XXXXX_
Data delay found: 16
15:50:32:setup_element:INFO: Eye window for uplink 18: XX_________________________________XXXXX
Data delay found: 18
15:50:32:setup_element:INFO: Eye window for uplink 19: _________________________________XXXXX__
Data delay found: 15
15:50:32:setup_element:INFO: Eye window for uplink 20: XX___________________________________XXX
Data delay found: 19
15:50:32:setup_element:INFO: Eye window for uplink 21: X__________________________________XXXXX
Data delay found: 17
15:50:32:setup_element:INFO: Eye window for uplink 22: XX__________________________________XXXX
Data delay found: 18
15:50:32:setup_element:INFO: Eye window for uplink 23: ___________________________________XXXX_
Data delay found: 16
15:50:32:setup_element:INFO: Eye window for uplink 24: _____XXXXX______________________________
Data delay found: 27
15:50:32:setup_element:INFO: Eye window for uplink 25: ________XXXX____________________________
Data delay found: 29
15:50:32:setup_element:INFO: Eye window for uplink 26: _____XXXXXX_____________________________
Data delay found: 27
15:50:32:setup_element:INFO: Eye window for uplink 27: ________XXXXX___________________________
Data delay found: 30
15:50:32:setup_element:INFO: Eye window for uplink 28: ___________XXXXXX_______________________
Data delay found: 33
15:50:32:setup_element:INFO: Eye window for uplink 29: _____________XXXXX______________________
Data delay found: 35
15:50:32:setup_element:INFO: Eye window for uplink 30: ________________XXXXXX__________________
Data delay found: 38
15:50:32:setup_element:INFO: Eye window for uplink 31: ______________XXXXXXX___________________
Data delay found: 37
15:50:32:setup_element:INFO: Setting the data phase to 20 for uplink 16
15:50:32:setup_element:INFO: Setting the data phase to 16 for uplink 17
15:50:32:setup_element:INFO: Setting the data phase to 18 for uplink 18
15:50:32:setup_element:INFO: Setting the data phase to 15 for uplink 19
15:50:32:setup_element:INFO: Setting the data phase to 19 for uplink 20
15:50:32:setup_element:INFO: Setting the data phase to 17 for uplink 21
15:50:32:setup_element:INFO: Setting the data phase to 18 for uplink 22
15:50:32:setup_element:INFO: Setting the data phase to 16 for uplink 23
15:50:32:setup_element:INFO: Setting the data phase to 27 for uplink 24
15:50:32:setup_element:INFO: Setting the data phase to 29 for uplink 25
15:50:32:setup_element:INFO: Setting the data phase to 27 for uplink 26
15:50:33:setup_element:INFO: Setting the data phase to 30 for uplink 27
15:50:33:setup_element:INFO: Setting the data phase to 33 for uplink 28
15:50:33:setup_element:INFO: Setting the data phase to 35 for uplink 29
15:50:33:setup_element:INFO: Setting the data phase to 38 for uplink 30
15:50:33:setup_element:INFO: Setting the data phase to 37 for uplink 31
15:50:33:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 33
Window Length: 70
Eye Windows:
Uplink 16: _______________________________________________________________________XXXXXXXX_
Uplink 17: _______________________________________________________________________XXXXXXXX_
Uplink 18: ______________________________________________________________________XXXXXXXX__
Uplink 19: ______________________________________________________________________XXXXXXXX__
Uplink 20: ______________________________________________________________________XXXXXXXXX_
Uplink 21: ______________________________________________________________________XXXXXXXXX_
Uplink 22: ______________________________________________________________________XXXXXXXX__
Uplink 23: ______________________________________________________________________XXXXXXXX__
Uplink 24: _____________________________________________________________________XXXXXXXX___
Uplink 25: _____________________________________________________________________XXXXXXXX___
Uplink 26: _____________________________________________________________________XXXXXXXX___
Uplink 27: _____________________________________________________________________XXXXXXXX___
Uplink 28: _______________________________________________________________________XXXXXXX__
Uplink 29: _______________________________________________________________________XXXXXXX__
Uplink 30: _______________________________________________________________________XXXXXXX__
Uplink 31: _______________________________________________________________________XXXXXXX__
Data phase characteristics:
Uplink 16:
Optimal Phase: 20
Window Length: 35
Eye Window: XXX___________________________________XX
Uplink 17:
Optimal Phase: 16
Window Length: 35
Eye Window: __________________________________XXXXX_
Uplink 18:
Optimal Phase: 18
Window Length: 33
Eye Window: XX_________________________________XXXXX
Uplink 19:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
Uplink 20:
Optimal Phase: 19
Window Length: 35
Eye Window: XX___________________________________XXX
Uplink 21:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXXX
Uplink 22:
Optimal Phase: 18
Window Length: 34
Eye Window: XX__________________________________XXXX
Uplink 23:
Optimal Phase: 16
Window Length: 36
Eye Window: ___________________________________XXXX_
Uplink 24:
Optimal Phase: 27
Window Length: 35
Eye Window: _____XXXXX______________________________
Uplink 25:
Optimal Phase: 29
Window Length: 36
Eye Window: ________XXXX____________________________
Uplink 26:
Optimal Phase: 27
Window Length: 34
Eye Window: _____XXXXXX_____________________________
Uplink 27:
Optimal Phase: 30
Window Length: 35
Eye Window: ________XXXXX___________________________
Uplink 28:
Optimal Phase: 33
Window Length: 34
Eye Window: ___________XXXXXX_______________________
Uplink 29:
Optimal Phase: 35
Window Length: 35
Eye Window: _____________XXXXX______________________
Uplink 30:
Optimal Phase: 38
Window Length: 34
Eye Window: ________________XXXXXX__________________
Uplink 31:
Optimal Phase: 37
Window Length: 33
Eye Window: ______________XXXXXXX___________________
]
15:50:33:setup_element:INFO: Beginning SMX ASICs map scan
15:50:33:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:50:33:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
15:50:33:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
15:50:33:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
15:50:33:uplink:INFO: Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
15:50:33:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 23
15:50:33:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 22
15:50:33:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 30
15:50:33:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 31
15:50:33:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 21
15:50:33:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 20
15:50:33:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28
15:50:33:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 29
15:50:33:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 19
15:50:33:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 18
15:50:34:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26
15:50:34:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 27
15:50:34:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 17
15:50:34:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 16
15:50:34:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 24
15:50:34:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 25
15:50:35:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 23), (1, 22)
ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
ASIC address 0x2: (ASIC uplink, uplink): (0, 21), (1, 20)
ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
ASIC address 0x4: (ASIC uplink, uplink): (0, 19), (1, 18)
ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
ASIC address 0x6: (ASIC uplink, uplink): (0, 17), (1, 16)
ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
Clock Phase Characteristic:
Optimal Phase: 33
Window Length: 70
Eye Windows:
Uplink 16: _______________________________________________________________________XXXXXXXX_
Uplink 17: _______________________________________________________________________XXXXXXXX_
Uplink 18: ______________________________________________________________________XXXXXXXX__
Uplink 19: ______________________________________________________________________XXXXXXXX__
Uplink 20: ______________________________________________________________________XXXXXXXXX_
Uplink 21: ______________________________________________________________________XXXXXXXXX_
Uplink 22: ______________________________________________________________________XXXXXXXX__
Uplink 23: ______________________________________________________________________XXXXXXXX__
Uplink 24: _____________________________________________________________________XXXXXXXX___
Uplink 25: _____________________________________________________________________XXXXXXXX___
Uplink 26: _____________________________________________________________________XXXXXXXX___
Uplink 27: _____________________________________________________________________XXXXXXXX___
Uplink 28: _______________________________________________________________________XXXXXXX__
Uplink 29: _______________________________________________________________________XXXXXXX__
Uplink 30: _______________________________________________________________________XXXXXXX__
Uplink 31: _______________________________________________________________________XXXXXXX__
Data phase characteristics:
Uplink 16:
Optimal Phase: 20
Window Length: 35
Eye Window: XXX___________________________________XX
Uplink 17:
Optimal Phase: 16
Window Length: 35
Eye Window: __________________________________XXXXX_
Uplink 18:
Optimal Phase: 18
Window Length: 33
Eye Window: XX_________________________________XXXXX
Uplink 19:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
Uplink 20:
Optimal Phase: 19
Window Length: 35
Eye Window: XX___________________________________XXX
Uplink 21:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXXX
Uplink 22:
Optimal Phase: 18
Window Length: 34
Eye Window: XX__________________________________XXXX
Uplink 23:
Optimal Phase: 16
Window Length: 36
Eye Window: ___________________________________XXXX_
Uplink 24:
Optimal Phase: 27
Window Length: 35
Eye Window: _____XXXXX______________________________
Uplink 25:
Optimal Phase: 29
Window Length: 36
Eye Window: ________XXXX____________________________
Uplink 26:
Optimal Phase: 27
Window Length: 34
Eye Window: _____XXXXXX_____________________________
Uplink 27:
Optimal Phase: 30
Window Length: 35
Eye Window: ________XXXXX___________________________
Uplink 28:
Optimal Phase: 33
Window Length: 34
Eye Window: ___________XXXXXX_______________________
Uplink 29:
Optimal Phase: 35
Window Length: 35
Eye Window: _____________XXXXX______________________
Uplink 30:
Optimal Phase: 38
Window Length: 34
Eye Window: ________________XXXXXX__________________
Uplink 31:
Optimal Phase: 37
Window Length: 33
Eye Window: ______________XXXXXXX___________________
15:50:35:setup_element:INFO: Performing Elink synchronization
15:50:35:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:50:35:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
15:50:35:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
15:50:35:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
15:50:35:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2
15:50:35:uplink:INFO: Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
15:50:36:ST3_emu:INFO: Number of chips: 8
15:50:36:ST3_emu:INFO: Chip address: 0x0
15:50:36:ST3_emu:INFO: Chip address: 0x1
15:50:36:ST3_emu:INFO: Chip address: 0x2
15:50:36:ST3_emu:INFO: Chip address: 0x3
15:50:36:ST3_emu:INFO: Chip address: 0x4
15:50:36:ST3_emu:INFO: Chip address: 0x5
15:50:36:ST3_emu:INFO: Chip address: 0x6
15:50:36:ST3_emu:INFO: Chip address: 0x7
15:50:36:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:50:36:febtest:INFO: 0-0 | XA-000-08-002-001-007-208-06 | 28.2 | 1230.3
15:50:37:febtest:INFO: 0-1 | XA-000-08-002-001-007-179-13 | 44.1 | 1171.5
15:50:37:febtest:INFO: 0-2 | XA-000-08-002-001-007-192-01 | 44.1 | 1177.4
15:50:37:febtest:INFO: 0-3 | XA-000-08-002-001-007-178-13 | 40.9 | 1189.2
15:50:37:febtest:INFO: 0-4 | XA-000-08-002-001-007-187-13 | 40.9 | 1189.2
15:50:38:febtest:INFO: 0-5 | XA-000-08-002-001-007-176-13 | 28.2 | 1224.5
15:50:38:febtest:INFO: 0-6 | XA-000-08-002-001-007-181-13 | 31.4 | 1218.6
15:50:38:febtest:INFO: 0-7 | XA-000-08-002-001-007-169-10 | 40.9 | 1177.4
15:50:38:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:50:42:ST3_smx:INFO: chip: 0-0 37.726682 C 1183.292940 mV
15:50:42:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:50:42:ST3_smx:INFO: Electrons
15:50:42:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:50:44:ST3_smx:INFO: ----> Checking Analog response
15:50:44:ST3_smx:INFO: ----> Checking broken channels
15:50:44:ST3_smx:INFO: Total # broken ch: 0
15:50:44:ST3_smx:INFO: List FAST: []
15:50:44:ST3_smx:INFO: List SLOW: []
15:50:44:ST3_smx:INFO: Holes
15:50:44:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:50:46:ST3_smx:INFO: ----> Checking Analog response
15:50:46:ST3_smx:INFO: ----> Checking broken channels
15:50:46:ST3_smx:INFO: Total # broken ch: 0
15:50:46:ST3_smx:INFO: List FAST: []
15:50:46:ST3_smx:INFO: List SLOW: []
15:50:46:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:50:46:febtest:INFO: 0-0 | XA-000-08-002-001-007-208-06 | 40.9 | 1183.3
15:50:47:febtest:INFO: 0-1 | XA-000-08-002-001-007-179-13 | 47.3 | 1171.5
15:50:47:febtest:INFO: 0-2 | XA-000-08-002-001-007-192-01 | 47.3 | 1177.4
15:50:47:febtest:INFO: 0-3 | XA-000-08-002-001-007-178-13 | 40.9 | 1189.2
15:50:47:febtest:INFO: 0-4 | XA-000-08-002-001-007-187-13 | 44.1 | 1183.3
15:50:48:febtest:INFO: 0-5 | XA-000-08-002-001-007-176-13 | 31.4 | 1224.5
15:50:48:febtest:INFO: 0-6 | XA-000-08-002-001-007-181-13 | 31.4 | 1218.6
15:50:48:febtest:INFO: 0-7 | XA-000-08-002-001-007-169-10 | 44.1 | 1177.4
15:50:48:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:50:52:ST3_smx:INFO: chip: 0-1 47.250730 C 1159.654860 mV
15:50:52:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:50:52:ST3_smx:INFO: Electrons
15:50:52:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:50:54:ST3_smx:INFO: ----> Checking Analog response
15:50:54:ST3_smx:INFO: ----> Checking broken channels
15:50:54:ST3_smx:INFO: Total # broken ch: 0
15:50:54:ST3_smx:INFO: List FAST: []
15:50:54:ST3_smx:INFO: List SLOW: []
15:50:54:ST3_smx:INFO: Holes
15:50:54:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:50:56:ST3_smx:INFO: ----> Checking Analog response
15:50:56:ST3_smx:INFO: ----> Checking broken channels
15:50:56:ST3_smx:INFO: Total # broken ch: 0
15:50:56:ST3_smx:INFO: List FAST: []
15:50:56:ST3_smx:INFO: List SLOW: []
15:50:56:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:50:57:febtest:INFO: 0-0 | XA-000-08-002-001-007-208-06 | 37.7 | 1183.3
15:50:57:febtest:INFO: 0-1 | XA-000-08-002-001-007-179-13 | 44.1 | 1159.7
15:50:57:febtest:INFO: 0-2 | XA-000-08-002-001-007-192-01 | 47.3 | 1177.4
15:50:57:febtest:INFO: 0-3 | XA-000-08-002-001-007-178-13 | 37.7 | 1189.2
15:50:57:febtest:INFO: 0-4 | XA-000-08-002-001-007-187-13 | 40.9 | 1189.2
15:50:58:febtest:INFO: 0-5 | XA-000-08-002-001-007-176-13 | 25.1 | 1224.5
15:50:58:febtest:INFO: 0-6 | XA-000-08-002-001-007-181-13 | 31.4 | 1218.6
15:50:58:febtest:INFO: 0-7 | XA-000-08-002-001-007-169-10 | 40.9 | 1177.4
15:50:59:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:51:02:ST3_smx:INFO: chip: 0-2 44.073563 C 1165.571835 mV
15:51:02:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:51:02:ST3_smx:INFO: Electrons
15:51:02:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:51:04:ST3_smx:INFO: ----> Checking Analog response
15:51:04:ST3_smx:INFO: ----> Checking broken channels
15:51:04:ST3_smx:INFO: Total # broken ch: 0
15:51:04:ST3_smx:INFO: List FAST: []
15:51:04:ST3_smx:INFO: List SLOW: []
15:51:04:ST3_smx:INFO: Holes
15:51:04:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:51:06:ST3_smx:INFO: ----> Checking Analog response
15:51:06:ST3_smx:INFO: ----> Checking broken channels
15:51:06:ST3_smx:INFO: Total # broken ch: 0
15:51:06:ST3_smx:INFO: List FAST: []
15:51:06:ST3_smx:INFO: List SLOW: []
15:51:06:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:51:07:febtest:INFO: 0-0 | XA-000-08-002-001-007-208-06 | 34.6 | 1183.3
15:51:07:febtest:INFO: 0-1 | XA-000-08-002-001-007-179-13 | 40.9 | 1159.7
15:51:07:febtest:INFO: 0-2 | XA-000-08-002-001-007-192-01 | 44.1 | 1159.7
15:51:07:febtest:INFO: 0-3 | XA-000-08-002-001-007-178-13 | 37.7 | 1189.2
15:51:07:febtest:INFO: 0-4 | XA-000-08-002-001-007-187-13 | 37.7 | 1189.2
15:51:08:febtest:INFO: 0-5 | XA-000-08-002-001-007-176-13 | 21.9 | 1224.5
15:51:08:febtest:INFO: 0-6 | XA-000-08-002-001-007-181-13 | 28.2 | 1218.6
15:51:08:febtest:INFO: 0-7 | XA-000-08-002-001-007-169-10 | 40.9 | 1177.4
15:51:08:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:51:12:ST3_smx:INFO: chip: 0-3 34.556970 C 1183.292940 mV
15:51:12:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:51:12:ST3_smx:INFO: Electrons
15:51:12:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:51:14:ST3_smx:INFO: ----> Checking Analog response
15:51:14:ST3_smx:INFO: ----> Checking broken channels
15:51:14:ST3_smx:INFO: Total # broken ch: 0
15:51:14:ST3_smx:INFO: List FAST: []
15:51:14:ST3_smx:INFO: List SLOW: []
15:51:14:ST3_smx:INFO: Holes
15:51:14:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:51:16:ST3_smx:INFO: ----> Checking Analog response
15:51:16:ST3_smx:INFO: ----> Checking broken channels
15:51:16:ST3_smx:INFO: Total # broken ch: 0
15:51:16:ST3_smx:INFO: List FAST: []
15:51:16:ST3_smx:INFO: List SLOW: []
15:51:16:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:51:17:febtest:INFO: 0-0 | XA-000-08-002-001-007-208-06 | 34.6 | 1183.3
15:51:17:febtest:INFO: 0-1 | XA-000-08-002-001-007-179-13 | 37.7 | 1159.7
15:51:17:febtest:INFO: 0-2 | XA-000-08-002-001-007-192-01 | 44.1 | 1159.7
15:51:17:febtest:INFO: 0-3 | XA-000-08-002-001-007-178-13 | 37.7 | 1177.4
15:51:18:febtest:INFO: 0-4 | XA-000-08-002-001-007-187-13 | 37.7 | 1183.3
15:51:18:febtest:INFO: 0-5 | XA-000-08-002-001-007-176-13 | 21.9 | 1218.6
15:51:18:febtest:INFO: 0-6 | XA-000-08-002-001-007-181-13 | 28.2 | 1218.6
15:51:18:febtest:INFO: 0-7 | XA-000-08-002-001-007-169-10 | 40.9 | 1177.4
15:51:19:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:51:22:ST3_smx:INFO: chip: 0-4 31.389742 C 1195.082160 mV
15:51:22:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:51:22:ST3_smx:INFO: Electrons
15:51:22:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:51:24:ST3_smx:INFO: ----> Checking Analog response
15:51:24:ST3_smx:INFO: ----> Checking broken channels
15:51:24:ST3_smx:INFO: Total # broken ch: 0
15:51:24:ST3_smx:INFO: List FAST: []
15:51:24:ST3_smx:INFO: List SLOW: []
15:51:24:ST3_smx:INFO: Holes
15:51:24:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:51:26:ST3_smx:INFO: ----> Checking Analog response
15:51:26:ST3_smx:INFO: ----> Checking broken channels
15:51:27:ST3_smx:INFO: Total # broken ch: 0
15:51:27:ST3_smx:INFO: List FAST: []
15:51:27:ST3_smx:INFO: List SLOW: []
15:51:27:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:51:27:febtest:INFO: 0-0 | XA-000-08-002-001-007-208-06 | 34.6 | 1183.3
15:51:27:febtest:INFO: 0-1 | XA-000-08-002-001-007-179-13 | 40.9 | 1153.7
15:51:27:febtest:INFO: 0-2 | XA-000-08-002-001-007-192-01 | 44.1 | 1159.7
15:51:27:febtest:INFO: 0-3 | XA-000-08-002-001-007-178-13 | 37.7 | 1177.4
15:51:28:febtest:INFO: 0-4 | XA-000-08-002-001-007-187-13 | 34.6 | 1189.2
15:51:28:febtest:INFO: 0-5 | XA-000-08-002-001-007-176-13 | 21.9 | 1218.6
15:51:28:febtest:INFO: 0-6 | XA-000-08-002-001-007-181-13 | 28.2 | 1218.6
15:51:28:febtest:INFO: 0-7 | XA-000-08-002-001-007-169-10 | 37.7 | 1177.4
15:51:29:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:51:32:ST3_smx:INFO: chip: 0-5 37.726682 C 1159.654860 mV
15:51:32:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:51:32:ST3_smx:INFO: Electrons
15:51:32:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:51:34:ST3_smx:INFO: ----> Checking Analog response
15:51:34:ST3_smx:INFO: ----> Checking broken channels
15:51:34:ST3_smx:INFO: Total # broken ch: 0
15:51:34:ST3_smx:INFO: List FAST: []
15:51:34:ST3_smx:INFO: List SLOW: []
15:51:34:ST3_smx:INFO: Holes
15:51:34:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:51:36:ST3_smx:INFO: ----> Checking Analog response
15:51:36:ST3_smx:INFO: ----> Checking broken channels
15:51:37:ST3_smx:INFO: Total # broken ch: 0
15:51:37:ST3_smx:INFO: List FAST: []
15:51:37:ST3_smx:INFO: List SLOW: []
15:51:37:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:51:37:febtest:INFO: 0-0 | XA-000-08-002-001-007-208-06 | 34.6 | 1183.3
15:51:37:febtest:INFO: 0-1 | XA-000-08-002-001-007-179-13 | 40.9 | 1153.7
15:51:37:febtest:INFO: 0-2 | XA-000-08-002-001-007-192-01 | 44.1 | 1159.7
15:51:38:febtest:INFO: 0-3 | XA-000-08-002-001-007-178-13 | 37.7 | 1171.5
15:51:38:febtest:INFO: 0-4 | XA-000-08-002-001-007-187-13 | 34.6 | 1189.2
15:51:38:febtest:INFO: 0-5 | XA-000-08-002-001-007-176-13 | 40.9 | 1153.7
15:51:38:febtest:INFO: 0-6 | XA-000-08-002-001-007-181-13 | 28.2 | 1212.7
15:51:39:febtest:INFO: 0-7 | XA-000-08-002-001-007-169-10 | 40.9 | 1177.4
15:51:39:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:51:42:ST3_smx:INFO: chip: 0-6 34.556970 C 1183.292940 mV
15:51:42:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:51:42:ST3_smx:INFO: Electrons
15:51:42:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:51:44:ST3_smx:INFO: ----> Checking Analog response
15:51:44:ST3_smx:INFO: ----> Checking broken channels
15:51:44:ST3_smx:INFO: Total # broken ch: 0
15:51:44:ST3_smx:INFO: List FAST: []
15:51:44:ST3_smx:INFO: List SLOW: []
15:51:44:ST3_smx:INFO: Holes
15:51:44:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:51:46:ST3_smx:INFO: ----> Checking Analog response
15:51:46:ST3_smx:INFO: ----> Checking broken channels
15:51:47:ST3_smx:INFO: Total # broken ch: 0
15:51:47:ST3_smx:INFO: List FAST: []
15:51:47:ST3_smx:INFO: List SLOW: []
15:51:47:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:51:47:febtest:INFO: 0-0 | XA-000-08-002-001-007-208-06 | 34.6 | 1177.4
15:51:47:febtest:INFO: 0-1 | XA-000-08-002-001-007-179-13 | 40.9 | 1153.7
15:51:47:febtest:INFO: 0-2 | XA-000-08-002-001-007-192-01 | 44.1 | 1159.7
15:51:48:febtest:INFO: 0-3 | XA-000-08-002-001-007-178-13 | 37.7 | 1177.4
15:51:48:febtest:INFO: 0-4 | XA-000-08-002-001-007-187-13 | 34.6 | 1189.2
15:51:48:febtest:INFO: 0-5 | XA-000-08-002-001-007-176-13 | 40.9 | 1153.7
15:51:48:febtest:INFO: 0-6 | XA-000-08-002-001-007-181-13 | 37.7 | 1177.4
15:51:49:febtest:INFO: 0-7 | XA-000-08-002-001-007-169-10 | 40.9 | 1171.5
15:51:49:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:51:53:ST3_smx:INFO: chip: 0-7 34.556970 C 1171.483840 mV
15:51:53:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:51:53:ST3_smx:INFO: Electrons
15:51:53:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:51:55:ST3_smx:INFO: ----> Checking Analog response
15:51:55:ST3_smx:INFO: ----> Checking broken channels
15:51:55:ST3_smx:INFO: Total # broken ch: 0
15:51:55:ST3_smx:INFO: List FAST: []
15:51:55:ST3_smx:INFO: List SLOW: []
15:51:55:ST3_smx:INFO: Holes
15:51:55:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:51:57:ST3_smx:INFO: ----> Checking Analog response
15:51:57:ST3_smx:INFO: ----> Checking broken channels
15:51:57:ST3_smx:INFO: Total # broken ch: 0
15:51:57:ST3_smx:INFO: List FAST: []
15:51:57:ST3_smx:INFO: List SLOW: []
15:51:57:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:51:57:febtest:INFO: 0-0 | XA-000-08-002-001-007-208-06 | 34.6 | 1177.4
15:51:57:febtest:INFO: 0-1 | XA-000-08-002-001-007-179-13 | 37.7 | 1153.7
15:51:58:febtest:INFO: 0-2 | XA-000-08-002-001-007-192-01 | 44.1 | 1159.7
15:51:58:febtest:INFO: 0-3 | XA-000-08-002-001-007-178-13 | 37.7 | 1171.5
15:51:58:febtest:INFO: 0-4 | XA-000-08-002-001-007-187-13 | 34.6 | 1189.2
15:51:58:febtest:INFO: 0-5 | XA-000-08-002-001-007-176-13 | 40.9 | 1153.7
15:51:58:febtest:INFO: 0-6 | XA-000-08-002-001-007-181-13 | 37.7 | 1177.4
15:51:59:febtest:INFO: 0-7 | XA-000-08-002-001-007-169-10 | 37.7 | 1171.5
############################################################
# S U M M A R Y #
############################################################
{'TEST_NAME': 'FEB-ASIC', 'TEST_DATE': '2023_08_02-15_50_24', 'OPERATOR': 'Oleksandr S.; Robert V.; ', 'PROJECT': 'Production', 'SITE': 'GSI', 'SETUP': 'GSI_TEST_SETUP_1', 'ASIC_ID': 'XA-000-08-002-001-007-169-10', 'FUSED_ID': 6359364699117615770, 'HW_ADDR': 7, 'VERS_NO': '2.2', 'CABLE_SET_ID': '', 'IC_TEMP': '0', 'VDDM': '0', 'AUX': '0', 'CSABIAS': '0', 'VDDM_INT': '0', 'ADC_Chi2': 0.0, 'ADC_NDF': 0, 'ADC_P0': 0.0, 'ADC_P1': 0.006824, 'ADC_P2': -2.485e-06, 'ADC_P0err': 0.001, 'ADC_P1err': 0.001, 'ADC_P2err': 1e-05, 'ADC_VREF_P': 58, 'ADC_VREF_N': 30, 'ADC_VREF_T': 128, 'ADC_VREF_TR': 122, 'THR2_GLB': 30, 'LOOP__PLS': 100, 'CALIB_PLS': 250, 'SnsLoop': 5, 'IFED': 31, 'CSA_BIAS': 15, 'CSA_Chi2': 0.0, 'CSA_NDF': 0, 'CSA_P0': 0.0, 'CSA_P1': 0.0, 'CSA_P2': 0.0, 'CSA_P0err': 0.0, 'CSA_P1err': 0.0, 'CSA_P2err': 0.0, 'CONF_FAIL_REG': 0, 'N_BROKEN_DISC': 0, 'N_BROKEN_FAST': '[]', 'N_BROKEN_SLOW': '[]', 'P_BROKEN_DISC': 0, 'P_BROKEN_FAST': '[]', 'P_BROKEN_SLOW': '[]', 'ASIC_QA_category': '', 'N_BROKEN_CABLE': 0, 'LIST_OF_BROKEN_CABLES': 0, 'VI_bInit': ['2.448', '1.5800', '1.846', '2.2930', '7.001', '1.5240', '7.001', '1.5240'], 'VI_aInit': ['2.450', '2.0230', '1.850', '1.4750', '7.000', '1.5410', '7.000', '1.5410'], 'VI_atEnd': ['0', '0', '0', '0', '0', '0'], 'AMP_CAL': 200, 'PlsLoop': 3, 'N_ANA_PRESENT': 'Analog response OK', 'N_DISC_FAIL_CH': 0, 'N_ANA_FAIL_CH': '0', 'P_ANA_PRESENT': 'Analog response OK', 'P_DISC_FAIL_CH': 0, 'P_ANA_FAIL_CH': '0'}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
15:52:03:ST3_Shared:INFO: /home/cbm/public_html/Production_LogDir//FEB/FEB_2008/B//TestDate_2023_08_02-15_50_24/