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FEB_2010 03.08.23 10:05:56
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09:52:59:ST3_hmp4040:INFO: HAMEG,HMP2030,017836163,HW50010002/SW2.30
09:52:59:febtest:INFO: FEB8.2 selected
09:52:59:febtest:INFO: FEB8.2 selected
10:05:41:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
10:05:41:ST3_Shared:INFO: --------------------------FEB-ASIC--------------------------
10:05:41:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
10:05:41:febtest:INFO: Tsting FEB with SN 2010
Traceback (most recent call last):
File "febtest.py", line 259, in DoFEB_AsicTest
if self.DoScanFEB8(reporter.out_dict):
File "febtest.py", line 212, in DoScanFEB8
if self.EMU.Scan_FEB8(reporter):
AttributeError: 'int' object has no attribute 'Scan_FEB8'
10:05:54:smx_tester:INFO: Setting Elink clock mode to 160 MHz
10:05:56:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
10:05:56:ST3_Shared:INFO: --------------------------FEB-ASIC--------------------------
10:05:56:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
10:05:56:febtest:INFO: Tsting FEB with SN 2010
10:05:57:smx_tester:INFO: Scanning setup
10:05:57:elinks:INFO: Disabling clock on downlink 0
10:05:57:elinks:INFO: Disabling clock on downlink 1
10:05:57:elinks:INFO: Disabling clock on downlink 2
10:05:57:elinks:INFO: Disabling clock on downlink 3
10:05:57:elinks:INFO: Disabling clock on downlink 4
10:05:57:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:05:57:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
10:05:57:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:05:57:elinks:INFO: Disabling clock on downlink 0
10:05:57:elinks:INFO: Disabling clock on downlink 1
10:05:57:elinks:INFO: Disabling clock on downlink 2
10:05:57:elinks:INFO: Disabling clock on downlink 3
10:05:57:elinks:INFO: Disabling clock on downlink 4
10:05:57:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:05:57:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
10:05:57:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:05:57:elinks:INFO: Disabling clock on downlink 0
10:05:57:elinks:INFO: Disabling clock on downlink 1
10:05:57:elinks:INFO: Disabling clock on downlink 2
10:05:57:elinks:INFO: Disabling clock on downlink 3
10:05:57:elinks:INFO: Disabling clock on downlink 4
10:05:57:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:05:57:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
10:05:58:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 16
10:05:58:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 17
10:05:58:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 18
10:05:58:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 19
10:05:58:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 20
10:05:58:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 21
10:05:58:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 22
10:05:58:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 23
10:05:58:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24
10:05:58:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25
10:05:58:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26
10:05:58:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27
10:05:58:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28
10:05:58:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29
10:05:58:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30
10:05:58:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31
10:05:58:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:05:58:elinks:INFO: Disabling clock on downlink 0
10:05:58:elinks:INFO: Disabling clock on downlink 1
10:05:58:elinks:INFO: Disabling clock on downlink 2
10:05:58:elinks:INFO: Disabling clock on downlink 3
10:05:58:elinks:INFO: Disabling clock on downlink 4
10:05:58:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:05:58:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
10:05:58:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:05:58:elinks:INFO: Disabling clock on downlink 0
10:05:58:elinks:INFO: Disabling clock on downlink 1
10:05:58:elinks:INFO: Disabling clock on downlink 2
10:05:58:elinks:INFO: Disabling clock on downlink 3
10:05:58:elinks:INFO: Disabling clock on downlink 4
10:05:58:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:05:58:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
10:05:58:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:05:58:setup_element:INFO: Scanning clock phase
10:05:58:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
10:05:58:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
10:05:58:setup_element:INFO: Clock phase scan results for group 0, downlink 2
10:05:58:setup_element:INFO: Eye window for uplink 16: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
10:05:58:setup_element:INFO: Eye window for uplink 17: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
10:05:58:setup_element:INFO: Eye window for uplink 18: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
10:05:58:setup_element:INFO: Eye window for uplink 19: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
10:05:58:setup_element:INFO: Eye window for uplink 20: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
10:05:58:setup_element:INFO: Eye window for uplink 21: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
10:05:58:setup_element:INFO: Eye window for uplink 22: _____________________________________________________________________XXXXXXXXX__
Clock Delay: 33
10:05:58:setup_element:INFO: Eye window for uplink 23: _____________________________________________________________________XXXXXXXXX__
Clock Delay: 33
10:05:58:setup_element:INFO: Eye window for uplink 24: ______________________________________________________________________XXXXXXX___
Clock Delay: 33
10:05:58:setup_element:INFO: Eye window for uplink 25: ______________________________________________________________________XXXXXXX___
Clock Delay: 33
10:05:58:setup_element:INFO: Eye window for uplink 26: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
10:05:58:setup_element:INFO: Eye window for uplink 27: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
10:05:58:setup_element:INFO: Eye window for uplink 28: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
10:05:58:setup_element:INFO: Eye window for uplink 29: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
10:05:58:setup_element:INFO: Eye window for uplink 30: ________________________________________________________________________XXXXXXXX
Clock Delay: 35
10:05:58:setup_element:INFO: Eye window for uplink 31: ________________________________________________________________________XXXXXXXX
Clock Delay: 35
10:05:58:setup_element:INFO: Setting the clock phase to 34 for group 0, downlink 2
10:05:58:setup_element:INFO: Scanning data phases
10:05:58:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
10:05:58:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
10:06:04:setup_element:INFO: Data phase scan results for group 0, downlink 2
10:06:04:setup_element:INFO: Eye window for uplink 16: ____________________________________XXX_
Data delay found: 17
10:06:04:setup_element:INFO: Eye window for uplink 17: _______________________________XXXXX____
Data delay found: 13
10:06:04:setup_element:INFO: Eye window for uplink 18: X_________________________________XXXXX_
Data delay found: 17
10:06:04:setup_element:INFO: Eye window for uplink 19: ________________________________XXXX____
Data delay found: 13
10:06:04:setup_element:INFO: Eye window for uplink 20: ____________________________________XXX_
Data delay found: 17
10:06:04:setup_element:INFO: Eye window for uplink 21: __________________________________XXXXX_
Data delay found: 16
10:06:04:setup_element:INFO: Eye window for uplink 22: __________________________________XXXX__
Data delay found: 15
10:06:04:setup_element:INFO: Eye window for uplink 23: ________________________________XXXX____
Data delay found: 13
10:06:04:setup_element:INFO: Eye window for uplink 24: _____XXXX_______________________________
Data delay found: 26
10:06:04:setup_element:INFO: Eye window for uplink 25: _______XXXXX____________________________
Data delay found: 29
10:06:04:setup_element:INFO: Eye window for uplink 26: _____XXXXX______________________________
Data delay found: 27
10:06:04:setup_element:INFO: Eye window for uplink 27: _________XXXXX__________________________
Data delay found: 31
10:06:04:setup_element:INFO: Eye window for uplink 28: ___________XXXXX________________________
Data delay found: 33
10:06:04:setup_element:INFO: Eye window for uplink 29: ____________XXXXX_______________________
Data delay found: 34
10:06:04:setup_element:INFO: Eye window for uplink 30: ______________XXXXXX____________________
Data delay found: 36
10:06:04:setup_element:INFO: Eye window for uplink 31: ____________XXXXXX______________________
Data delay found: 34
10:06:04:setup_element:INFO: Setting the data phase to 17 for uplink 16
10:06:04:setup_element:INFO: Setting the data phase to 13 for uplink 17
10:06:04:setup_element:INFO: Setting the data phase to 17 for uplink 18
10:06:04:setup_element:INFO: Setting the data phase to 13 for uplink 19
10:06:04:setup_element:INFO: Setting the data phase to 17 for uplink 20
10:06:04:setup_element:INFO: Setting the data phase to 16 for uplink 21
10:06:04:setup_element:INFO: Setting the data phase to 15 for uplink 22
10:06:04:setup_element:INFO: Setting the data phase to 13 for uplink 23
10:06:04:setup_element:INFO: Setting the data phase to 26 for uplink 24
10:06:04:setup_element:INFO: Setting the data phase to 29 for uplink 25
10:06:04:setup_element:INFO: Setting the data phase to 27 for uplink 26
10:06:04:setup_element:INFO: Setting the data phase to 31 for uplink 27
10:06:04:setup_element:INFO: Setting the data phase to 33 for uplink 28
10:06:04:setup_element:INFO: Setting the data phase to 34 for uplink 29
10:06:04:setup_element:INFO: Setting the data phase to 36 for uplink 30
10:06:04:setup_element:INFO: Setting the data phase to 34 for uplink 31
10:06:04:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 34
Window Length: 69
Eye Windows:
Uplink 16: _____________________________________________________________________XXXXXXXX___
Uplink 17: _____________________________________________________________________XXXXXXXX___
Uplink 18: ______________________________________________________________________XXXXXXXX__
Uplink 19: ______________________________________________________________________XXXXXXXX__
Uplink 20: ______________________________________________________________________XXXXXXXX__
Uplink 21: ______________________________________________________________________XXXXXXXX__
Uplink 22: _____________________________________________________________________XXXXXXXXX__
Uplink 23: _____________________________________________________________________XXXXXXXXX__
Uplink 24: ______________________________________________________________________XXXXXXX___
Uplink 25: ______________________________________________________________________XXXXXXX___
Uplink 26: _____________________________________________________________________XXXXXXXX___
Uplink 27: _____________________________________________________________________XXXXXXXX___
Uplink 28: _______________________________________________________________________XXXXXXX__
Uplink 29: _______________________________________________________________________XXXXXXX__
Uplink 30: ________________________________________________________________________XXXXXXXX
Uplink 31: ________________________________________________________________________XXXXXXXX
Data phase characteristics:
Uplink 16:
Optimal Phase: 17
Window Length: 37
Eye Window: ____________________________________XXX_
Uplink 17:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 18:
Optimal Phase: 17
Window Length: 33
Eye Window: X_________________________________XXXXX_
Uplink 19:
Optimal Phase: 13
Window Length: 36
Eye Window: ________________________________XXXX____
Uplink 20:
Optimal Phase: 17
Window Length: 37
Eye Window: ____________________________________XXX_
Uplink 21:
Optimal Phase: 16
Window Length: 35
Eye Window: __________________________________XXXXX_
Uplink 22:
Optimal Phase: 15
Window Length: 36
Eye Window: __________________________________XXXX__
Uplink 23:
Optimal Phase: 13
Window Length: 36
Eye Window: ________________________________XXXX____
Uplink 24:
Optimal Phase: 26
Window Length: 36
Eye Window: _____XXXX_______________________________
Uplink 25:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 26:
Optimal Phase: 27
Window Length: 35
Eye Window: _____XXXXX______________________________
Uplink 27:
Optimal Phase: 31
Window Length: 35
Eye Window: _________XXXXX__________________________
Uplink 28:
Optimal Phase: 33
Window Length: 35
Eye Window: ___________XXXXX________________________
Uplink 29:
Optimal Phase: 34
Window Length: 35
Eye Window: ____________XXXXX_______________________
Uplink 30:
Optimal Phase: 36
Window Length: 34
Eye Window: ______________XXXXXX____________________
Uplink 31:
Optimal Phase: 34
Window Length: 34
Eye Window: ____________XXXXXX______________________
]
10:06:04:setup_element:INFO: Beginning SMX ASICs map scan
10:06:04:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
10:06:04:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
10:06:04:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
10:06:04:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
10:06:04:uplink:INFO: Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
10:06:04:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 23
10:06:04:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 22
10:06:04:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 30
10:06:04:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 31
10:06:05:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 21
10:06:05:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 20
10:06:05:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28
10:06:05:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 29
10:06:05:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 19
10:06:05:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 18
10:06:05:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26
10:06:05:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 27
10:06:05:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 17
10:06:05:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 16
10:06:05:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 24
10:06:05:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 25
10:06:07:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 23), (1, 22)
ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
ASIC address 0x2: (ASIC uplink, uplink): (0, 21), (1, 20)
ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
ASIC address 0x4: (ASIC uplink, uplink): (0, 19), (1, 18)
ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
ASIC address 0x6: (ASIC uplink, uplink): (0, 17), (1, 16)
ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
Clock Phase Characteristic:
Optimal Phase: 34
Window Length: 69
Eye Windows:
Uplink 16: _____________________________________________________________________XXXXXXXX___
Uplink 17: _____________________________________________________________________XXXXXXXX___
Uplink 18: ______________________________________________________________________XXXXXXXX__
Uplink 19: ______________________________________________________________________XXXXXXXX__
Uplink 20: ______________________________________________________________________XXXXXXXX__
Uplink 21: ______________________________________________________________________XXXXXXXX__
Uplink 22: _____________________________________________________________________XXXXXXXXX__
Uplink 23: _____________________________________________________________________XXXXXXXXX__
Uplink 24: ______________________________________________________________________XXXXXXX___
Uplink 25: ______________________________________________________________________XXXXXXX___
Uplink 26: _____________________________________________________________________XXXXXXXX___
Uplink 27: _____________________________________________________________________XXXXXXXX___
Uplink 28: _______________________________________________________________________XXXXXXX__
Uplink 29: _______________________________________________________________________XXXXXXX__
Uplink 30: ________________________________________________________________________XXXXXXXX
Uplink 31: ________________________________________________________________________XXXXXXXX
Data phase characteristics:
Uplink 16:
Optimal Phase: 17
Window Length: 37
Eye Window: ____________________________________XXX_
Uplink 17:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 18:
Optimal Phase: 17
Window Length: 33
Eye Window: X_________________________________XXXXX_
Uplink 19:
Optimal Phase: 13
Window Length: 36
Eye Window: ________________________________XXXX____
Uplink 20:
Optimal Phase: 17
Window Length: 37
Eye Window: ____________________________________XXX_
Uplink 21:
Optimal Phase: 16
Window Length: 35
Eye Window: __________________________________XXXXX_
Uplink 22:
Optimal Phase: 15
Window Length: 36
Eye Window: __________________________________XXXX__
Uplink 23:
Optimal Phase: 13
Window Length: 36
Eye Window: ________________________________XXXX____
Uplink 24:
Optimal Phase: 26
Window Length: 36
Eye Window: _____XXXX_______________________________
Uplink 25:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 26:
Optimal Phase: 27
Window Length: 35
Eye Window: _____XXXXX______________________________
Uplink 27:
Optimal Phase: 31
Window Length: 35
Eye Window: _________XXXXX__________________________
Uplink 28:
Optimal Phase: 33
Window Length: 35
Eye Window: ___________XXXXX________________________
Uplink 29:
Optimal Phase: 34
Window Length: 35
Eye Window: ____________XXXXX_______________________
Uplink 30:
Optimal Phase: 36
Window Length: 34
Eye Window: ______________XXXXXX____________________
Uplink 31:
Optimal Phase: 34
Window Length: 34
Eye Window: ____________XXXXXX______________________
10:06:07:setup_element:INFO: Performing Elink synchronization
10:06:07:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
10:06:07:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
10:06:07:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
10:06:07:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
10:06:07:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2
10:06:07:uplink:INFO: Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
10:06:07:ST3_emu:INFO: Number of chips: 8
10:06:07:ST3_emu:INFO: Chip address: 0x0
10:06:07:ST3_emu:INFO: Chip address: 0x1
10:06:07:ST3_emu:INFO: Chip address: 0x2
10:06:07:ST3_emu:INFO: Chip address: 0x3
10:06:07:ST3_emu:INFO: Chip address: 0x4
10:06:07:ST3_emu:INFO: Chip address: 0x5
10:06:07:ST3_emu:INFO: Chip address: 0x6
10:06:07:ST3_emu:INFO: Chip address: 0x7
10:06:08:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:06:08:febtest:INFO: 0-0 | XA-000-08-002-001-007-210-06 | 56.8 | 1135.9
10:06:08:febtest:INFO: 0-1 | XA-000-08-002-001-007-188-13 | 56.8 | 1141.9
10:06:09:febtest:INFO: 0-2 | XA-000-08-002-001-007-202-01 | 37.7 | 1206.9
10:06:09:febtest:INFO: 0-3 | XA-000-08-002-001-007-197-01 | 44.1 | 1201.0
10:06:09:febtest:INFO: 0-4 | XA-000-08-002-001-007-190-13 | 47.3 | 1165.6
10:06:09:febtest:INFO: 0-5 | XA-000-08-002-001-007-209-06 | 56.8 | 1130.0
10:06:10:febtest:INFO: 0-6 | XA-000-08-002-001-007-185-13 | 37.7 | 1195.1
10:06:10:febtest:INFO: 0-7 | XA-000-08-002-001-007-183-13 | 37.7 | 1189.2
10:06:10:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
10:06:14:ST3_smx:INFO: chip: 0-0 50.430383 C 1153.732915 mV
10:06:14:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
10:06:14:ST3_smx:INFO: Electrons
10:06:14:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
10:06:16:ST3_smx:INFO: ----> Checking Analog response
10:06:16:ST3_smx:INFO: ----> Checking broken channels
10:06:16:ST3_smx:INFO: Total # broken ch: 0
10:06:16:ST3_smx:INFO: List FAST: []
10:06:16:ST3_smx:INFO: List SLOW: []
10:06:16:ST3_smx:INFO: Holes
10:06:16:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
10:06:18:ST3_smx:INFO: ----> Checking Analog response
10:06:18:ST3_smx:INFO: ----> Checking broken channels
10:06:19:ST3_smx:INFO: Total # broken ch: 0
10:06:19:ST3_smx:INFO: List FAST: []
10:06:19:ST3_smx:INFO: List SLOW: []
10:06:19:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:06:19:febtest:INFO: 0-0 | XA-000-08-002-001-007-210-06 | 50.4 | 1153.7
10:06:19:febtest:INFO: 0-1 | XA-000-08-002-001-007-188-13 | 56.8 | 1141.9
10:06:19:febtest:INFO: 0-2 | XA-000-08-002-001-007-202-01 | 34.6 | 1206.9
10:06:20:febtest:INFO: 0-3 | XA-000-08-002-001-007-197-01 | 44.1 | 1195.1
10:06:20:febtest:INFO: 0-4 | XA-000-08-002-001-007-190-13 | 47.3 | 1165.6
10:06:20:febtest:INFO: 0-5 | XA-000-08-002-001-007-209-06 | 56.8 | 1130.0
10:06:20:febtest:INFO: 0-6 | XA-000-08-002-001-007-185-13 | 34.6 | 1195.1
10:06:20:febtest:INFO: 0-7 | XA-000-08-002-001-007-183-13 | 37.7 | 1189.2
10:06:21:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
10:06:25:ST3_smx:INFO: chip: 0-1 50.430383 C 1147.806000 mV
10:06:25:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
10:06:25:ST3_smx:INFO: Electrons
10:06:25:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
10:06:27:ST3_smx:INFO: ----> Checking Analog response
10:06:27:ST3_smx:INFO: ----> Checking broken channels
10:06:27:ST3_smx:INFO: Total # broken ch: 0
10:06:27:ST3_smx:INFO: List FAST: []
10:06:27:ST3_smx:INFO: List SLOW: []
10:06:27:ST3_smx:INFO: Holes
10:06:27:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
10:06:29:ST3_smx:INFO: ----> Checking Analog response
10:06:29:ST3_smx:INFO: ----> Checking broken channels
10:06:29:ST3_smx:INFO: Total # broken ch: 0
10:06:29:ST3_smx:INFO: List FAST: []
10:06:29:ST3_smx:INFO: List SLOW: []
10:06:29:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:06:30:febtest:INFO: 0-0 | XA-000-08-002-001-007-210-06 | 50.4 | 1153.7
10:06:30:febtest:INFO: 0-1 | XA-000-08-002-001-007-188-13 | 53.6 | 1141.9
10:06:30:febtest:INFO: 0-2 | XA-000-08-002-001-007-202-01 | 37.7 | 1206.9
10:06:30:febtest:INFO: 0-3 | XA-000-08-002-001-007-197-01 | 44.1 | 1195.1
10:06:30:febtest:INFO: 0-4 | XA-000-08-002-001-007-190-13 | 47.3 | 1165.6
10:06:31:febtest:INFO: 0-5 | XA-000-08-002-001-007-209-06 | 56.8 | 1130.0
10:06:31:febtest:INFO: 0-6 | XA-000-08-002-001-007-185-13 | 34.6 | 1195.1
10:06:31:febtest:INFO: 0-7 | XA-000-08-002-001-007-183-13 | 37.7 | 1189.2
10:06:31:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
10:06:35:ST3_smx:INFO: chip: 0-2 47.250730 C 1147.806000 mV
10:06:35:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
10:06:36:ST3_smx:INFO: Electrons
10:06:36:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
10:06:38:ST3_smx:INFO: ----> Checking Analog response
10:06:38:ST3_smx:INFO: ----> Checking broken channels
10:06:38:ST3_smx:INFO: Total # broken ch: 0
10:06:38:ST3_smx:INFO: List FAST: []
10:06:38:ST3_smx:INFO: List SLOW: []
10:06:38:ST3_smx:INFO: Holes
10:06:38:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
10:06:40:ST3_smx:INFO: ----> Checking Analog response
10:06:40:ST3_smx:INFO: ----> Checking broken channels
10:06:40:ST3_smx:INFO: Total # broken ch: 0
10:06:40:ST3_smx:INFO: List FAST: []
10:06:40:ST3_smx:INFO: List SLOW: []
10:06:40:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:06:40:febtest:INFO: 0-0 | XA-000-08-002-001-007-210-06 | 53.6 | 1147.8
10:06:41:febtest:INFO: 0-1 | XA-000-08-002-001-007-188-13 | 53.6 | 1141.9
10:06:41:febtest:INFO: 0-2 | XA-000-08-002-001-007-202-01 | 50.4 | 1147.8
10:06:41:febtest:INFO: 0-3 | XA-000-08-002-001-007-197-01 | 44.1 | 1195.1
10:06:41:febtest:INFO: 0-4 | XA-000-08-002-001-007-190-13 | 47.3 | 1165.6
10:06:42:febtest:INFO: 0-5 | XA-000-08-002-001-007-209-06 | 56.8 | 1130.0
10:06:42:febtest:INFO: 0-6 | XA-000-08-002-001-007-185-13 | 34.6 | 1195.1
10:06:42:febtest:INFO: 0-7 | XA-000-08-002-001-007-183-13 | 37.7 | 1189.2
10:06:42:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
10:06:46:ST3_smx:INFO: chip: 0-3 50.430383 C 1165.571835 mV
10:06:46:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
10:06:46:ST3_smx:INFO: Electrons
10:06:46:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
10:06:49:ST3_smx:INFO: ----> Checking Analog response
10:06:49:ST3_smx:INFO: ----> Checking broken channels
10:06:49:ST3_smx:INFO: Total # broken ch: 0
10:06:49:ST3_smx:INFO: List FAST: []
10:06:49:ST3_smx:INFO: List SLOW: []
10:06:49:ST3_smx:INFO: Holes
10:06:49:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
10:06:51:ST3_smx:INFO: ----> Checking Analog response
10:06:51:ST3_smx:INFO: ----> Checking broken channels
10:06:51:ST3_smx:INFO: Total # broken ch: 0
10:06:51:ST3_smx:INFO: List FAST: []
10:06:51:ST3_smx:INFO: List SLOW: []
10:06:51:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:06:52:febtest:INFO: 0-0 | XA-000-08-002-001-007-210-06 | 53.6 | 1147.8
10:06:52:febtest:INFO: 0-1 | XA-000-08-002-001-007-188-13 | 56.8 | 1141.9
10:06:52:febtest:INFO: 0-2 | XA-000-08-002-001-007-202-01 | 50.4 | 1147.8
10:06:52:febtest:INFO: 0-3 | XA-000-08-002-001-007-197-01 | 53.6 | 1159.7
10:06:52:febtest:INFO: 0-4 | XA-000-08-002-001-007-190-13 | 50.4 | 1165.6
10:06:53:febtest:INFO: 0-5 | XA-000-08-002-001-007-209-06 | 60.0 | 1130.0
10:06:53:febtest:INFO: 0-6 | XA-000-08-002-001-007-185-13 | 34.6 | 1195.1
10:06:53:febtest:INFO: 0-7 | XA-000-08-002-001-007-183-13 | 40.9 | 1183.3
10:06:53:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
10:06:57:ST3_smx:INFO: chip: 0-4 44.073563 C 1165.571835 mV
10:06:57:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
10:06:57:ST3_smx:INFO: Electrons
10:06:57:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
10:06:59:ST3_smx:INFO: ----> Checking Analog response
10:06:59:ST3_smx:INFO: ----> Checking broken channels
10:07:00:ST3_smx:INFO: Total # broken ch: 0
10:07:00:ST3_smx:INFO: List FAST: []
10:07:00:ST3_smx:INFO: List SLOW: []
10:07:00:ST3_smx:INFO: Holes
10:07:00:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
10:07:02:ST3_smx:INFO: ----> Checking Analog response
10:07:02:ST3_smx:INFO: ----> Checking broken channels
10:07:02:ST3_smx:INFO: Total # broken ch: 0
10:07:02:ST3_smx:INFO: List FAST: []
10:07:02:ST3_smx:INFO: List SLOW: []
10:07:02:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:07:02:febtest:INFO: 0-0 | XA-000-08-002-001-007-210-06 | 53.6 | 1147.8
10:07:02:febtest:INFO: 0-1 | XA-000-08-002-001-007-188-13 | 56.8 | 1141.9
10:07:03:febtest:INFO: 0-2 | XA-000-08-002-001-007-202-01 | 50.4 | 1147.8
10:07:03:febtest:INFO: 0-3 | XA-000-08-002-001-007-197-01 | 56.8 | 1159.7
10:07:03:febtest:INFO: 0-4 | XA-000-08-002-001-007-190-13 | 47.3 | 1165.6
10:07:03:febtest:INFO: 0-5 | XA-000-08-002-001-007-209-06 | 60.0 | 1130.0
10:07:04:febtest:INFO: 0-6 | XA-000-08-002-001-007-185-13 | 34.6 | 1189.2
10:07:04:febtest:INFO: 0-7 | XA-000-08-002-001-007-183-13 | 40.9 | 1183.3
10:07:04:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
10:07:08:ST3_smx:INFO: chip: 0-5 56.797143 C 1124.048640 mV
10:07:08:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
10:07:08:ST3_smx:INFO: Electrons
10:07:08:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
10:07:10:ST3_smx:INFO: ----> Checking Analog response
10:07:10:ST3_smx:INFO: ----> Checking broken channels
10:07:10:ST3_smx:INFO: Total # broken ch: 0
10:07:10:ST3_smx:INFO: List FAST: []
10:07:10:ST3_smx:INFO: List SLOW: []
10:07:10:ST3_smx:INFO: Holes
10:07:10:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
10:07:12:ST3_smx:INFO: ----> Checking Analog response
10:07:12:ST3_smx:INFO: ----> Checking broken channels
10:07:13:ST3_smx:INFO: Total # broken ch: 0
10:07:13:ST3_smx:INFO: List FAST: []
10:07:13:ST3_smx:INFO: List SLOW: []
10:07:13:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:07:13:febtest:INFO: 0-0 | XA-000-08-002-001-007-210-06 | 53.6 | 1147.8
10:07:13:febtest:INFO: 0-1 | XA-000-08-002-001-007-188-13 | 56.8 | 1135.9
10:07:13:febtest:INFO: 0-2 | XA-000-08-002-001-007-202-01 | 53.6 | 1141.9
10:07:14:febtest:INFO: 0-3 | XA-000-08-002-001-007-197-01 | 56.8 | 1153.7
10:07:14:febtest:INFO: 0-4 | XA-000-08-002-001-007-190-13 | 47.3 | 1165.6
10:07:14:febtest:INFO: 0-5 | XA-000-08-002-001-007-209-06 | 60.0 | 1118.1
10:07:14:febtest:INFO: 0-6 | XA-000-08-002-001-007-185-13 | 37.7 | 1189.2
10:07:14:febtest:INFO: 0-7 | XA-000-08-002-001-007-183-13 | 40.9 | 1183.3
10:07:15:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
10:07:19:ST3_smx:INFO: chip: 0-6 47.250730 C 1147.806000 mV
10:07:19:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
10:07:19:ST3_smx:INFO: Electrons
10:07:19:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
10:07:21:ST3_smx:INFO: ----> Checking Analog response
10:07:21:ST3_smx:INFO: ----> Checking broken channels
10:07:21:ST3_smx:INFO: Total # broken ch: 0
10:07:21:ST3_smx:INFO: List FAST: []
10:07:21:ST3_smx:INFO: List SLOW: []
10:07:21:ST3_smx:INFO: Holes
10:07:21:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
10:07:23:ST3_smx:INFO: ----> Checking Analog response
10:07:23:ST3_smx:INFO: ----> Checking broken channels
10:07:23:ST3_smx:INFO: Total # broken ch: 0
10:07:23:ST3_smx:INFO: List FAST: []
10:07:23:ST3_smx:INFO: List SLOW: []
10:07:23:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:07:24:febtest:INFO: 0-0 | XA-000-08-002-001-007-210-06 | 56.8 | 1141.9
10:07:24:febtest:INFO: 0-1 | XA-000-08-002-001-007-188-13 | 56.8 | 1135.9
10:07:24:febtest:INFO: 0-2 | XA-000-08-002-001-007-202-01 | 53.6 | 1141.9
10:07:24:febtest:INFO: 0-3 | XA-000-08-002-001-007-197-01 | 56.8 | 1153.7
10:07:25:febtest:INFO: 0-4 | XA-000-08-002-001-007-190-13 | 47.3 | 1165.6
10:07:25:febtest:INFO: 0-5 | XA-000-08-002-001-007-209-06 | 60.0 | 1118.1
10:07:25:febtest:INFO: 0-6 | XA-000-08-002-001-007-185-13 | 47.3 | 1141.9
10:07:25:febtest:INFO: 0-7 | XA-000-08-002-001-007-183-13 | 40.9 | 1183.3
10:07:25:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
10:07:29:ST3_smx:INFO: chip: 0-7 47.250730 C 1141.874115 mV
10:07:29:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
10:07:29:ST3_smx:INFO: Electrons
10:07:29:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
10:07:31:ST3_smx:INFO: ----> Checking Analog response
10:07:31:ST3_smx:INFO: ----> Checking broken channels
10:07:32:ST3_smx:INFO: Total # broken ch: 0
10:07:32:ST3_smx:INFO: List FAST: []
10:07:32:ST3_smx:INFO: List SLOW: []
10:07:32:ST3_smx:INFO: Holes
10:07:32:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
10:07:34:ST3_smx:INFO: ----> Checking Analog response
10:07:34:ST3_smx:INFO: ----> Checking broken channels
10:07:34:ST3_smx:INFO: Total # broken ch: 0
10:07:34:ST3_smx:INFO: List FAST: []
10:07:34:ST3_smx:INFO: List SLOW: []
10:07:34:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:07:34:febtest:INFO: 0-0 | XA-000-08-002-001-007-210-06 | 56.8 | 1141.9
10:07:34:febtest:INFO: 0-1 | XA-000-08-002-001-007-188-13 | 60.0 | 1135.9
10:07:35:febtest:INFO: 0-2 | XA-000-08-002-001-007-202-01 | 53.6 | 1141.9
10:07:35:febtest:INFO: 0-3 | XA-000-08-002-001-007-197-01 | 56.8 | 1153.7
10:07:35:febtest:INFO: 0-4 | XA-000-08-002-001-007-190-13 | 47.3 | 1165.6
10:07:35:febtest:INFO: 0-5 | XA-000-08-002-001-007-209-06 | 60.0 | 1118.1
10:07:36:febtest:INFO: 0-6 | XA-000-08-002-001-007-185-13 | 47.3 | 1141.9
10:07:36:febtest:INFO: 0-7 | XA-000-08-002-001-007-183-13 | 50.4 | 1141.9
############################################################
# S U M M A R Y #
############################################################
{'TEST_NAME': 'FEB-ASIC', 'TEST_DATE': '2023_08_03-10_05_56', 'OPERATOR': 'Alois Alzheimer', 'PROJECT': 'Production', 'SITE': 'GSI', 'SETUP': 'GSI_TEST_SETUP_1', 'ASIC_ID': 'XA-000-08-002-001-007-183-13', 'FUSED_ID': 6359364699117615997, 'HW_ADDR': 7, 'VERS_NO': '2.2', 'CABLE_SET_ID': '', 'IC_TEMP': '0', 'VDDM': '0', 'AUX': '0', 'CSABIAS': '0', 'VDDM_INT': '0', 'ADC_Chi2': 0.0, 'ADC_NDF': 0, 'ADC_P0': 0.0, 'ADC_P1': 0.006824, 'ADC_P2': -2.485e-06, 'ADC_P0err': 0.001, 'ADC_P1err': 0.001, 'ADC_P2err': 1e-05, 'ADC_VREF_P': 58, 'ADC_VREF_N': 30, 'ADC_VREF_T': 128, 'ADC_VREF_TR': 122, 'THR2_GLB': 30, 'LOOP__PLS': 100, 'CALIB_PLS': 250, 'SnsLoop': 5, 'IFED': 31, 'CSA_BIAS': 15, 'CSA_Chi2': 0.0, 'CSA_NDF': 0, 'CSA_P0': 0.0, 'CSA_P1': 0.0, 'CSA_P2': 0.0, 'CSA_P0err': 0.0, 'CSA_P1err': 0.0, 'CSA_P2err': 0.0, 'CONF_FAIL_REG': 0, 'N_BROKEN_DISC': 0, 'N_BROKEN_FAST': '[]', 'N_BROKEN_SLOW': '[]', 'P_BROKEN_DISC': 0, 'P_BROKEN_FAST': '[]', 'P_BROKEN_SLOW': '[]', 'ASIC_QA_category': '', 'N_BROKEN_CABLE': 0, 'LIST_OF_BROKEN_CABLES': 0, 'VI_bInit': ['2.450', '1.6510', '1.847', '2.7950', '7.000', '1.5230', '7.000', '1.5230'], 'VI_aInit': ['0', '0', '0', '0', '0', '0'], 'VI_atEnd': ['0', '0', '0', '0', '0', '0'], 'AMP_CAL': 200, 'PlsLoop': 3, 'N_ANA_PRESENT': 'Analog response OK', 'N_DISC_FAIL_CH': 0, 'N_ANA_FAIL_CH': '0', 'P_ANA_PRESENT': 'Analog response OK', 'P_DISC_FAIL_CH': 0, 'P_ANA_FAIL_CH': '0'}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
10:07:36:ST3_Shared:INFO: Listo of operators:Robert V.;
10:07:36:ST3_Shared:INFO: Listo of operators:Alois Alzheimer
10:07:47:ST3_Shared:INFO: Listo of operators:Robert V.;
10:08:10:ST3_Shared:INFO: /home/cbm/public_html/Production_LogDir//FEB/FEB_2010/B//TestDate_2023_08_03-10_05_56/