Go Back
FEB_2012 28.11.23 10:51:40
TextEdit.txt
10:51:15:febtest:INFO: FEB 8-2 B @ GSI
10:51:27:smx_tester:INFO: Setting Elink clock mode to 160 MHz
10:51:35:ST3_Shared:INFO: Listo of operators:Oleksandr S.; Irakli K.;
10:51:36:ST3_Shared:INFO: Listo of operators:Irakli K.;
10:51:40:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
10:51:40:ST3_Shared:INFO: --------------------------FEB-ASIC--------------------------
10:51:40:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
10:51:41:febtest:INFO: Tsting FEB with SN 2012
10:51:42:smx_tester:INFO: Scanning setup
10:51:42:elinks:INFO: Disabling clock on downlink 0
10:51:42:elinks:INFO: Disabling clock on downlink 1
10:51:42:elinks:INFO: Disabling clock on downlink 2
10:51:42:elinks:INFO: Disabling clock on downlink 3
10:51:42:elinks:INFO: Disabling clock on downlink 4
10:51:42:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:51:42:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
10:51:42:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:51:42:elinks:INFO: Disabling clock on downlink 0
10:51:42:elinks:INFO: Disabling clock on downlink 1
10:51:42:elinks:INFO: Disabling clock on downlink 2
10:51:42:elinks:INFO: Disabling clock on downlink 3
10:51:42:elinks:INFO: Disabling clock on downlink 4
10:51:42:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:51:42:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
10:51:42:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:51:42:elinks:INFO: Disabling clock on downlink 0
10:51:42:elinks:INFO: Disabling clock on downlink 1
10:51:42:elinks:INFO: Disabling clock on downlink 2
10:51:42:elinks:INFO: Disabling clock on downlink 3
10:51:42:elinks:INFO: Disabling clock on downlink 4
10:51:42:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:51:42:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
10:51:42:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 16
10:51:42:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 17
10:51:42:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 18
10:51:42:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 19
10:51:42:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 20
10:51:42:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 21
10:51:43:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 22
10:51:43:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 23
10:51:43:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24
10:51:43:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25
10:51:43:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26
10:51:43:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27
10:51:43:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28
10:51:43:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29
10:51:43:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30
10:51:43:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31
10:51:43:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:51:43:elinks:INFO: Disabling clock on downlink 0
10:51:43:elinks:INFO: Disabling clock on downlink 1
10:51:43:elinks:INFO: Disabling clock on downlink 2
10:51:43:elinks:INFO: Disabling clock on downlink 3
10:51:43:elinks:INFO: Disabling clock on downlink 4
10:51:43:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:51:43:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
10:51:43:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:51:43:elinks:INFO: Disabling clock on downlink 0
10:51:43:elinks:INFO: Disabling clock on downlink 1
10:51:43:elinks:INFO: Disabling clock on downlink 2
10:51:43:elinks:INFO: Disabling clock on downlink 3
10:51:43:elinks:INFO: Disabling clock on downlink 4
10:51:43:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:51:43:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
10:51:43:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:51:43:setup_element:INFO: Scanning clock phase
10:51:43:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
10:51:43:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
10:51:43:setup_element:INFO: Clock phase scan results for group 0, downlink 2
10:51:43:setup_element:INFO: Eye window for uplink 16: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
10:51:43:setup_element:INFO: Eye window for uplink 17: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
10:51:43:setup_element:INFO: Eye window for uplink 18: _______________________________________________________________________XXXXXXXXX
Clock Delay: 35
10:51:43:setup_element:INFO: Eye window for uplink 19: _______________________________________________________________________XXXXXXXXX
Clock Delay: 35
10:51:43:setup_element:INFO: Eye window for uplink 20: ________________________________________________________________________________
Clock Delay: 40
10:51:43:setup_element:INFO: Eye window for uplink 21: ________________________________________________________________________________
Clock Delay: 40
10:51:43:setup_element:INFO: Eye window for uplink 22: ________________________________________________________________________________
Clock Delay: 40
10:51:43:setup_element:INFO: Eye window for uplink 23: ________________________________________________________________________________
Clock Delay: 40
10:51:43:setup_element:INFO: Eye window for uplink 24: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
10:51:43:setup_element:INFO: Eye window for uplink 25: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
10:51:43:setup_element:INFO: Eye window for uplink 26: ________________________________________________________________________________
Clock Delay: 40
10:51:43:setup_element:INFO: Eye window for uplink 27: ________________________________________________________________________________
Clock Delay: 40
10:51:43:setup_element:INFO: Eye window for uplink 28: ________________________________________________________________________XXXXXXX_
Clock Delay: 35
10:51:43:setup_element:INFO: Eye window for uplink 29: ________________________________________________________________________XXXXXXX_
Clock Delay: 35
10:51:43:setup_element:INFO: Eye window for uplink 30: _________________________________________________________________________XXXXXXX
Clock Delay: 36
10:51:43:setup_element:INFO: Eye window for uplink 31: _________________________________________________________________________XXXXXXX
Clock Delay: 36
10:51:43:setup_element:INFO: Setting the clock phase to 35 for group 0, downlink 2
10:51:43:setup_element:INFO: Scanning data phases
10:51:43:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
10:51:43:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
10:51:49:setup_element:INFO: Data phase scan results for group 0, downlink 2
10:51:49:setup_element:INFO: Eye window for uplink 16: ___________________________________XXXX_
Data delay found: 16
10:51:49:setup_element:INFO: Eye window for uplink 17: _______________________________XXXXX____
Data delay found: 13
10:51:49:setup_element:INFO: Eye window for uplink 18: XX_________________________________XXXXX
Data delay found: 18
10:51:49:setup_element:INFO: Eye window for uplink 19: _________________________________XXXXXX_
Data delay found: 15
10:51:49:setup_element:INFO: Eye window for uplink 20: __________________________________XXXXXX
Data delay found: 16
10:51:49:setup_element:INFO: Eye window for uplink 21: ________________________________XXXXXX__
Data delay found: 14
10:51:49:setup_element:INFO: Eye window for uplink 22: X________________________XXXXXXXXXXXXXXX
Data delay found: 12
10:51:49:setup_element:INFO: Eye window for uplink 23: _________________________XXXXXXXXXXXXXXX
Data delay found: 12
10:51:49:setup_element:INFO: Eye window for uplink 24: _XXXXXXXXXXX___________________________X
Data delay found: 25
10:51:49:setup_element:INFO: Eye window for uplink 25: _______XXXXXX___________________________
Data delay found: 29
10:51:49:setup_element:INFO: Eye window for uplink 26: __XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Data delay found: 0
10:51:49:setup_element:INFO: Eye window for uplink 27: __XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Data delay found: 0
10:51:49:setup_element:INFO: Eye window for uplink 28: __________XXXXXX________________________
Data delay found: 32
10:51:49:setup_element:INFO: Eye window for uplink 29: ____________XXXXXXXX____________________
Data delay found: 35
10:51:49:setup_element:INFO: Eye window for uplink 30: __________XXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Data delay found: 4
10:51:49:setup_element:INFO: Eye window for uplink 31: __________XXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Data delay found: 4
10:51:49:setup_element:INFO: Setting the data phase to 16 for uplink 16
10:51:49:setup_element:INFO: Setting the data phase to 13 for uplink 17
10:51:49:setup_element:INFO: Setting the data phase to 18 for uplink 18
10:51:49:setup_element:INFO: Setting the data phase to 15 for uplink 19
10:51:49:setup_element:INFO: Setting the data phase to 16 for uplink 20
10:51:49:setup_element:INFO: Setting the data phase to 14 for uplink 21
10:51:49:setup_element:INFO: Setting the data phase to 12 for uplink 22
10:51:49:setup_element:INFO: Setting the data phase to 12 for uplink 23
10:51:49:setup_element:INFO: Setting the data phase to 25 for uplink 24
10:51:49:setup_element:INFO: Setting the data phase to 29 for uplink 25
10:51:49:setup_element:INFO: Setting the data phase to 0 for uplink 26
10:51:49:setup_element:INFO: Setting the data phase to 0 for uplink 27
10:51:49:setup_element:INFO: Setting the data phase to 32 for uplink 28
10:51:49:setup_element:INFO: Setting the data phase to 35 for uplink 29
10:51:49:setup_element:INFO: Setting the data phase to 4 for uplink 30
10:51:49:setup_element:INFO: Setting the data phase to 4 for uplink 31
10:51:49:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 35
Window Length: 71
Eye Windows:
Uplink 16: _______________________________________________________________________XXXXXXXX_
Uplink 17: _______________________________________________________________________XXXXXXXX_
Uplink 18: _______________________________________________________________________XXXXXXXXX
Uplink 19: _______________________________________________________________________XXXXXXXXX
Uplink 20: ________________________________________________________________________________
Uplink 21: ________________________________________________________________________________
Uplink 22: ________________________________________________________________________________
Uplink 23: ________________________________________________________________________________
Uplink 24: _______________________________________________________________________XXXXXXXX_
Uplink 25: _______________________________________________________________________XXXXXXXX_
Uplink 26: ________________________________________________________________________________
Uplink 27: ________________________________________________________________________________
Uplink 28: ________________________________________________________________________XXXXXXX_
Uplink 29: ________________________________________________________________________XXXXXXX_
Uplink 30: _________________________________________________________________________XXXXXXX
Uplink 31: _________________________________________________________________________XXXXXXX
Data phase characteristics:
Uplink 16:
Optimal Phase: 16
Window Length: 36
Eye Window: ___________________________________XXXX_
Uplink 17:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 18:
Optimal Phase: 18
Window Length: 33
Eye Window: XX_________________________________XXXXX
Uplink 19:
Optimal Phase: 15
Window Length: 34
Eye Window: _________________________________XXXXXX_
Uplink 20:
Optimal Phase: 16
Window Length: 34
Eye Window: __________________________________XXXXXX
Uplink 21:
Optimal Phase: 14
Window Length: 34
Eye Window: ________________________________XXXXXX__
Uplink 22:
Optimal Phase: 12
Window Length: 24
Eye Window: X________________________XXXXXXXXXXXXXXX
Uplink 23:
Optimal Phase: 12
Window Length: 25
Eye Window: _________________________XXXXXXXXXXXXXXX
Uplink 24:
Optimal Phase: 25
Window Length: 27
Eye Window: _XXXXXXXXXXX___________________________X
Uplink 25:
Optimal Phase: 29
Window Length: 34
Eye Window: _______XXXXXX___________________________
Uplink 26:
Optimal Phase: 0
Window Length: 2
Eye Window: __XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Uplink 27:
Optimal Phase: 0
Window Length: 2
Eye Window: __XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Uplink 28:
Optimal Phase: 32
Window Length: 34
Eye Window: __________XXXXXX________________________
Uplink 29:
Optimal Phase: 35
Window Length: 32
Eye Window: ____________XXXXXXXX____________________
Uplink 30:
Optimal Phase: 4
Window Length: 10
Eye Window: __________XXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Uplink 31:
Optimal Phase: 4
Window Length: 10
Eye Window: __________XXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
]
10:51:49:setup_element:INFO: Beginning SMX ASICs map scan
10:51:49:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
10:51:49:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
10:51:49:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
10:51:49:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
10:51:49:uplink:INFO: Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
10:51:49:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 23
10:51:49:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 22
10:51:49:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 30
10:51:49:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 31
10:51:50:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 21
10:51:50:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 20
10:51:50:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28
10:51:50:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 29
10:51:50:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 19
10:51:50:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 18
10:51:50:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26
10:51:50:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 27
10:51:50:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 17
10:51:50:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 16
10:51:50:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 24
10:51:50:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 25
10:51:52:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 23), (1, 22)
ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
ASIC address 0x2: (ASIC uplink, uplink): (0, 21), (1, 20)
ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
ASIC address 0x4: (ASIC uplink, uplink): (0, 19), (1, 18)
ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
ASIC address 0x6: (ASIC uplink, uplink): (0, 17), (1, 16)
ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
Clock Phase Characteristic:
Optimal Phase: 35
Window Length: 71
Eye Windows:
Uplink 16: _______________________________________________________________________XXXXXXXX_
Uplink 17: _______________________________________________________________________XXXXXXXX_
Uplink 18: _______________________________________________________________________XXXXXXXXX
Uplink 19: _______________________________________________________________________XXXXXXXXX
Uplink 20: ________________________________________________________________________________
Uplink 21: ________________________________________________________________________________
Uplink 22: ________________________________________________________________________________
Uplink 23: ________________________________________________________________________________
Uplink 24: _______________________________________________________________________XXXXXXXX_
Uplink 25: _______________________________________________________________________XXXXXXXX_
Uplink 26: ________________________________________________________________________________
Uplink 27: ________________________________________________________________________________
Uplink 28: ________________________________________________________________________XXXXXXX_
Uplink 29: ________________________________________________________________________XXXXXXX_
Uplink 30: _________________________________________________________________________XXXXXXX
Uplink 31: _________________________________________________________________________XXXXXXX
Data phase characteristics:
Uplink 16:
Optimal Phase: 16
Window Length: 36
Eye Window: ___________________________________XXXX_
Uplink 17:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 18:
Optimal Phase: 18
Window Length: 33
Eye Window: XX_________________________________XXXXX
Uplink 19:
Optimal Phase: 15
Window Length: 34
Eye Window: _________________________________XXXXXX_
Uplink 20:
Optimal Phase: 16
Window Length: 34
Eye Window: __________________________________XXXXXX
Uplink 21:
Optimal Phase: 14
Window Length: 34
Eye Window: ________________________________XXXXXX__
Uplink 22:
Optimal Phase: 12
Window Length: 24
Eye Window: X________________________XXXXXXXXXXXXXXX
Uplink 23:
Optimal Phase: 12
Window Length: 25
Eye Window: _________________________XXXXXXXXXXXXXXX
Uplink 24:
Optimal Phase: 25
Window Length: 27
Eye Window: _XXXXXXXXXXX___________________________X
Uplink 25:
Optimal Phase: 29
Window Length: 34
Eye Window: _______XXXXXX___________________________
Uplink 26:
Optimal Phase: 0
Window Length: 2
Eye Window: __XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Uplink 27:
Optimal Phase: 0
Window Length: 2
Eye Window: __XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Uplink 28:
Optimal Phase: 32
Window Length: 34
Eye Window: __________XXXXXX________________________
Uplink 29:
Optimal Phase: 35
Window Length: 32
Eye Window: ____________XXXXXXXX____________________
Uplink 30:
Optimal Phase: 4
Window Length: 10
Eye Window: __________XXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Uplink 31:
Optimal Phase: 4
Window Length: 10
Eye Window: __________XXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
10:51:52:setup_element:INFO: Performing Elink synchronization
10:51:52:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
10:51:52:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
10:51:52:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
10:51:52:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
10:51:52:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2
10:51:52:uplink:INFO: Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
10:51:52:ST3_emu:INFO: Number of chips: 8
addr | upli | dwnli | grp | uplinks | uplinks_map
0 | [0] | 2 | 0 | [23] | [(0, 23), (1, 22)]
1 | [0] | 2 | 0 | [30] | [(0, 30), (1, 31)]
2 | [0] | 2 | 0 | [21] | [(0, 21), (1, 20)]
3 | [0] | 2 | 0 | [28] | [(0, 28), (1, 29)]
4 | [0] | 2 | 0 | [19] | [(0, 19), (1, 18)]
5 | [0] | 2 | 0 | [26] | [(0, 26), (1, 27)]
6 | [0] | 2 | 0 | [17] | [(0, 17), (1, 16)]
7 | [0] | 2 | 0 | [24] | [(0, 24), (1, 25)]
10:51:53:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:51:53:febtest:INFO: 0-0 | XA-000-08-001-064-014-128-04 | 34.6 | 1189.2
10:51:53:febtest:INFO: 0-1 | XA-000-08-002-000-003-233-01 | 25.1 | 1224.5
10:51:53:febtest:INFO: 0-2 | XA-000-08-002-000-003-230-01 | 40.9 | 1165.6
10:51:54:febtest:INFO: 0-3 | XA-000-08-002-000-003-196-15 | 25.1 | 1230.3
10:51:54:febtest:INFO: 0-4 | XA-000-08-002-000-003-222-08 | 44.1 | 1159.7
10:51:54:febtest:INFO: 0-5 | XA-000-08-002-000-003-189-03 | 34.6 | 1201.0
10:51:54:febtest:INFO: 0-6 | XA-000-08-002-000-003-194-15 | 37.7 | 1183.3
10:51:55:febtest:INFO: 0-7 | XA-000-08-002-001-007-151-03 | 21.9 | 1236.2
10:51:55:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
10:51:58:ST3_smx:INFO: chip: 0-0 40.898880 C 1177.390875 mV
10:51:58:ST3_smx:INFO: Electrons
10:51:58:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
10:52:01:ST3_smx:INFO: ----> Checking Analog response
10:52:01:ST3_smx:INFO: ----> Checking broken channels
10:52:01:ST3_smx:INFO: Total # broken ch: 1
10:52:01:ST3_smx:INFO: List FAST: [99]
10:52:01:ST3_smx:INFO: List SLOW: []
10:52:01:ST3_smx:INFO: Holes
10:52:01:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
10:52:03:ST3_smx:INFO: ----> Checking Analog response
10:52:03:ST3_smx:INFO: ----> Checking broken channels
10:52:03:ST3_smx:INFO: Total # broken ch: 1
10:52:03:ST3_smx:INFO: List FAST: [99]
10:52:03:ST3_smx:INFO: List SLOW: []
10:52:03:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:52:03:febtest:INFO: 0-0 | XA-000-08-001-064-014-128-04 | 40.9 | 1171.5
10:52:04:febtest:INFO: 0-1 | XA-000-08-002-000-003-233-01 | 25.1 | 1224.5
10:52:04:febtest:INFO: 0-2 | XA-000-08-002-000-003-230-01 | 40.9 | 1165.6
10:52:04:febtest:INFO: 0-3 | XA-000-08-002-000-003-196-15 | 25.1 | 1230.3
10:52:04:febtest:INFO: 0-4 | XA-000-08-002-000-003-222-08 | 44.1 | 1159.7
10:52:04:febtest:INFO: 0-5 | XA-000-08-002-000-003-189-03 | 34.6 | 1201.0
10:52:05:febtest:INFO: 0-6 | XA-000-08-002-000-003-194-15 | 37.7 | 1183.3
10:52:05:febtest:INFO: 0-7 | XA-000-08-002-001-007-151-03 | 21.9 | 1236.2
10:52:05:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
10:52:09:ST3_smx:INFO: chip: 0-1 25.062742 C 1224.468235 mV
10:52:09:ST3_smx:INFO: Electrons
10:52:09:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
10:52:11:ST3_smx:INFO: ----> Checking Analog response
10:52:11:ST3_smx:INFO: ----> Checking broken channels
10:52:11:ST3_smx:INFO: Total # broken ch: 4
10:52:11:ST3_smx:INFO: List FAST: [63, 88, 98, 100]
10:52:11:ST3_smx:INFO: List SLOW: []
10:52:11:ST3_smx:INFO: Holes
10:52:11:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
10:52:13:ST3_smx:INFO: ----> Checking Analog response
10:52:13:ST3_smx:INFO: ----> Checking broken channels
10:52:14:ST3_smx:INFO: Total # broken ch: 4
10:52:14:ST3_smx:INFO: List FAST: [63, 88, 98, 100]
10:52:14:ST3_smx:INFO: List SLOW: []
10:52:14:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:52:14:febtest:INFO: 0-0 | XA-000-08-001-064-014-128-04 | 40.9 | 1171.5
10:52:14:febtest:INFO: 0-1 | XA-000-08-002-000-003-233-01 | 28.2 | 1218.6
10:52:14:febtest:INFO: 0-2 | XA-000-08-002-000-003-230-01 | 40.9 | 1165.6
10:52:14:febtest:INFO: 0-3 | XA-000-08-002-000-003-196-15 | 25.1 | 1230.3
10:52:15:febtest:INFO: 0-4 | XA-000-08-002-000-003-222-08 | 44.1 | 1159.7
10:52:15:febtest:INFO: 0-5 | XA-000-08-002-000-003-189-03 | 34.6 | 1201.0
10:52:15:febtest:INFO: 0-6 | XA-000-08-002-000-003-194-15 | 37.7 | 1183.3
10:52:15:febtest:INFO: 0-7 | XA-000-08-002-001-007-151-03 | 21.9 | 1242.0
10:52:16:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
10:52:19:ST3_smx:INFO: chip: 0-2 40.898880 C 1165.571835 mV
10:52:19:ST3_smx:INFO: Electrons
10:52:19:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
10:52:22:ST3_smx:INFO: ----> Checking Analog response
10:52:22:ST3_smx:INFO: ----> Checking broken channels
10:52:22:ST3_smx:INFO: Total # broken ch: 1
10:52:22:ST3_smx:INFO: List FAST: [41]
10:52:22:ST3_smx:INFO: List SLOW: []
10:52:22:ST3_smx:INFO: Holes
10:52:22:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
10:52:24:ST3_smx:INFO: ----> Checking Analog response
10:52:24:ST3_smx:INFO: ----> Checking broken channels
10:52:24:ST3_smx:INFO: Total # broken ch: 1
10:52:24:ST3_smx:INFO: List FAST: [41]
10:52:24:ST3_smx:INFO: List SLOW: []
10:52:24:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:52:24:febtest:INFO: 0-0 | XA-000-08-001-064-014-128-04 | 40.9 | 1171.5
10:52:25:febtest:INFO: 0-1 | XA-000-08-002-000-003-233-01 | 28.2 | 1224.5
10:52:25:febtest:INFO: 0-2 | XA-000-08-002-000-003-230-01 | 44.1 | 1159.7
10:52:25:febtest:INFO: 0-3 | XA-000-08-002-000-003-196-15 | 25.1 | 1230.3
10:52:25:febtest:INFO: 0-4 | XA-000-08-002-000-003-222-08 | 44.1 | 1159.7
10:52:25:febtest:INFO: 0-5 | XA-000-08-002-000-003-189-03 | 34.6 | 1201.0
10:52:26:febtest:INFO: 0-6 | XA-000-08-002-000-003-194-15 | 37.7 | 1183.3
10:52:26:febtest:INFO: 0-7 | XA-000-08-002-001-007-151-03 | 21.9 | 1242.0
10:52:26:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
10:52:30:ST3_smx:INFO: chip: 0-3 34.556970 C 1195.082160 mV
10:52:30:ST3_smx:INFO: Electrons
10:52:30:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
10:52:32:ST3_smx:INFO: ----> Checking Analog response
10:52:32:ST3_smx:INFO: ----> Checking broken channels
10:52:32:ST3_smx:INFO: Total # broken ch: 13
10:52:32:ST3_smx:INFO: List FAST: [43, 47, 49, 92, 93, 99, 113, 119]
10:52:32:ST3_smx:INFO: List SLOW: [43, 47, 93, 99, 113]
10:52:32:ST3_smx:INFO: Holes
10:52:32:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
10:52:34:ST3_smx:INFO: ----> Checking Analog response
10:52:34:ST3_smx:INFO: ----> Checking broken channels
10:52:35:ST3_smx:INFO: Total # broken ch: 13
10:52:35:ST3_smx:INFO: List FAST: [43, 47, 49, 92, 93, 99, 113, 119]
10:52:35:ST3_smx:INFO: List SLOW: [43, 47, 93, 99, 113]
10:52:35:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:52:35:febtest:INFO: 0-0 | XA-000-08-001-064-014-128-04 | 40.9 | 1171.5
10:52:35:febtest:INFO: 0-1 | XA-000-08-002-000-003-233-01 | 28.2 | 1224.5
10:52:35:febtest:INFO: 0-2 | XA-000-08-002-000-003-230-01 | 44.1 | 1165.6
10:52:36:febtest:INFO: 0-3 | XA-000-08-002-000-003-196-15 | 37.7 | 1195.1
10:52:36:febtest:INFO: 0-4 | XA-000-08-002-000-003-222-08 | 44.1 | 1159.7
10:52:36:febtest:INFO: 0-5 | XA-000-08-002-000-003-189-03 | 34.6 | 1201.0
10:52:36:febtest:INFO: 0-6 | XA-000-08-002-000-003-194-15 | 37.7 | 1183.3
10:52:36:febtest:INFO: 0-7 | XA-000-08-002-001-007-151-03 | 21.9 | 1242.0
10:52:36:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
10:52:40:ST3_smx:INFO: chip: 0-4 47.250730 C 1153.732915 mV
10:52:40:ST3_smx:INFO: Electrons
10:52:40:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
10:52:42:ST3_smx:INFO: ----> Checking Analog response
10:52:42:ST3_smx:INFO: ----> Checking broken channels
10:52:43:ST3_smx:INFO: Total # broken ch: 5
10:52:43:ST3_smx:INFO: List FAST: [25, 75, 86, 102, 115]
10:52:43:ST3_smx:INFO: List SLOW: []
10:52:43:ST3_smx:INFO: Holes
10:52:43:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
10:52:45:ST3_smx:INFO: ----> Checking Analog response
10:52:45:ST3_smx:INFO: ----> Checking broken channels
10:52:45:ST3_smx:INFO: Total # broken ch: 5
10:52:45:ST3_smx:INFO: List FAST: [25, 75, 86, 102, 115]
10:52:45:ST3_smx:INFO: List SLOW: []
10:52:45:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:52:45:febtest:INFO: 0-0 | XA-000-08-001-064-014-128-04 | 40.9 | 1171.5
10:52:45:febtest:INFO: 0-1 | XA-000-08-002-000-003-233-01 | 28.2 | 1224.5
10:52:46:febtest:INFO: 0-2 | XA-000-08-002-000-003-230-01 | 44.1 | 1165.6
10:52:46:febtest:INFO: 0-3 | XA-000-08-002-000-003-196-15 | 37.7 | 1195.1
10:52:46:febtest:INFO: 0-4 | XA-000-08-002-000-003-222-08 | 47.3 | 1147.8
10:52:46:febtest:INFO: 0-5 | XA-000-08-002-000-003-189-03 | 34.6 | 1201.0
10:52:46:febtest:INFO: 0-6 | XA-000-08-002-000-003-194-15 | 37.7 | 1183.3
10:52:46:febtest:INFO: 0-7 | XA-000-08-002-001-007-151-03 | 21.9 | 1242.0
10:52:47:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
10:52:51:ST3_smx:INFO: chip: 0-5 34.556970 C 1206.851500 mV
10:52:51:ST3_smx:INFO: Electrons
10:52:51:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
10:52:53:ST3_smx:INFO: ----> Checking Analog response
10:52:53:ST3_smx:INFO: ----> Checking broken channels
10:52:53:ST3_smx:INFO: Total # broken ch: 1
10:52:53:ST3_smx:INFO: List FAST: [57]
10:52:53:ST3_smx:INFO: List SLOW: []
10:52:53:ST3_smx:INFO: Holes
10:52:53:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
10:52:55:ST3_smx:INFO: ----> Checking Analog response
10:52:55:ST3_smx:INFO: ----> Checking broken channels
10:52:55:ST3_smx:INFO: Total # broken ch: 1
10:52:55:ST3_smx:INFO: List FAST: [57]
10:52:55:ST3_smx:INFO: List SLOW: []
10:52:55:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:52:55:febtest:INFO: 0-0 | XA-000-08-001-064-014-128-04 | 40.9 | 1171.5
10:52:56:febtest:INFO: 0-1 | XA-000-08-002-000-003-233-01 | 28.2 | 1224.5
10:52:56:febtest:INFO: 0-2 | XA-000-08-002-000-003-230-01 | 44.1 | 1165.6
10:52:56:febtest:INFO: 0-3 | XA-000-08-002-000-003-196-15 | 37.7 | 1195.1
10:52:56:febtest:INFO: 0-4 | XA-000-08-002-000-003-222-08 | 47.3 | 1153.7
10:52:56:febtest:INFO: 0-5 | XA-000-08-002-000-003-189-03 | 34.6 | 1201.0
10:52:57:febtest:INFO: 0-6 | XA-000-08-002-000-003-194-15 | 37.7 | 1183.3
10:52:57:febtest:INFO: 0-7 | XA-000-08-002-001-007-151-03 | 25.1 | 1242.0
10:52:57:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
10:53:01:ST3_smx:INFO: chip: 0-6 40.898880 C 1177.390875 mV
10:53:01:ST3_smx:INFO: Electrons
10:53:01:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
10:53:03:ST3_smx:INFO: ----> Checking Analog response
10:53:03:ST3_smx:INFO: ----> Checking broken channels
10:53:03:ST3_smx:INFO: Total # broken ch: 0
10:53:03:ST3_smx:INFO: List FAST: []
10:53:03:ST3_smx:INFO: List SLOW: []
10:53:03:ST3_smx:INFO: Holes
10:53:03:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
10:53:05:ST3_smx:INFO: ----> Checking Analog response
10:53:05:ST3_smx:INFO: ----> Checking broken channels
10:53:05:ST3_smx:INFO: Total # broken ch: 0
10:53:05:ST3_smx:INFO: List FAST: []
10:53:05:ST3_smx:INFO: List SLOW: []
10:53:05:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:53:05:febtest:INFO: 0-0 | XA-000-08-001-064-014-128-04 | 40.9 | 1171.5
10:53:06:febtest:INFO: 0-1 | XA-000-08-002-000-003-233-01 | 28.2 | 1224.5
10:53:06:febtest:INFO: 0-2 | XA-000-08-002-000-003-230-01 | 44.1 | 1165.6
10:53:06:febtest:INFO: 0-3 | XA-000-08-002-000-003-196-15 | 37.7 | 1195.1
10:53:06:febtest:INFO: 0-4 | XA-000-08-002-000-003-222-08 | 47.3 | 1153.7
10:53:07:febtest:INFO: 0-5 | XA-000-08-002-000-003-189-03 | 34.6 | 1201.0
10:53:07:febtest:INFO: 0-6 | XA-000-08-002-000-003-194-15 | 40.9 | 1171.5
10:53:07:febtest:INFO: 0-7 | XA-000-08-002-001-007-151-03 | 25.1 | 1242.0
10:53:07:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
10:53:11:ST3_smx:INFO: chip: 0-7 28.225000 C 1236.187875 mV
10:53:11:ST3_smx:INFO: Electrons
10:53:11:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
10:53:13:ST3_smx:INFO: ----> Checking Analog response
10:53:13:ST3_smx:INFO: ----> Checking broken channels
10:53:13:ST3_smx:INFO: Total # broken ch: 3
10:53:13:ST3_smx:INFO: List FAST: [27, 37, 102]
10:53:13:ST3_smx:INFO: List SLOW: []
10:53:13:ST3_smx:INFO: Holes
10:53:13:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
10:53:15:ST3_smx:INFO: ----> Checking Analog response
10:53:15:ST3_smx:INFO: ----> Checking broken channels
10:53:16:ST3_smx:INFO: Total # broken ch: 3
10:53:16:ST3_smx:INFO: List FAST: [27, 37, 102]
10:53:16:ST3_smx:INFO: List SLOW: []
10:53:16:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:53:16:febtest:INFO: 0-0 | XA-000-08-001-064-014-128-04 | 40.9 | 1171.5
10:53:16:febtest:INFO: 0-1 | XA-000-08-002-000-003-233-01 | 28.2 | 1224.5
10:53:16:febtest:INFO: 0-2 | XA-000-08-002-000-003-230-01 | 44.1 | 1165.6
10:53:17:febtest:INFO: 0-3 | XA-000-08-002-000-003-196-15 | 37.7 | 1195.1
10:53:17:febtest:INFO: 0-4 | XA-000-08-002-000-003-222-08 | 47.3 | 1153.7
10:53:17:febtest:INFO: 0-5 | XA-000-08-002-000-003-189-03 | 34.6 | 1206.9
10:53:17:febtest:INFO: 0-6 | XA-000-08-002-000-003-194-15 | 40.9 | 1171.5
10:53:18:febtest:INFO: 0-7 | XA-000-08-002-001-007-151-03 | 28.2 | 1230.3
############################################################
# S U M M A R Y #
############################################################
{'TEST_NAME': 'FEB-ASIC', 'TEST_DATE': '2023_11_28-10_51_40', 'OPERATOR': 'Irakli K.; ', 'PROJECT': 'Production', 'SITE': 'GSI', 'SETUP': 'GSI_TEST_SETUP_1', 'ASIC_ID': 'XA-000-08-002-001-007-151-03', 'FUSED_ID': 6359364699117615475, 'HW_ADDR': 7, 'UPLINK': 24, 'VERS_NO': '2.2', 'CABLE_SET_ID': '', 'IC_TEMP': '0', 'VDDM': '0', 'AUX': '0', 'CSABIAS': '0', 'VDDM_INT': '0', 'ADC_Chi2': 0.0, 'ADC_NDF': 0, 'ADC_P0': 0.0, 'ADC_P1': 0.006824, 'ADC_P2': -2.485e-06, 'ADC_P0err': 0.001, 'ADC_P1err': 0.001, 'ADC_P2err': 1e-05, 'ADC_VREF_P': 58, 'ADC_VREF_N': 30, 'ADC_VREF_T': 128, 'ADC_VREF_TR': 122, 'THR2_GLB': 30, 'LOOP__PLS': 100, 'CALIB_PLS': 250, 'SnsLoop': 5, 'IFED': 31, 'CSA_BIAS': 15, 'CSA_Chi2': 0.0, 'CSA_NDF': 0, 'CSA_P0': 0.0, 'CSA_P1': 0.0, 'CSA_P2': 0.0, 'CSA_P0err': 0.0, 'CSA_P1err': 0.0, 'CSA_P2err': 0.0, 'CONF_FAIL_REG': 0, 'N_BROKEN_DISC': 3, 'N_BROKEN_FAST': '[27, 37, 102]', 'N_BROKEN_SLOW': '[]', 'P_BROKEN_DISC': 3, 'P_BROKEN_FAST': '[27, 37, 102]', 'P_BROKEN_SLOW': '[]', 'ASIC_QA_category': '', 'N_BROKEN_CABLE': 0, 'LIST_OF_BROKEN_CABLES': 0, 'FEB_SN': '1086', 'FEB_TYPE': 8.2, 'FEB_UPLINKS': 2, 'FEB_A': 1, 'FEB_B': 0, 'ADDR_0': '', 'ADDR_1': '', 'ADDR_2': '', 'ADDR_3': '', 'ADDR_4': '', 'ADDR_5': '', 'ADDR_6': '', 'ADDR_7': '', 'SENSOR_ID': '', 'MODULE_NAME': '', 'MODULE_LADDER': '', 'MODULE_MODULE': '', 'MODULE_SIZE': '', 'MODULE_GRADE': '', 'MODULE_TYPE': '', 'VI_bInit': ['2.447', '1.9870', '1.847', '2.0210', '7.000', '1.5590', '7.000', '1.5590'], 'VI_aInit': ['0', '0', '0', '0', '0', '0'], 'VI_atEnd': ['0', '0', '0', '0', '0', '0'], 'AMP_CAL': 125, 'PlsLoop': 3, 'N_ANA_PRESENT': 'Analog response OK', 'N_DISC_FAIL_CH': 0, 'N_ANA_FAIL_CH': '0', 'P_ANA_PRESENT': 'Analog response OK', 'P_DISC_FAIL_CH': 0, 'P_ANA_FAIL_CH': '0'}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-ASIC
TEST_DATE : 2023_11_28-10_51_40
OPERATOR : Irakli K.;
SITE : GSI
SETUP : GSI_TEST_SETUP_1
Set-ID :
---------------------------------------
MODULE_NAME :
FEB_SN : 1086
FEB_TYPE : 8.2
FEB_UPLINKS : 2
FEB_A : 1
FEB_B : 0
---------------------------------------
MODULE_NAME
---------------------------------------
VI_before_Init : ['2.447', '1.9870', '1.847', '2.0210', '7.000', '1.5590', '7.000', '1.5590']
VI_after__Init : ['2.450', '2.0440', '1.850', '0.3197', '7.000', '1.5550', '7.000', '1.5550']
VI_at__the_End : ['2.450', '2.0440', '1.850', '0.3197', '7.000', '1.5550', '7.000', '1.5550']
10:53:23:ST3_Shared:INFO: /home/cbm/public_html/Production_LogDir//FEB/FEB_2012/TestDate_2023_11_28-10_51_40/