Go Back
FEB_2013 28.08.23 10:17:55
TextEdit.txt
10:16:55:ST3_hmp4040:INFO: HAMEG,HMP2030,017836163,HW50010002/SW2.30
10:16:55:febtest:INFO: FEB8.2 selected
10:16:56:febtest:INFO: FEB8.2 selected
10:16:57:ST3_Shared:INFO: Listo of operators:Oleksandr S.;
10:17:15:smx_tester:INFO: Setting Elink clock mode to 160 MHz
10:17:55:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
10:17:55:ST3_Shared:INFO: --------------------------FEB-ASIC--------------------------
10:17:55:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
10:17:55:febtest:INFO: Tsting FEB with SN 2013
10:17:56:smx_tester:INFO: Scanning setup
10:17:56:elinks:INFO: Disabling clock on downlink 0
10:17:56:elinks:INFO: Disabling clock on downlink 1
10:17:56:elinks:INFO: Disabling clock on downlink 2
10:17:56:elinks:INFO: Disabling clock on downlink 3
10:17:56:elinks:INFO: Disabling clock on downlink 4
10:17:56:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:17:56:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
10:17:56:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:17:56:elinks:INFO: Disabling clock on downlink 0
10:17:56:elinks:INFO: Disabling clock on downlink 1
10:17:56:elinks:INFO: Disabling clock on downlink 2
10:17:57:elinks:INFO: Disabling clock on downlink 3
10:17:57:elinks:INFO: Disabling clock on downlink 4
10:17:57:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:17:57:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
10:17:57:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:17:57:elinks:INFO: Disabling clock on downlink 0
10:17:57:elinks:INFO: Disabling clock on downlink 1
10:17:57:elinks:INFO: Disabling clock on downlink 2
10:17:57:elinks:INFO: Disabling clock on downlink 3
10:17:57:elinks:INFO: Disabling clock on downlink 4
10:17:57:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:17:57:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
10:17:57:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 16
10:17:57:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 17
10:17:57:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 18
10:17:57:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 19
10:17:57:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 20
10:17:57:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 21
10:17:57:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 22
10:17:57:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 23
10:17:57:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24
10:17:57:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25
10:17:57:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26
10:17:57:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27
10:17:57:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28
10:17:57:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29
10:17:57:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30
10:17:57:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31
10:17:57:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:17:57:elinks:INFO: Disabling clock on downlink 0
10:17:57:elinks:INFO: Disabling clock on downlink 1
10:17:57:elinks:INFO: Disabling clock on downlink 2
10:17:57:elinks:INFO: Disabling clock on downlink 3
10:17:57:elinks:INFO: Disabling clock on downlink 4
10:17:57:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:17:57:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
10:17:57:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:17:57:elinks:INFO: Disabling clock on downlink 0
10:17:57:elinks:INFO: Disabling clock on downlink 1
10:17:57:elinks:INFO: Disabling clock on downlink 2
10:17:57:elinks:INFO: Disabling clock on downlink 3
10:17:57:elinks:INFO: Disabling clock on downlink 4
10:17:57:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:17:57:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
10:17:57:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:17:57:setup_element:INFO: Scanning clock phase
10:17:57:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
10:17:57:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
10:17:57:setup_element:INFO: Clock phase scan results for group 0, downlink 2
10:17:57:setup_element:INFO: Eye window for uplink 16: ________________________________________________________________________XXXXXXXX
Clock Delay: 35
10:17:57:setup_element:INFO: Eye window for uplink 17: ________________________________________________________________________XXXXXXXX
Clock Delay: 35
10:17:57:setup_element:INFO: Eye window for uplink 18: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
10:17:57:setup_element:INFO: Eye window for uplink 19: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
10:17:57:setup_element:INFO: Eye window for uplink 20: ________________________________________________________________________XXXXXXXX
Clock Delay: 35
10:17:57:setup_element:INFO: Eye window for uplink 21: ________________________________________________________________________XXXXXXXX
Clock Delay: 35
10:17:57:setup_element:INFO: Eye window for uplink 22: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
10:17:57:setup_element:INFO: Eye window for uplink 23: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
10:17:57:setup_element:INFO: Eye window for uplink 24: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
10:17:57:setup_element:INFO: Eye window for uplink 25: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
10:17:57:setup_element:INFO: Eye window for uplink 26: _______________________________________________________________________XXXXXXXXX
Clock Delay: 35
10:17:57:setup_element:INFO: Eye window for uplink 27: _______________________________________________________________________XXXXXXXXX
Clock Delay: 35
10:17:57:setup_element:INFO: Eye window for uplink 28: ________________________________________________________________________________
Clock Delay: 40
10:17:57:setup_element:INFO: Eye window for uplink 29: ________________________________________________________________________________
Clock Delay: 40
10:17:57:setup_element:INFO: Eye window for uplink 30: X_________________________________________________________________________XXXXXX
Clock Delay: 37
10:17:57:setup_element:INFO: Eye window for uplink 31: X_________________________________________________________________________XXXXXX
Clock Delay: 37
10:17:57:setup_element:INFO: Setting the clock phase to 35 for group 0, downlink 2
10:17:57:setup_element:INFO: Scanning data phases
10:17:57:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
10:17:58:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
10:18:03:setup_element:INFO: Data phase scan results for group 0, downlink 2
10:18:03:setup_element:INFO: Eye window for uplink 16: XXXX___________________________________X
Data delay found: 21
10:18:03:setup_element:INFO: Eye window for uplink 17: ___________________________________XXXXX
Data delay found: 17
10:18:03:setup_element:INFO: Eye window for uplink 18: XX__________________________________XXXX
Data delay found: 18
10:18:03:setup_element:INFO: Eye window for uplink 19: _________________________________XXXXX__
Data delay found: 15
10:18:03:setup_element:INFO: Eye window for uplink 20: XX___________________________________XXX
Data delay found: 19
10:18:03:setup_element:INFO: Eye window for uplink 21: X__________________________________XXXXX
Data delay found: 17
10:18:03:setup_element:INFO: Eye window for uplink 22: XX_________________________________XXXXX
Data delay found: 18
10:18:03:setup_element:INFO: Eye window for uplink 23: __________________________________XXXXX_
Data delay found: 16
10:18:03:setup_element:INFO: Eye window for uplink 24: _____XXXXX______________________________
Data delay found: 27
10:18:03:setup_element:INFO: Eye window for uplink 25: ________XXXXX___________________________
Data delay found: 30
10:18:03:setup_element:INFO: Eye window for uplink 26: _______XXXXX____________________________
Data delay found: 29
10:18:03:setup_element:INFO: Eye window for uplink 27: __________XXXXXX________________________
Data delay found: 32
10:18:03:setup_element:INFO: Eye window for uplink 28: ___________XXXXX________________________
Data delay found: 33
10:18:03:setup_element:INFO: Eye window for uplink 29: _____________XXXXX______________________
Data delay found: 35
10:18:03:setup_element:INFO: Eye window for uplink 30: _________________XXXXXX_________________
Data delay found: 39
10:18:03:setup_element:INFO: Eye window for uplink 31: _______________XXXXXXX__________________
Data delay found: 38
10:18:03:setup_element:INFO: Setting the data phase to 21 for uplink 16
10:18:03:setup_element:INFO: Setting the data phase to 17 for uplink 17
10:18:03:setup_element:INFO: Setting the data phase to 18 for uplink 18
10:18:03:setup_element:INFO: Setting the data phase to 15 for uplink 19
10:18:03:setup_element:INFO: Setting the data phase to 19 for uplink 20
10:18:03:setup_element:INFO: Setting the data phase to 17 for uplink 21
10:18:03:setup_element:INFO: Setting the data phase to 18 for uplink 22
10:18:03:setup_element:INFO: Setting the data phase to 16 for uplink 23
10:18:03:setup_element:INFO: Setting the data phase to 27 for uplink 24
10:18:03:setup_element:INFO: Setting the data phase to 30 for uplink 25
10:18:03:setup_element:INFO: Setting the data phase to 29 for uplink 26
10:18:03:setup_element:INFO: Setting the data phase to 32 for uplink 27
10:18:03:setup_element:INFO: Setting the data phase to 33 for uplink 28
10:18:03:setup_element:INFO: Setting the data phase to 35 for uplink 29
10:18:03:setup_element:INFO: Setting the data phase to 39 for uplink 30
10:18:03:setup_element:INFO: Setting the data phase to 38 for uplink 31
10:18:03:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 35
Window Length: 70
Eye Windows:
Uplink 16: ________________________________________________________________________XXXXXXXX
Uplink 17: ________________________________________________________________________XXXXXXXX
Uplink 18: _______________________________________________________________________XXXXXXXX_
Uplink 19: _______________________________________________________________________XXXXXXXX_
Uplink 20: ________________________________________________________________________XXXXXXXX
Uplink 21: ________________________________________________________________________XXXXXXXX
Uplink 22: _______________________________________________________________________XXXXXXXX_
Uplink 23: _______________________________________________________________________XXXXXXXX_
Uplink 24: _______________________________________________________________________XXXXXXX__
Uplink 25: _______________________________________________________________________XXXXXXX__
Uplink 26: _______________________________________________________________________XXXXXXXXX
Uplink 27: _______________________________________________________________________XXXXXXXXX
Uplink 28: ________________________________________________________________________________
Uplink 29: ________________________________________________________________________________
Uplink 30: X_________________________________________________________________________XXXXXX
Uplink 31: X_________________________________________________________________________XXXXXX
Data phase characteristics:
Uplink 16:
Optimal Phase: 21
Window Length: 35
Eye Window: XXXX___________________________________X
Uplink 17:
Optimal Phase: 17
Window Length: 35
Eye Window: ___________________________________XXXXX
Uplink 18:
Optimal Phase: 18
Window Length: 34
Eye Window: XX__________________________________XXXX
Uplink 19:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
Uplink 20:
Optimal Phase: 19
Window Length: 35
Eye Window: XX___________________________________XXX
Uplink 21:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXXX
Uplink 22:
Optimal Phase: 18
Window Length: 33
Eye Window: XX_________________________________XXXXX
Uplink 23:
Optimal Phase: 16
Window Length: 35
Eye Window: __________________________________XXXXX_
Uplink 24:
Optimal Phase: 27
Window Length: 35
Eye Window: _____XXXXX______________________________
Uplink 25:
Optimal Phase: 30
Window Length: 35
Eye Window: ________XXXXX___________________________
Uplink 26:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 27:
Optimal Phase: 32
Window Length: 34
Eye Window: __________XXXXXX________________________
Uplink 28:
Optimal Phase: 33
Window Length: 35
Eye Window: ___________XXXXX________________________
Uplink 29:
Optimal Phase: 35
Window Length: 35
Eye Window: _____________XXXXX______________________
Uplink 30:
Optimal Phase: 39
Window Length: 34
Eye Window: _________________XXXXXX_________________
Uplink 31:
Optimal Phase: 38
Window Length: 33
Eye Window: _______________XXXXXXX__________________
]
10:18:03:setup_element:INFO: Beginning SMX ASICs map scan
10:18:03:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
10:18:03:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
10:18:03:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
10:18:03:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
10:18:03:uplink:INFO: Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
10:18:03:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 23
10:18:03:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 22
10:18:03:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 30
10:18:03:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 31
10:18:04:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 21
10:18:04:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 20
10:18:04:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28
10:18:04:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 29
10:18:04:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 19
10:18:04:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 18
10:18:04:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26
10:18:04:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 27
10:18:04:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 17
10:18:04:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 16
10:18:05:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 24
10:18:05:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 25
10:18:06:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 23), (1, 22)
ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
ASIC address 0x2: (ASIC uplink, uplink): (0, 21), (1, 20)
ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
ASIC address 0x4: (ASIC uplink, uplink): (0, 19), (1, 18)
ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
ASIC address 0x6: (ASIC uplink, uplink): (0, 17), (1, 16)
ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
Clock Phase Characteristic:
Optimal Phase: 35
Window Length: 70
Eye Windows:
Uplink 16: ________________________________________________________________________XXXXXXXX
Uplink 17: ________________________________________________________________________XXXXXXXX
Uplink 18: _______________________________________________________________________XXXXXXXX_
Uplink 19: _______________________________________________________________________XXXXXXXX_
Uplink 20: ________________________________________________________________________XXXXXXXX
Uplink 21: ________________________________________________________________________XXXXXXXX
Uplink 22: _______________________________________________________________________XXXXXXXX_
Uplink 23: _______________________________________________________________________XXXXXXXX_
Uplink 24: _______________________________________________________________________XXXXXXX__
Uplink 25: _______________________________________________________________________XXXXXXX__
Uplink 26: _______________________________________________________________________XXXXXXXXX
Uplink 27: _______________________________________________________________________XXXXXXXXX
Uplink 28: ________________________________________________________________________________
Uplink 29: ________________________________________________________________________________
Uplink 30: X_________________________________________________________________________XXXXXX
Uplink 31: X_________________________________________________________________________XXXXXX
Data phase characteristics:
Uplink 16:
Optimal Phase: 21
Window Length: 35
Eye Window: XXXX___________________________________X
Uplink 17:
Optimal Phase: 17
Window Length: 35
Eye Window: ___________________________________XXXXX
Uplink 18:
Optimal Phase: 18
Window Length: 34
Eye Window: XX__________________________________XXXX
Uplink 19:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
Uplink 20:
Optimal Phase: 19
Window Length: 35
Eye Window: XX___________________________________XXX
Uplink 21:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXXX
Uplink 22:
Optimal Phase: 18
Window Length: 33
Eye Window: XX_________________________________XXXXX
Uplink 23:
Optimal Phase: 16
Window Length: 35
Eye Window: __________________________________XXXXX_
Uplink 24:
Optimal Phase: 27
Window Length: 35
Eye Window: _____XXXXX______________________________
Uplink 25:
Optimal Phase: 30
Window Length: 35
Eye Window: ________XXXXX___________________________
Uplink 26:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 27:
Optimal Phase: 32
Window Length: 34
Eye Window: __________XXXXXX________________________
Uplink 28:
Optimal Phase: 33
Window Length: 35
Eye Window: ___________XXXXX________________________
Uplink 29:
Optimal Phase: 35
Window Length: 35
Eye Window: _____________XXXXX______________________
Uplink 30:
Optimal Phase: 39
Window Length: 34
Eye Window: _________________XXXXXX_________________
Uplink 31:
Optimal Phase: 38
Window Length: 33
Eye Window: _______________XXXXXXX__________________
10:18:06:setup_element:INFO: Performing Elink synchronization
10:18:06:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
10:18:06:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
10:18:06:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
10:18:06:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
10:18:06:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2
10:18:06:uplink:INFO: Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
10:18:06:ST3_emu:INFO: Number of chips: 8
10:18:06:ST3_emu:INFO: Chip address: 0x0
10:18:06:ST3_emu:INFO: Chip address: 0x1
10:18:06:ST3_emu:INFO: Chip address: 0x2
10:18:06:ST3_emu:INFO: Chip address: 0x3
10:18:06:ST3_emu:INFO: Chip address: 0x4
10:18:06:ST3_emu:INFO: Chip address: 0x5
10:18:06:ST3_emu:INFO: Chip address: 0x6
10:18:06:ST3_emu:INFO: Chip address: 0x7
10:18:07:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:18:07:febtest:INFO: 0-0 | XA-000-08-002-001-006-147-14 | 18.7 | 1224.5
10:18:08:febtest:INFO: 0-1 | XA-000-08-002-001-006-143-09 | 47.3 | 1118.1
10:18:08:febtest:INFO: 0-2 | XA-000-08-002-001-006-140-09 | 21.9 | 1206.9
10:18:08:febtest:INFO: 0-3 | XA-000-08-002-001-006-153-14 | 25.1 | 1195.1
10:18:08:febtest:INFO: 0-4 | XA-000-08-002-001-006-169-07 | 21.9 | 1212.7
10:18:08:febtest:INFO: 0-5 | XA-000-08-002-001-006-163-07 | 34.6 | 1171.5
10:18:09:febtest:INFO: 0-6 | XA-000-08-002-001-006-177-00 | 28.2 | 1189.2
10:18:09:febtest:INFO: 0-7 | XA-000-08-002-001-006-173-07 | 18.7 | 1224.5
10:18:09:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
10:18:13:ST3_smx:INFO: chip: 0-0 21.902970 C 1195.082160 mV
10:18:13:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
10:18:13:ST3_smx:INFO: Electrons
10:18:13:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
10:18:15:ST3_smx:INFO: ----> Checking Analog response
10:18:15:ST3_smx:INFO: ----> Checking broken channels
10:18:15:ST3_smx:INFO: Total # broken ch: 0
10:18:15:ST3_smx:INFO: List FAST: []
10:18:15:ST3_smx:INFO: List SLOW: []
10:18:15:ST3_smx:INFO: Holes
10:18:15:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
10:18:17:ST3_smx:INFO: ----> Checking Analog response
10:18:17:ST3_smx:INFO: ----> Checking broken channels
10:18:18:ST3_smx:INFO: Total # broken ch: 0
10:18:18:ST3_smx:INFO: List FAST: []
10:18:18:ST3_smx:INFO: List SLOW: []
10:18:18:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:18:18:febtest:INFO: 0-0 | XA-000-08-002-001-006-147-14 | 21.9 | 1189.2
10:18:18:febtest:INFO: 0-1 | XA-000-08-002-001-006-143-09 | 47.3 | 1118.1
10:18:18:febtest:INFO: 0-2 | XA-000-08-002-001-006-140-09 | 18.7 | 1206.9
10:18:18:febtest:INFO: 0-3 | XA-000-08-002-001-006-153-14 | 25.1 | 1201.0
10:18:19:febtest:INFO: 0-4 | XA-000-08-002-001-006-169-07 | 18.7 | 1212.7
10:18:19:febtest:INFO: 0-5 | XA-000-08-002-001-006-163-07 | 34.6 | 1171.5
10:18:19:febtest:INFO: 0-6 | XA-000-08-002-001-006-177-00 | 28.2 | 1189.2
10:18:19:febtest:INFO: 0-7 | XA-000-08-002-001-006-173-07 | 18.7 | 1224.5
10:18:20:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
10:18:23:ST3_smx:INFO: chip: 0-1 40.898880 C 1135.937260 mV
10:18:23:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
10:18:23:ST3_smx:INFO: Electrons
10:18:23:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
10:18:26:ST3_smx:INFO: ----> Checking Analog response
10:18:26:ST3_smx:INFO: ----> Checking broken channels
10:18:26:ST3_smx:INFO: Total # broken ch: 0
10:18:26:ST3_smx:INFO: List FAST: []
10:18:26:ST3_smx:INFO: List SLOW: []
10:18:26:ST3_smx:INFO: Holes
10:18:26:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
10:18:28:ST3_smx:INFO: ----> Checking Analog response
10:18:28:ST3_smx:INFO: ----> Checking broken channels
10:18:28:ST3_smx:INFO: Total # broken ch: 0
10:18:28:ST3_smx:INFO: List FAST: []
10:18:28:ST3_smx:INFO: List SLOW: []
10:18:28:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:18:28:febtest:INFO: 0-0 | XA-000-08-002-001-006-147-14 | 21.9 | 1195.1
10:18:28:febtest:INFO: 0-1 | XA-000-08-002-001-006-143-09 | 40.9 | 1130.0
10:18:29:febtest:INFO: 0-2 | XA-000-08-002-001-006-140-09 | 18.7 | 1206.9
10:18:29:febtest:INFO: 0-3 | XA-000-08-002-001-006-153-14 | 25.1 | 1195.1
10:18:29:febtest:INFO: 0-4 | XA-000-08-002-001-006-169-07 | 18.7 | 1206.9
10:18:29:febtest:INFO: 0-5 | XA-000-08-002-001-006-163-07 | 34.6 | 1171.5
10:18:30:febtest:INFO: 0-6 | XA-000-08-002-001-006-177-00 | 28.2 | 1189.2
10:18:30:febtest:INFO: 0-7 | XA-000-08-002-001-006-173-07 | 18.7 | 1224.5
10:18:30:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
10:18:34:ST3_smx:INFO: chip: 0-2 21.902970 C 1195.082160 mV
10:18:34:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
10:18:34:ST3_smx:INFO: Electrons
10:18:34:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
10:18:36:ST3_smx:INFO: ----> Checking Analog response
10:18:36:ST3_smx:INFO: ----> Checking broken channels
10:18:36:ST3_smx:INFO: Total # broken ch: 0
10:18:36:ST3_smx:INFO: List FAST: []
10:18:36:ST3_smx:INFO: List SLOW: []
10:18:36:ST3_smx:INFO: Holes
10:18:36:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
10:18:38:ST3_smx:INFO: ----> Checking Analog response
10:18:38:ST3_smx:INFO: ----> Checking broken channels
10:18:39:ST3_smx:INFO: Total # broken ch: 0
10:18:39:ST3_smx:INFO: List FAST: []
10:18:39:ST3_smx:INFO: List SLOW: []
10:18:39:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:18:39:febtest:INFO: 0-0 | XA-000-08-002-001-006-147-14 | 21.9 | 1189.2
10:18:39:febtest:INFO: 0-1 | XA-000-08-002-001-006-143-09 | 40.9 | 1130.0
10:18:39:febtest:INFO: 0-2 | XA-000-08-002-001-006-140-09 | 25.1 | 1189.2
10:18:39:febtest:INFO: 0-3 | XA-000-08-002-001-006-153-14 | 25.1 | 1195.1
10:18:40:febtest:INFO: 0-4 | XA-000-08-002-001-006-169-07 | 21.9 | 1206.9
10:18:40:febtest:INFO: 0-5 | XA-000-08-002-001-006-163-07 | 34.6 | 1165.6
10:18:40:febtest:INFO: 0-6 | XA-000-08-002-001-006-177-00 | 28.2 | 1183.3
10:18:40:febtest:INFO: 0-7 | XA-000-08-002-001-006-173-07 | 18.7 | 1224.5
10:18:41:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
10:18:44:ST3_smx:INFO: chip: 0-3 21.902970 C 1195.082160 mV
10:18:44:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
10:18:44:ST3_smx:INFO: Electrons
10:18:44:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
10:18:46:ST3_smx:INFO: ----> Checking Analog response
10:18:46:ST3_smx:INFO: ----> Checking broken channels
10:18:47:ST3_smx:INFO: Total # broken ch: 0
10:18:47:ST3_smx:INFO: List FAST: []
10:18:47:ST3_smx:INFO: List SLOW: []
10:18:47:ST3_smx:INFO: Holes
10:18:47:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
10:18:49:ST3_smx:INFO: ----> Checking Analog response
10:18:49:ST3_smx:INFO: ----> Checking broken channels
10:18:49:ST3_smx:INFO: Total # broken ch: 0
10:18:49:ST3_smx:INFO: List FAST: []
10:18:49:ST3_smx:INFO: List SLOW: []
10:18:49:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:18:49:febtest:INFO: 0-0 | XA-000-08-002-001-006-147-14 | 25.1 | 1195.1
10:18:49:febtest:INFO: 0-1 | XA-000-08-002-001-006-143-09 | 40.9 | 1130.0
10:18:50:febtest:INFO: 0-2 | XA-000-08-002-001-006-140-09 | 25.1 | 1189.2
10:18:50:febtest:INFO: 0-3 | XA-000-08-002-001-006-153-14 | 25.1 | 1189.2
10:18:50:febtest:INFO: 0-4 | XA-000-08-002-001-006-169-07 | 21.9 | 1206.9
10:18:50:febtest:INFO: 0-5 | XA-000-08-002-001-006-163-07 | 34.6 | 1165.6
10:18:51:febtest:INFO: 0-6 | XA-000-08-002-001-006-177-00 | 31.4 | 1183.3
10:18:51:febtest:INFO: 0-7 | XA-000-08-002-001-006-173-07 | 18.7 | 1224.5
10:18:51:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
10:18:55:ST3_smx:INFO: chip: 0-4 18.745682 C 1200.969315 mV
10:18:55:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
10:18:55:ST3_smx:INFO: Electrons
10:18:55:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
10:18:57:ST3_smx:INFO: ----> Checking Analog response
10:18:57:ST3_smx:INFO: ----> Checking broken channels
10:18:57:ST3_smx:INFO: Total # broken ch: 0
10:18:57:ST3_smx:INFO: List FAST: []
10:18:57:ST3_smx:INFO: List SLOW: []
10:18:57:ST3_smx:INFO: Holes
10:18:57:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
10:18:59:ST3_smx:INFO: ----> Checking Analog response
10:18:59:ST3_smx:INFO: ----> Checking broken channels
10:19:00:ST3_smx:INFO: Total # broken ch: 0
10:19:00:ST3_smx:INFO: List FAST: []
10:19:00:ST3_smx:INFO: List SLOW: []
10:19:00:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:19:00:febtest:INFO: 0-0 | XA-000-08-002-001-006-147-14 | 25.1 | 1189.2
10:19:00:febtest:INFO: 0-1 | XA-000-08-002-001-006-143-09 | 40.9 | 1130.0
10:19:00:febtest:INFO: 0-2 | XA-000-08-002-001-006-140-09 | 25.1 | 1189.2
10:19:00:febtest:INFO: 0-3 | XA-000-08-002-001-006-153-14 | 25.1 | 1195.1
10:19:01:febtest:INFO: 0-4 | XA-000-08-002-001-006-169-07 | 21.9 | 1195.1
10:19:01:febtest:INFO: 0-5 | XA-000-08-002-001-006-163-07 | 34.6 | 1165.6
10:19:01:febtest:INFO: 0-6 | XA-000-08-002-001-006-177-00 | 31.4 | 1183.3
10:19:01:febtest:INFO: 0-7 | XA-000-08-002-001-006-173-07 | 18.7 | 1224.5
10:19:02:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
10:19:05:ST3_smx:INFO: chip: 0-5 31.389742 C 1171.483840 mV
10:19:05:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
10:19:05:ST3_smx:INFO: Electrons
10:19:05:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
10:19:08:ST3_smx:INFO: ----> Checking Analog response
10:19:08:ST3_smx:INFO: ----> Checking broken channels
10:19:08:ST3_smx:INFO: Total # broken ch: 0
10:19:08:ST3_smx:INFO: List FAST: []
10:19:08:ST3_smx:INFO: List SLOW: []
10:19:08:ST3_smx:INFO: Holes
10:19:08:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
10:19:10:ST3_smx:INFO: ----> Checking Analog response
10:19:10:ST3_smx:INFO: ----> Checking broken channels
10:19:10:ST3_smx:INFO: Total # broken ch: 0
10:19:10:ST3_smx:INFO: List FAST: []
10:19:10:ST3_smx:INFO: List SLOW: []
10:19:10:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:19:10:febtest:INFO: 0-0 | XA-000-08-002-001-006-147-14 | 25.1 | 1189.2
10:19:11:febtest:INFO: 0-1 | XA-000-08-002-001-006-143-09 | 40.9 | 1124.0
10:19:11:febtest:INFO: 0-2 | XA-000-08-002-001-006-140-09 | 25.1 | 1189.2
10:19:11:febtest:INFO: 0-3 | XA-000-08-002-001-006-153-14 | 25.1 | 1189.2
10:19:11:febtest:INFO: 0-4 | XA-000-08-002-001-006-169-07 | 21.9 | 1201.0
10:19:11:febtest:INFO: 0-5 | XA-000-08-002-001-006-163-07 | 34.6 | 1165.6
10:19:12:febtest:INFO: 0-6 | XA-000-08-002-001-006-177-00 | 31.4 | 1183.3
10:19:12:febtest:INFO: 0-7 | XA-000-08-002-001-006-173-07 | 18.7 | 1224.5
10:19:12:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
10:19:16:ST3_smx:INFO: chip: 0-6 28.225000 C 1183.292940 mV
10:19:16:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
10:19:16:ST3_smx:INFO: Electrons
10:19:16:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
10:19:18:ST3_smx:INFO: ----> Checking Analog response
10:19:18:ST3_smx:INFO: ----> Checking broken channels
10:19:18:ST3_smx:INFO: Total # broken ch: 0
10:19:18:ST3_smx:INFO: List FAST: []
10:19:18:ST3_smx:INFO: List SLOW: []
10:19:18:ST3_smx:INFO: Holes
10:19:18:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
10:19:20:ST3_smx:INFO: ----> Checking Analog response
10:19:20:ST3_smx:INFO: ----> Checking broken channels
10:19:21:ST3_smx:INFO: Total # broken ch: 0
10:19:21:ST3_smx:INFO: List FAST: []
10:19:21:ST3_smx:INFO: List SLOW: []
10:19:21:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:19:21:febtest:INFO: 0-0 | XA-000-08-002-001-006-147-14 | 25.1 | 1189.2
10:19:21:febtest:INFO: 0-1 | XA-000-08-002-001-006-143-09 | 40.9 | 1130.0
10:19:21:febtest:INFO: 0-2 | XA-000-08-002-001-006-140-09 | 25.1 | 1183.3
10:19:22:febtest:INFO: 0-3 | XA-000-08-002-001-006-153-14 | 25.1 | 1189.2
10:19:22:febtest:INFO: 0-4 | XA-000-08-002-001-006-169-07 | 21.9 | 1195.1
10:19:22:febtest:INFO: 0-5 | XA-000-08-002-001-006-163-07 | 34.6 | 1165.6
10:19:22:febtest:INFO: 0-6 | XA-000-08-002-001-006-177-00 | 31.4 | 1177.4
10:19:22:febtest:INFO: 0-7 | XA-000-08-002-001-006-173-07 | 18.7 | 1224.5
10:19:23:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
10:19:27:ST3_smx:INFO: chip: 0-7 28.225000 C 1183.292940 mV
10:19:27:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
10:19:27:ST3_smx:INFO: Electrons
10:19:27:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
10:19:29:ST3_smx:INFO: ----> Checking Analog response
10:19:29:ST3_smx:INFO: ----> Checking broken channels
10:19:29:ST3_smx:INFO: Total # broken ch: 0
10:19:29:ST3_smx:INFO: List FAST: []
10:19:29:ST3_smx:INFO: List SLOW: []
10:19:29:ST3_smx:INFO: Holes
10:19:29:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
10:19:31:ST3_smx:INFO: ----> Checking Analog response
10:19:31:ST3_smx:INFO: ----> Checking broken channels
10:19:31:ST3_smx:INFO: Total # broken ch: 0
10:19:31:ST3_smx:INFO: List FAST: []
10:19:31:ST3_smx:INFO: List SLOW: []
10:19:31:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:19:31:febtest:INFO: 0-0 | XA-000-08-002-001-006-147-14 | 25.1 | 1189.2
10:19:32:febtest:INFO: 0-1 | XA-000-08-002-001-006-143-09 | 44.1 | 1124.0
10:19:32:febtest:INFO: 0-2 | XA-000-08-002-001-006-140-09 | 25.1 | 1183.3
10:19:32:febtest:INFO: 0-3 | XA-000-08-002-001-006-153-14 | 25.1 | 1189.2
10:19:32:febtest:INFO: 0-4 | XA-000-08-002-001-006-169-07 | 21.9 | 1195.1
10:19:33:febtest:INFO: 0-5 | XA-000-08-002-001-006-163-07 | 34.6 | 1165.6
10:19:33:febtest:INFO: 0-6 | XA-000-08-002-001-006-177-00 | 31.4 | 1177.4
10:19:33:febtest:INFO: 0-7 | XA-000-08-002-001-006-173-07 | 31.4 | 1177.4
############################################################
# S U M M A R Y #
############################################################
{'TEST_NAME': 'FEB-ASIC', 'TEST_DATE': '2023_08_28-10_17_55', 'OPERATOR': 'Oleksandr S.; ', 'PROJECT': 'Production', 'SITE': 'GSI', 'SETUP': 'GSI_TEST_SETUP_1', 'ASIC_ID': 'XA-000-08-002-001-006-173-07', 'FUSED_ID': 6359364699117611735, 'HW_ADDR': 7, 'VERS_NO': '2.2', 'CABLE_SET_ID': '', 'IC_TEMP': '0', 'VDDM': '0', 'AUX': '0', 'CSABIAS': '0', 'VDDM_INT': '0', 'ADC_Chi2': 0.0, 'ADC_NDF': 0, 'ADC_P0': 0.0, 'ADC_P1': 0.006824, 'ADC_P2': -2.485e-06, 'ADC_P0err': 0.001, 'ADC_P1err': 0.001, 'ADC_P2err': 1e-05, 'ADC_VREF_P': 58, 'ADC_VREF_N': 30, 'ADC_VREF_T': 128, 'ADC_VREF_TR': 122, 'THR2_GLB': 30, 'LOOP__PLS': 100, 'CALIB_PLS': 250, 'SnsLoop': 5, 'IFED': 31, 'CSA_BIAS': 15, 'CSA_Chi2': 0.0, 'CSA_NDF': 0, 'CSA_P0': 0.0, 'CSA_P1': 0.0, 'CSA_P2': 0.0, 'CSA_P0err': 0.0, 'CSA_P1err': 0.0, 'CSA_P2err': 0.0, 'CONF_FAIL_REG': 0, 'N_BROKEN_DISC': 0, 'N_BROKEN_FAST': '[]', 'N_BROKEN_SLOW': '[]', 'P_BROKEN_DISC': 0, 'P_BROKEN_FAST': '[]', 'P_BROKEN_SLOW': '[]', 'ASIC_QA_category': '', 'N_BROKEN_CABLE': 0, 'LIST_OF_BROKEN_CABLES': 0, 'VI_bInit': ['2.448', '1.6200', '1.846', '2.4680', '7.000', '1.5260', '7.000', '1.5260'], 'VI_aInit': ['0', '0', '0', '0', '0', '0'], 'VI_atEnd': ['0', '0', '0', '0', '0', '0'], 'AMP_CAL': 200, 'PlsLoop': 3, 'N_ANA_PRESENT': 'Analog response OK', 'N_DISC_FAIL_CH': 0, 'N_ANA_FAIL_CH': '0', 'P_ANA_PRESENT': 'Analog response OK', 'P_DISC_FAIL_CH': 0, 'P_ANA_FAIL_CH': '0'}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
10:19:37:ST3_Shared:INFO: /home/cbm/public_html/Production_LogDir//FEB/FEB_2013/B//TestDate_2023_08_28-10_17_55/