Go Back
FEB_2013 28.08.23 13:56:22
TextEdit.txt
13:56:20:smx_tester:INFO: Setting Elink clock mode to 160 MHz
13:56:22:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
13:56:22:ST3_Shared:INFO: --------------------------FEB-ASIC--------------------------
13:56:22:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
13:56:22:febtest:INFO: Tsting FEB with SN 2013
13:56:24:smx_tester:INFO: Scanning setup
13:56:24:elinks:INFO: Disabling clock on downlink 0
13:56:24:elinks:INFO: Disabling clock on downlink 1
13:56:24:elinks:INFO: Disabling clock on downlink 2
13:56:24:elinks:INFO: Disabling clock on downlink 3
13:56:24:elinks:INFO: Disabling clock on downlink 4
13:56:24:setup_element:INFO: Checking SOS, encoding_mode: SOS
13:56:24:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
13:56:24:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
13:56:24:elinks:INFO: Disabling clock on downlink 0
13:56:24:elinks:INFO: Disabling clock on downlink 1
13:56:24:elinks:INFO: Disabling clock on downlink 2
13:56:24:elinks:INFO: Disabling clock on downlink 3
13:56:24:elinks:INFO: Disabling clock on downlink 4
13:56:24:setup_element:INFO: Checking SOS, encoding_mode: SOS
13:56:24:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
13:56:24:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
13:56:24:elinks:INFO: Disabling clock on downlink 0
13:56:24:elinks:INFO: Disabling clock on downlink 1
13:56:24:elinks:INFO: Disabling clock on downlink 2
13:56:24:elinks:INFO: Disabling clock on downlink 3
13:56:24:elinks:INFO: Disabling clock on downlink 4
13:56:24:setup_element:INFO: Checking SOS, encoding_mode: SOS
13:56:24:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
13:56:24:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 16
13:56:24:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 17
13:56:24:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 18
13:56:24:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 19
13:56:24:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 20
13:56:24:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 21
13:56:24:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 22
13:56:24:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 23
13:56:24:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24
13:56:24:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25
13:56:24:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26
13:56:24:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27
13:56:24:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28
13:56:24:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29
13:56:24:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30
13:56:24:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31
13:56:24:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
13:56:24:elinks:INFO: Disabling clock on downlink 0
13:56:24:elinks:INFO: Disabling clock on downlink 1
13:56:24:elinks:INFO: Disabling clock on downlink 2
13:56:24:elinks:INFO: Disabling clock on downlink 3
13:56:24:elinks:INFO: Disabling clock on downlink 4
13:56:24:setup_element:INFO: Checking SOS, encoding_mode: SOS
13:56:24:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
13:56:24:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
13:56:24:elinks:INFO: Disabling clock on downlink 0
13:56:24:elinks:INFO: Disabling clock on downlink 1
13:56:24:elinks:INFO: Disabling clock on downlink 2
13:56:24:elinks:INFO: Disabling clock on downlink 3
13:56:24:elinks:INFO: Disabling clock on downlink 4
13:56:24:setup_element:INFO: Checking SOS, encoding_mode: SOS
13:56:24:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
13:56:24:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
13:56:24:setup_element:INFO: Scanning clock phase
13:56:25:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
13:56:25:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
13:56:25:setup_element:INFO: Clock phase scan results for group 0, downlink 2
13:56:25:setup_element:INFO: Eye window for uplink 16: X_______________________________________________________________________XXXXXXXX
Clock Delay: 36
13:56:25:setup_element:INFO: Eye window for uplink 17: X_______________________________________________________________________XXXXXXXX
Clock Delay: 36
13:56:25:setup_element:INFO: Eye window for uplink 18: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
13:56:25:setup_element:INFO: Eye window for uplink 19: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
13:56:25:setup_element:INFO: Eye window for uplink 20: ________________________________________________________________________XXXXXXXX
Clock Delay: 35
13:56:25:setup_element:INFO: Eye window for uplink 21: ________________________________________________________________________XXXXXXXX
Clock Delay: 35
13:56:25:setup_element:INFO: Eye window for uplink 22: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
13:56:25:setup_element:INFO: Eye window for uplink 23: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
13:56:25:setup_element:INFO: Eye window for uplink 24: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
13:56:25:setup_element:INFO: Eye window for uplink 25: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
13:56:25:setup_element:INFO: Eye window for uplink 26: ________________________________________________________________________________
Clock Delay: 40
13:56:25:setup_element:INFO: Eye window for uplink 27: ________________________________________________________________________________
Clock Delay: 40
13:56:25:setup_element:INFO: Eye window for uplink 28: ________________________________________________________________________________
Clock Delay: 40
13:56:25:setup_element:INFO: Eye window for uplink 29: ________________________________________________________________________________
Clock Delay: 40
13:56:25:setup_element:INFO: Eye window for uplink 30: XX________________________________________________________________________XXXXXX
Clock Delay: 37
13:56:25:setup_element:INFO: Eye window for uplink 31: XX________________________________________________________________________XXXXXX
Clock Delay: 37
13:56:25:setup_element:INFO: Setting the clock phase to 36 for group 0, downlink 2
13:56:25:setup_element:INFO: Scanning data phases
13:56:25:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
13:56:25:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
13:56:31:setup_element:INFO: Data phase scan results for group 0, downlink 2
13:56:31:setup_element:INFO: Eye window for uplink 16: XX____________________________________XX
Data delay found: 19
13:56:31:setup_element:INFO: Eye window for uplink 17: _________________________________XXXXX__
Data delay found: 15
13:56:31:setup_element:INFO: Eye window for uplink 18: X_________________________________XXXXX_
Data delay found: 17
13:56:31:setup_element:INFO: Eye window for uplink 19: ________________________________XXXX____
Data delay found: 13
13:56:31:setup_element:INFO: Eye window for uplink 20: ___________________________________XXXXX
Data delay found: 17
13:56:31:setup_element:INFO: Eye window for uplink 21: _________________________________XXXXXX_
Data delay found: 15
13:56:31:setup_element:INFO: Eye window for uplink 22: __________________________________XXXXX_
Data delay found: 16
13:56:31:setup_element:INFO: Eye window for uplink 23: ________________________________XXXXX___
Data delay found: 14
13:56:31:setup_element:INFO: Eye window for uplink 24: ____XXXXX_______________________________
Data delay found: 26
13:56:31:setup_element:INFO: Eye window for uplink 25: ______XXXXX_____________________________
Data delay found: 28
13:56:31:setup_element:INFO: Eye window for uplink 26: _____XXXXXX_____________________________
Data delay found: 27
13:56:31:setup_element:INFO: Eye window for uplink 27: ________XXXXXX__________________________
Data delay found: 30
13:56:31:setup_element:INFO: Eye window for uplink 28: _________XXXXXX_________________________
Data delay found: 31
13:56:31:setup_element:INFO: Eye window for uplink 29: ___________XXXXX________________________
Data delay found: 33
13:56:31:setup_element:INFO: Eye window for uplink 30: ________________XXXXXX__________________
Data delay found: 38
13:56:31:setup_element:INFO: Eye window for uplink 31: ______________XXXXX_X___________________
Data delay found: 37
13:56:31:setup_element:INFO: Setting the data phase to 19 for uplink 16
13:56:31:setup_element:INFO: Setting the data phase to 15 for uplink 17
13:56:31:setup_element:INFO: Setting the data phase to 17 for uplink 18
13:56:31:setup_element:INFO: Setting the data phase to 13 for uplink 19
13:56:31:setup_element:INFO: Setting the data phase to 17 for uplink 20
13:56:31:setup_element:INFO: Setting the data phase to 15 for uplink 21
13:56:31:setup_element:INFO: Setting the data phase to 16 for uplink 22
13:56:31:setup_element:INFO: Setting the data phase to 14 for uplink 23
13:56:31:setup_element:INFO: Setting the data phase to 26 for uplink 24
13:56:31:setup_element:INFO: Setting the data phase to 28 for uplink 25
13:56:31:setup_element:INFO: Setting the data phase to 27 for uplink 26
13:56:31:setup_element:INFO: Setting the data phase to 30 for uplink 27
13:56:31:setup_element:INFO: Setting the data phase to 31 for uplink 28
13:56:31:setup_element:INFO: Setting the data phase to 33 for uplink 29
13:56:31:setup_element:INFO: Setting the data phase to 38 for uplink 30
13:56:31:setup_element:INFO: Setting the data phase to 37 for uplink 31
13:56:31:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 36
Window Length: 69
Eye Windows:
Uplink 16: X_______________________________________________________________________XXXXXXXX
Uplink 17: X_______________________________________________________________________XXXXXXXX
Uplink 18: _______________________________________________________________________XXXXXXXX_
Uplink 19: _______________________________________________________________________XXXXXXXX_
Uplink 20: ________________________________________________________________________XXXXXXXX
Uplink 21: ________________________________________________________________________XXXXXXXX
Uplink 22: _______________________________________________________________________XXXXXXXX_
Uplink 23: _______________________________________________________________________XXXXXXXX_
Uplink 24: _______________________________________________________________________XXXXXXX__
Uplink 25: _______________________________________________________________________XXXXXXX__
Uplink 26: ________________________________________________________________________________
Uplink 27: ________________________________________________________________________________
Uplink 28: ________________________________________________________________________________
Uplink 29: ________________________________________________________________________________
Uplink 30: XX________________________________________________________________________XXXXXX
Uplink 31: XX________________________________________________________________________XXXXXX
Data phase characteristics:
Uplink 16:
Optimal Phase: 19
Window Length: 36
Eye Window: XX____________________________________XX
Uplink 17:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
Uplink 18:
Optimal Phase: 17
Window Length: 33
Eye Window: X_________________________________XXXXX_
Uplink 19:
Optimal Phase: 13
Window Length: 36
Eye Window: ________________________________XXXX____
Uplink 20:
Optimal Phase: 17
Window Length: 35
Eye Window: ___________________________________XXXXX
Uplink 21:
Optimal Phase: 15
Window Length: 34
Eye Window: _________________________________XXXXXX_
Uplink 22:
Optimal Phase: 16
Window Length: 35
Eye Window: __________________________________XXXXX_
Uplink 23:
Optimal Phase: 14
Window Length: 35
Eye Window: ________________________________XXXXX___
Uplink 24:
Optimal Phase: 26
Window Length: 35
Eye Window: ____XXXXX_______________________________
Uplink 25:
Optimal Phase: 28
Window Length: 35
Eye Window: ______XXXXX_____________________________
Uplink 26:
Optimal Phase: 27
Window Length: 34
Eye Window: _____XXXXXX_____________________________
Uplink 27:
Optimal Phase: 30
Window Length: 34
Eye Window: ________XXXXXX__________________________
Uplink 28:
Optimal Phase: 31
Window Length: 34
Eye Window: _________XXXXXX_________________________
Uplink 29:
Optimal Phase: 33
Window Length: 35
Eye Window: ___________XXXXX________________________
Uplink 30:
Optimal Phase: 38
Window Length: 34
Eye Window: ________________XXXXXX__________________
Uplink 31:
Optimal Phase: 37
Window Length: 33
Eye Window: ______________XXXXX_X___________________
]
13:56:31:setup_element:INFO: Beginning SMX ASICs map scan
13:56:31:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
13:56:31:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
13:56:31:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
13:56:31:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
13:56:31:uplink:INFO: Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
13:56:31:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 23
13:56:31:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 22
13:56:31:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 30
13:56:31:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 31
13:56:31:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 21
13:56:31:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 20
13:56:31:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28
13:56:31:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 29
13:56:31:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 19
13:56:32:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 18
13:56:32:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26
13:56:32:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 27
13:56:32:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 17
13:56:32:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 16
13:56:32:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 24
13:56:32:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 25
13:56:33:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 23), (1, 22)
ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
ASIC address 0x2: (ASIC uplink, uplink): (0, 21), (1, 20)
ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
ASIC address 0x4: (ASIC uplink, uplink): (0, 19), (1, 18)
ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
ASIC address 0x6: (ASIC uplink, uplink): (0, 17), (1, 16)
ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
Clock Phase Characteristic:
Optimal Phase: 36
Window Length: 69
Eye Windows:
Uplink 16: X_______________________________________________________________________XXXXXXXX
Uplink 17: X_______________________________________________________________________XXXXXXXX
Uplink 18: _______________________________________________________________________XXXXXXXX_
Uplink 19: _______________________________________________________________________XXXXXXXX_
Uplink 20: ________________________________________________________________________XXXXXXXX
Uplink 21: ________________________________________________________________________XXXXXXXX
Uplink 22: _______________________________________________________________________XXXXXXXX_
Uplink 23: _______________________________________________________________________XXXXXXXX_
Uplink 24: _______________________________________________________________________XXXXXXX__
Uplink 25: _______________________________________________________________________XXXXXXX__
Uplink 26: ________________________________________________________________________________
Uplink 27: ________________________________________________________________________________
Uplink 28: ________________________________________________________________________________
Uplink 29: ________________________________________________________________________________
Uplink 30: XX________________________________________________________________________XXXXXX
Uplink 31: XX________________________________________________________________________XXXXXX
Data phase characteristics:
Uplink 16:
Optimal Phase: 19
Window Length: 36
Eye Window: XX____________________________________XX
Uplink 17:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
Uplink 18:
Optimal Phase: 17
Window Length: 33
Eye Window: X_________________________________XXXXX_
Uplink 19:
Optimal Phase: 13
Window Length: 36
Eye Window: ________________________________XXXX____
Uplink 20:
Optimal Phase: 17
Window Length: 35
Eye Window: ___________________________________XXXXX
Uplink 21:
Optimal Phase: 15
Window Length: 34
Eye Window: _________________________________XXXXXX_
Uplink 22:
Optimal Phase: 16
Window Length: 35
Eye Window: __________________________________XXXXX_
Uplink 23:
Optimal Phase: 14
Window Length: 35
Eye Window: ________________________________XXXXX___
Uplink 24:
Optimal Phase: 26
Window Length: 35
Eye Window: ____XXXXX_______________________________
Uplink 25:
Optimal Phase: 28
Window Length: 35
Eye Window: ______XXXXX_____________________________
Uplink 26:
Optimal Phase: 27
Window Length: 34
Eye Window: _____XXXXXX_____________________________
Uplink 27:
Optimal Phase: 30
Window Length: 34
Eye Window: ________XXXXXX__________________________
Uplink 28:
Optimal Phase: 31
Window Length: 34
Eye Window: _________XXXXXX_________________________
Uplink 29:
Optimal Phase: 33
Window Length: 35
Eye Window: ___________XXXXX________________________
Uplink 30:
Optimal Phase: 38
Window Length: 34
Eye Window: ________________XXXXXX__________________
Uplink 31:
Optimal Phase: 37
Window Length: 33
Eye Window: ______________XXXXX_X___________________
13:56:33:setup_element:INFO: Performing Elink synchronization
13:56:33:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
13:56:33:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
13:56:33:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
13:56:33:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
13:56:33:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2
13:56:33:uplink:INFO: Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
13:56:34:ST3_emu:INFO: Number of chips: 8
13:56:34:ST3_emu:INFO: Chip address: 0x0
13:56:34:ST3_emu:INFO: Chip address: 0x1
13:56:34:ST3_emu:INFO: Chip address: 0x2
13:56:34:ST3_emu:INFO: Chip address: 0x3
13:56:34:ST3_emu:INFO: Chip address: 0x4
13:56:34:ST3_emu:INFO: Chip address: 0x5
13:56:34:ST3_emu:INFO: Chip address: 0x6
13:56:34:ST3_emu:INFO: Chip address: 0x7
13:56:34:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
13:56:34:febtest:INFO: 0-0 | XA-000-08-002-001-006-147-14 | 18.7 | 1230.3
13:56:35:febtest:INFO: 0-1 | XA-000-08-002-001-006-143-09 | 50.4 | 1118.1
13:56:35:febtest:INFO: 0-2 | XA-000-08-002-001-006-140-09 | 25.1 | 1206.9
13:56:35:febtest:INFO: 0-3 | XA-000-08-002-001-006-153-14 | 25.1 | 1201.0
13:56:35:febtest:INFO: 0-4 | XA-000-08-002-001-006-169-07 | 21.9 | 1212.7
13:56:36:febtest:INFO: 0-5 | XA-000-08-002-001-006-163-07 | 34.6 | 1171.5
13:56:36:febtest:INFO: 0-6 | XA-000-08-002-001-006-177-00 | 31.4 | 1189.2
13:56:36:febtest:INFO: 0-7 | XA-000-08-002-001-006-173-07 | 12.4 | 1247.9
13:56:36:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
13:56:40:ST3_smx:INFO: chip: 0-0 21.902970 C 1206.851500 mV
13:56:40:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
13:56:40:ST3_smx:INFO: Electrons
13:56:40:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
13:56:42:ST3_smx:INFO: ----> Checking Analog response
13:56:42:ST3_smx:INFO: ----> Checking broken channels
13:56:42:ST3_smx:INFO: Total # broken ch: 0
13:56:42:ST3_smx:INFO: List FAST: []
13:56:42:ST3_smx:INFO: List SLOW: []
13:56:42:ST3_smx:INFO: Holes
13:56:42:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
13:56:44:ST3_smx:INFO: ----> Checking Analog response
13:56:44:ST3_smx:INFO: ----> Checking broken channels
13:56:44:ST3_smx:INFO: Total # broken ch: 0
13:56:44:ST3_smx:INFO: List FAST: []
13:56:44:ST3_smx:INFO: List SLOW: []
13:56:44:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
13:56:45:febtest:INFO: 0-0 | XA-000-08-002-001-006-147-14 | 21.9 | 1195.1
13:56:45:febtest:INFO: 0-1 | XA-000-08-002-001-006-143-09 | 50.4 | 1118.1
13:56:45:febtest:INFO: 0-2 | XA-000-08-002-001-006-140-09 | 25.1 | 1201.0
13:56:45:febtest:INFO: 0-3 | XA-000-08-002-001-006-153-14 | 25.1 | 1201.0
13:56:46:febtest:INFO: 0-4 | XA-000-08-002-001-006-169-07 | 21.9 | 1212.7
13:56:46:febtest:INFO: 0-5 | XA-000-08-002-001-006-163-07 | 34.6 | 1171.5
13:56:46:febtest:INFO: 0-6 | XA-000-08-002-001-006-177-00 | 31.4 | 1189.2
13:56:46:febtest:INFO: 0-7 | XA-000-08-002-001-006-173-07 | 12.4 | 1247.9
13:56:47:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
13:56:50:ST3_smx:INFO: chip: 0-1 40.898880 C 1135.937260 mV
13:56:50:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
13:56:50:ST3_smx:INFO: Electrons
13:56:50:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
13:56:52:ST3_smx:INFO: ----> Checking Analog response
13:56:52:ST3_smx:INFO: ----> Checking broken channels
13:56:53:ST3_smx:INFO: Total # broken ch: 0
13:56:53:ST3_smx:INFO: List FAST: []
13:56:53:ST3_smx:INFO: List SLOW: []
13:56:53:ST3_smx:INFO: Holes
13:56:53:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
13:56:55:ST3_smx:INFO: ----> Checking Analog response
13:56:55:ST3_smx:INFO: ----> Checking broken channels
13:56:55:ST3_smx:INFO: Total # broken ch: 0
13:56:55:ST3_smx:INFO: List FAST: []
13:56:55:ST3_smx:INFO: List SLOW: []
13:56:55:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
13:56:55:febtest:INFO: 0-0 | XA-000-08-002-001-006-147-14 | 25.1 | 1201.0
13:56:55:febtest:INFO: 0-1 | XA-000-08-002-001-006-143-09 | 44.1 | 1130.0
13:56:56:febtest:INFO: 0-2 | XA-000-08-002-001-006-140-09 | 25.1 | 1201.0
13:56:56:febtest:INFO: 0-3 | XA-000-08-002-001-006-153-14 | 28.2 | 1195.1
13:56:56:febtest:INFO: 0-4 | XA-000-08-002-001-006-169-07 | 21.9 | 1212.7
13:56:56:febtest:INFO: 0-5 | XA-000-08-002-001-006-163-07 | 37.7 | 1171.5
13:56:57:febtest:INFO: 0-6 | XA-000-08-002-001-006-177-00 | 31.4 | 1189.2
13:56:57:febtest:INFO: 0-7 | XA-000-08-002-001-006-173-07 | 15.6 | 1247.9
13:56:57:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
13:57:00:ST3_smx:INFO: chip: 0-2 18.745682 C 1206.851500 mV
13:57:00:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
13:57:00:ST3_smx:INFO: Electrons
13:57:00:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
13:57:02:ST3_smx:INFO: ----> Checking Analog response
13:57:02:ST3_smx:INFO: ----> Checking broken channels
13:57:03:ST3_smx:INFO: Total # broken ch: 0
13:57:03:ST3_smx:INFO: List FAST: []
13:57:03:ST3_smx:INFO: List SLOW: []
13:57:03:ST3_smx:INFO: Holes
13:57:03:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
13:57:05:ST3_smx:INFO: ----> Checking Analog response
13:57:05:ST3_smx:INFO: ----> Checking broken channels
13:57:05:ST3_smx:INFO: Total # broken ch: 0
13:57:05:ST3_smx:INFO: List FAST: []
13:57:05:ST3_smx:INFO: List SLOW: []
13:57:05:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
13:57:05:febtest:INFO: 0-0 | XA-000-08-002-001-006-147-14 | 21.9 | 1201.0
13:57:05:febtest:INFO: 0-1 | XA-000-08-002-001-006-143-09 | 40.9 | 1130.0
13:57:06:febtest:INFO: 0-2 | XA-000-08-002-001-006-140-09 | 21.9 | 1201.0
13:57:06:febtest:INFO: 0-3 | XA-000-08-002-001-006-153-14 | 25.1 | 1195.1
13:57:06:febtest:INFO: 0-4 | XA-000-08-002-001-006-169-07 | 21.9 | 1212.7
13:57:06:febtest:INFO: 0-5 | XA-000-08-002-001-006-163-07 | 37.7 | 1165.6
13:57:06:febtest:INFO: 0-6 | XA-000-08-002-001-006-177-00 | 31.4 | 1183.3
13:57:07:febtest:INFO: 0-7 | XA-000-08-002-001-006-173-07 | 15.6 | 1247.9
13:57:07:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
13:57:11:ST3_smx:INFO: chip: 0-3 21.902970 C 1200.969315 mV
13:57:11:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
13:57:11:ST3_smx:INFO: Electrons
13:57:11:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
13:57:13:ST3_smx:INFO: ----> Checking Analog response
13:57:13:ST3_smx:INFO: ----> Checking broken channels
13:57:13:ST3_smx:INFO: Total # broken ch: 0
13:57:13:ST3_smx:INFO: List FAST: []
13:57:13:ST3_smx:INFO: List SLOW: []
13:57:13:ST3_smx:INFO: Holes
13:57:13:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
13:57:15:ST3_smx:INFO: ----> Checking Analog response
13:57:15:ST3_smx:INFO: ----> Checking broken channels
13:57:15:ST3_smx:INFO: Total # broken ch: 0
13:57:15:ST3_smx:INFO: List FAST: []
13:57:15:ST3_smx:INFO: List SLOW: []
13:57:15:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
13:57:15:febtest:INFO: 0-0 | XA-000-08-002-001-006-147-14 | 21.9 | 1201.0
13:57:16:febtest:INFO: 0-1 | XA-000-08-002-001-006-143-09 | 40.9 | 1130.0
13:57:16:febtest:INFO: 0-2 | XA-000-08-002-001-006-140-09 | 21.9 | 1201.0
13:57:16:febtest:INFO: 0-3 | XA-000-08-002-001-006-153-14 | 25.1 | 1195.1
13:57:16:febtest:INFO: 0-4 | XA-000-08-002-001-006-169-07 | 21.9 | 1212.7
13:57:17:febtest:INFO: 0-5 | XA-000-08-002-001-006-163-07 | 34.6 | 1171.5
13:57:17:febtest:INFO: 0-6 | XA-000-08-002-001-006-177-00 | 31.4 | 1183.3
13:57:17:febtest:INFO: 0-7 | XA-000-08-002-001-006-173-07 | 15.6 | 1242.0
13:57:17:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
13:57:21:ST3_smx:INFO: chip: 0-4 18.745682 C 1206.851500 mV
13:57:21:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
13:57:21:ST3_smx:INFO: Electrons
13:57:21:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
13:57:23:ST3_smx:INFO: ----> Checking Analog response
13:57:23:ST3_smx:INFO: ----> Checking broken channels
13:57:23:ST3_smx:INFO: Total # broken ch: 0
13:57:23:ST3_smx:INFO: List FAST: []
13:57:23:ST3_smx:INFO: List SLOW: []
13:57:23:ST3_smx:INFO: Holes
13:57:23:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
13:57:25:ST3_smx:INFO: ----> Checking Analog response
13:57:25:ST3_smx:INFO: ----> Checking broken channels
13:57:25:ST3_smx:INFO: Total # broken ch: 0
13:57:25:ST3_smx:INFO: List FAST: []
13:57:25:ST3_smx:INFO: List SLOW: []
13:57:25:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
13:57:26:febtest:INFO: 0-0 | XA-000-08-002-001-006-147-14 | 21.9 | 1195.1
13:57:26:febtest:INFO: 0-1 | XA-000-08-002-001-006-143-09 | 44.1 | 1130.0
13:57:26:febtest:INFO: 0-2 | XA-000-08-002-001-006-140-09 | 21.9 | 1201.0
13:57:26:febtest:INFO: 0-3 | XA-000-08-002-001-006-153-14 | 25.1 | 1195.1
13:57:26:febtest:INFO: 0-4 | XA-000-08-002-001-006-169-07 | 21.9 | 1201.0
13:57:27:febtest:INFO: 0-5 | XA-000-08-002-001-006-163-07 | 37.7 | 1165.6
13:57:27:febtest:INFO: 0-6 | XA-000-08-002-001-006-177-00 | 31.4 | 1183.3
13:57:27:febtest:INFO: 0-7 | XA-000-08-002-001-006-173-07 | 15.6 | 1247.9
13:57:27:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
13:57:31:ST3_smx:INFO: chip: 0-5 31.389742 C 1171.483840 mV
13:57:31:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
13:57:31:ST3_smx:INFO: Electrons
13:57:31:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
13:57:33:ST3_smx:INFO: ----> Checking Analog response
13:57:33:ST3_smx:INFO: ----> Checking broken channels
13:57:33:ST3_smx:INFO: Total # broken ch: 0
13:57:33:ST3_smx:INFO: List FAST: []
13:57:33:ST3_smx:INFO: List SLOW: []
13:57:33:ST3_smx:INFO: Holes
13:57:33:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
13:57:35:ST3_smx:INFO: ----> Checking Analog response
13:57:35:ST3_smx:INFO: ----> Checking broken channels
13:57:36:ST3_smx:INFO: Total # broken ch: 0
13:57:36:ST3_smx:INFO: List FAST: []
13:57:36:ST3_smx:INFO: List SLOW: []
13:57:36:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
13:57:36:febtest:INFO: 0-0 | XA-000-08-002-001-006-147-14 | 21.9 | 1195.1
13:57:36:febtest:INFO: 0-1 | XA-000-08-002-001-006-143-09 | 40.9 | 1130.0
13:57:36:febtest:INFO: 0-2 | XA-000-08-002-001-006-140-09 | 21.9 | 1201.0
13:57:36:febtest:INFO: 0-3 | XA-000-08-002-001-006-153-14 | 25.1 | 1195.1
13:57:37:febtest:INFO: 0-4 | XA-000-08-002-001-006-169-07 | 21.9 | 1201.0
13:57:37:febtest:INFO: 0-5 | XA-000-08-002-001-006-163-07 | 34.6 | 1165.6
13:57:37:febtest:INFO: 0-6 | XA-000-08-002-001-006-177-00 | 31.4 | 1183.3
13:57:37:febtest:INFO: 0-7 | XA-000-08-002-001-006-173-07 | 15.6 | 1242.0
13:57:37:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
13:57:41:ST3_smx:INFO: chip: 0-6 28.225000 C 1183.292940 mV
13:57:41:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
13:57:41:ST3_smx:INFO: Electrons
13:57:41:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
13:57:44:ST3_smx:INFO: ----> Checking Analog response
13:57:44:ST3_smx:INFO: ----> Checking broken channels
13:57:44:ST3_smx:INFO: Total # broken ch: 0
13:57:44:ST3_smx:INFO: List FAST: []
13:57:44:ST3_smx:INFO: List SLOW: []
13:57:44:ST3_smx:INFO: Holes
13:57:44:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
13:57:46:ST3_smx:INFO: ----> Checking Analog response
13:57:46:ST3_smx:INFO: ----> Checking broken channels
13:57:46:ST3_smx:INFO: Total # broken ch: 0
13:57:46:ST3_smx:INFO: List FAST: []
13:57:46:ST3_smx:INFO: List SLOW: []
13:57:46:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
13:57:46:febtest:INFO: 0-0 | XA-000-08-002-001-006-147-14 | 21.9 | 1195.1
13:57:47:febtest:INFO: 0-1 | XA-000-08-002-001-006-143-09 | 40.9 | 1130.0
13:57:47:febtest:INFO: 0-2 | XA-000-08-002-001-006-140-09 | 21.9 | 1201.0
13:57:47:febtest:INFO: 0-3 | XA-000-08-002-001-006-153-14 | 25.1 | 1195.1
13:57:47:febtest:INFO: 0-4 | XA-000-08-002-001-006-169-07 | 21.9 | 1201.0
13:57:48:febtest:INFO: 0-5 | XA-000-08-002-001-006-163-07 | 34.6 | 1165.6
13:57:48:febtest:INFO: 0-6 | XA-000-08-002-001-006-177-00 | 28.2 | 1177.4
13:57:48:febtest:INFO: 0-7 | XA-000-08-002-001-006-173-07 | 15.6 | 1242.0
13:57:48:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
13:57:52:ST3_smx:INFO: chip: 0-7 28.225000 C 1183.292940 mV
13:57:52:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
13:57:52:ST3_smx:INFO: Electrons
13:57:52:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
13:57:55:ST3_smx:INFO: ----> Checking Analog response
13:57:55:ST3_smx:INFO: ----> Checking broken channels
13:57:55:ST3_smx:INFO: Total # broken ch: 0
13:57:55:ST3_smx:INFO: List FAST: []
13:57:55:ST3_smx:INFO: List SLOW: []
13:57:55:ST3_smx:INFO: Holes
13:57:55:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
13:57:57:ST3_smx:INFO: ----> Checking Analog response
13:57:57:ST3_smx:INFO: ----> Checking broken channels
13:57:57:ST3_smx:INFO: Total # broken ch: 0
13:57:57:ST3_smx:INFO: List FAST: []
13:57:57:ST3_smx:INFO: List SLOW: []
13:57:57:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
13:57:58:febtest:INFO: 0-0 | XA-000-08-002-001-006-147-14 | 25.1 | 1195.1
13:57:58:febtest:INFO: 0-1 | XA-000-08-002-001-006-143-09 | 40.9 | 1130.0
13:57:58:febtest:INFO: 0-2 | XA-000-08-002-001-006-140-09 | 21.9 | 1201.0
13:57:58:febtest:INFO: 0-3 | XA-000-08-002-001-006-153-14 | 25.1 | 1189.2
13:57:59:febtest:INFO: 0-4 | XA-000-08-002-001-006-169-07 | 21.9 | 1201.0
13:57:59:febtest:INFO: 0-5 | XA-000-08-002-001-006-163-07 | 34.6 | 1165.6
13:57:59:febtest:INFO: 0-6 | XA-000-08-002-001-006-177-00 | 31.4 | 1177.4
13:57:59:febtest:INFO: 0-7 | XA-000-08-002-001-006-173-07 | 31.4 | 1177.4
############################################################
# S U M M A R Y #
############################################################
{'TEST_NAME': 'FEB-ASIC', 'TEST_DATE': '2023_08_28-13_56_22', 'OPERATOR': 'Oleksandr S.; ', 'PROJECT': 'Production', 'SITE': 'GSI', 'SETUP': 'GSI_TEST_SETUP_1', 'ASIC_ID': 'XA-000-08-002-001-006-173-07', 'FUSED_ID': 6359364699117611735, 'HW_ADDR': 7, 'VERS_NO': '2.2', 'CABLE_SET_ID': '', 'IC_TEMP': '0', 'VDDM': '0', 'AUX': '0', 'CSABIAS': '0', 'VDDM_INT': '0', 'ADC_Chi2': 0.0, 'ADC_NDF': 0, 'ADC_P0': 0.0, 'ADC_P1': 0.006824, 'ADC_P2': -2.485e-06, 'ADC_P0err': 0.001, 'ADC_P1err': 0.001, 'ADC_P2err': 1e-05, 'ADC_VREF_P': 58, 'ADC_VREF_N': 30, 'ADC_VREF_T': 128, 'ADC_VREF_TR': 122, 'THR2_GLB': 30, 'LOOP__PLS': 100, 'CALIB_PLS': 250, 'SnsLoop': 5, 'IFED': 31, 'CSA_BIAS': 15, 'CSA_Chi2': 0.0, 'CSA_NDF': 0, 'CSA_P0': 0.0, 'CSA_P1': 0.0, 'CSA_P2': 0.0, 'CSA_P0err': 0.0, 'CSA_P1err': 0.0, 'CSA_P2err': 0.0, 'CONF_FAIL_REG': 0, 'N_BROKEN_DISC': 0, 'N_BROKEN_FAST': '[]', 'N_BROKEN_SLOW': '[]', 'P_BROKEN_DISC': 0, 'P_BROKEN_FAST': '[]', 'P_BROKEN_SLOW': '[]', 'ASIC_QA_category': '', 'N_BROKEN_CABLE': 0, 'LIST_OF_BROKEN_CABLES': 0, 'VI_bInit': ['2.448', '1.5390', '1.846', '2.4220', '7.001', '1.5370', '7.001', '1.5370'], 'VI_aInit': ['2.450', '1.9790', '1.850', '1.4300', '7.000', '1.5410', '7.000', '1.5410'], 'VI_atEnd': ['0', '0', '0', '0', '0', '0'], 'AMP_CAL': 200, 'PlsLoop': 3, 'N_ANA_PRESENT': 'Analog response OK', 'N_DISC_FAIL_CH': 0, 'N_ANA_FAIL_CH': '0', 'P_ANA_PRESENT': 'Analog response OK', 'P_DISC_FAIL_CH': 0, 'P_ANA_FAIL_CH': '0'}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
13:58:01:ST3_Shared:INFO: /home/cbm/public_html/Production_LogDir//FEB/FEB_2013/B//TestDate_2023_08_28-13_56_22/
13:58:01:ST3_Shared:WARNING: report/cDist_0.png
13:58:01:ST3_Shared:WARNING: report/cDist_0.root
13:58:01:ST3_Shared:WARNING: report/cDist_1.png
13:58:01:ST3_Shared:WARNING: report/cDist_1.root
13:58:01:ST3_Shared:WARNING: report/cDist_2.png
13:58:01:ST3_Shared:WARNING: report/cDist_2.root
13:58:01:ST3_Shared:WARNING: report/cDist_3.png
13:58:01:ST3_Shared:WARNING: report/cDist_3.root
13:58:01:ST3_Shared:WARNING: report/cDist_4.png
13:58:01:ST3_Shared:WARNING: report/cDist_4.root
13:58:01:ST3_Shared:WARNING: report/cDist_5.png
13:58:01:ST3_Shared:WARNING: report/cDist_5.root