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FEB_2013 09.10.23 15:43:45
TextEdit.txt
15:42:25:ST3_hmp4040:INFO: HAMEG,HMP2030,017836163,HW50010002/SW2.30
15:42:26:febtest:INFO: FEB8.2 selected
15:42:26:smx_tester:INFO: Setting Elink clock mode to 160 MHz
15:42:26:febtest:INFO: FEB8.2 selected
15:42:26:smx_tester:INFO: Setting Elink clock mode to 160 MHz
15:43:45:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
15:43:45:ST3_Shared:INFO: --------------------------FEB-ASIC--------------------------
15:43:45:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
15:43:45:febtest:INFO: Tsting FEB with SN 2013
15:43:47:smx_tester:INFO: Scanning setup
15:43:47:elinks:INFO: Disabling clock on downlink 0
15:43:47:elinks:INFO: Disabling clock on downlink 1
15:43:47:elinks:INFO: Disabling clock on downlink 2
15:43:47:elinks:INFO: Disabling clock on downlink 3
15:43:47:elinks:INFO: Disabling clock on downlink 4
15:43:47:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:43:47:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
15:43:47:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:43:47:elinks:INFO: Disabling clock on downlink 0
15:43:47:elinks:INFO: Disabling clock on downlink 1
15:43:47:elinks:INFO: Disabling clock on downlink 2
15:43:47:elinks:INFO: Disabling clock on downlink 3
15:43:47:elinks:INFO: Disabling clock on downlink 4
15:43:47:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:43:47:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
15:43:47:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:43:47:elinks:INFO: Disabling clock on downlink 0
15:43:47:elinks:INFO: Disabling clock on downlink 1
15:43:47:elinks:INFO: Disabling clock on downlink 2
15:43:47:elinks:INFO: Disabling clock on downlink 3
15:43:47:elinks:INFO: Disabling clock on downlink 4
15:43:47:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:43:47:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:43:47:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 16
15:43:47:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 17
15:43:47:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 18
15:43:47:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 19
15:43:47:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 20
15:43:47:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 21
15:43:47:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 22
15:43:47:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 23
15:43:47:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24
15:43:47:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25
15:43:47:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26
15:43:47:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27
15:43:47:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28
15:43:47:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29
15:43:47:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30
15:43:47:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31
15:43:47:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:43:47:elinks:INFO: Disabling clock on downlink 0
15:43:47:elinks:INFO: Disabling clock on downlink 1
15:43:47:elinks:INFO: Disabling clock on downlink 2
15:43:47:elinks:INFO: Disabling clock on downlink 3
15:43:47:elinks:INFO: Disabling clock on downlink 4
15:43:47:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:43:47:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
15:43:47:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:43:47:elinks:INFO: Disabling clock on downlink 0
15:43:47:elinks:INFO: Disabling clock on downlink 1
15:43:47:elinks:INFO: Disabling clock on downlink 2
15:43:47:elinks:INFO: Disabling clock on downlink 3
15:43:47:elinks:INFO: Disabling clock on downlink 4
15:43:47:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:43:47:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
15:43:47:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:43:48:setup_element:INFO: Scanning clock phase
15:43:48:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:43:48:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
15:43:48:setup_element:INFO: Clock phase scan results for group 0, downlink 2
15:43:48:setup_element:INFO: Eye window for uplink 16: ________________________________________________________________________XXXXXXXX
Clock Delay: 35
15:43:48:setup_element:INFO: Eye window for uplink 17: ________________________________________________________________________XXXXXXXX
Clock Delay: 35
15:43:48:setup_element:INFO: Eye window for uplink 18: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
15:43:48:setup_element:INFO: Eye window for uplink 19: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
15:43:48:setup_element:INFO: Eye window for uplink 20: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
15:43:48:setup_element:INFO: Eye window for uplink 21: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
15:43:48:setup_element:INFO: Eye window for uplink 22: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
15:43:48:setup_element:INFO: Eye window for uplink 23: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
15:43:48:setup_element:INFO: Eye window for uplink 24: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
15:43:48:setup_element:INFO: Eye window for uplink 25: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
15:43:48:setup_element:INFO: Eye window for uplink 26: _______________________________________________________________________XXXXXXXXX
Clock Delay: 35
15:43:48:setup_element:INFO: Eye window for uplink 27: _______________________________________________________________________XXXXXXXXX
Clock Delay: 35
15:43:48:setup_element:INFO: Eye window for uplink 28: ________________________________________________________________________________
Clock Delay: 40
15:43:48:setup_element:INFO: Eye window for uplink 29: ________________________________________________________________________________
Clock Delay: 40
15:43:48:setup_element:INFO: Eye window for uplink 30: X_________________________________________________________________________XXXXXX
Clock Delay: 37
15:43:48:setup_element:INFO: Eye window for uplink 31: X_________________________________________________________________________XXXXXX
Clock Delay: 37
15:43:48:setup_element:INFO: Setting the clock phase to 35 for group 0, downlink 2
15:43:48:setup_element:INFO: Scanning data phases
15:43:48:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:43:48:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
15:43:54:setup_element:INFO: Data phase scan results for group 0, downlink 2
15:43:54:setup_element:INFO: Eye window for uplink 16: XX___________________________________XXX
Data delay found: 19
15:43:54:setup_element:INFO: Eye window for uplink 17: _________________________________XXXXX__
Data delay found: 15
15:43:54:setup_element:INFO: Eye window for uplink 18: X_________________________________XXXXX_
Data delay found: 17
15:43:54:setup_element:INFO: Eye window for uplink 19: ________________________________XXXX____
Data delay found: 13
15:43:54:setup_element:INFO: Eye window for uplink 20: X__________________________________XXXXX
Data delay found: 17
15:43:54:setup_element:INFO: Eye window for uplink 21: __________________________________XXXXX_
Data delay found: 16
15:43:54:setup_element:INFO: Eye window for uplink 22: X_________________________________XXXXX_
Data delay found: 17
15:43:54:setup_element:INFO: Eye window for uplink 23: _________________________________XXXX___
Data delay found: 14
15:43:54:setup_element:INFO: Eye window for uplink 24: ____XXXXX_______________________________
Data delay found: 26
15:43:54:setup_element:INFO: Eye window for uplink 25: ________XXXXX___________________________
Data delay found: 30
15:43:54:setup_element:INFO: Eye window for uplink 26: ______XXXXX_____________________________
Data delay found: 28
15:43:54:setup_element:INFO: Eye window for uplink 27: ________XXXXXXX_________________________
Data delay found: 31
15:43:54:setup_element:INFO: Eye window for uplink 28: __________XXXXX_________________________
Data delay found: 32
15:43:54:setup_element:INFO: Eye window for uplink 29: ___________XXXXX________________________
Data delay found: 33
15:43:54:setup_element:INFO: Eye window for uplink 30: ________________XXXXXX__________________
Data delay found: 38
15:43:54:setup_element:INFO: Eye window for uplink 31: ______________XXXXXXX___________________
Data delay found: 37
15:43:54:setup_element:INFO: Setting the data phase to 19 for uplink 16
15:43:54:setup_element:INFO: Setting the data phase to 15 for uplink 17
15:43:54:setup_element:INFO: Setting the data phase to 17 for uplink 18
15:43:54:setup_element:INFO: Setting the data phase to 13 for uplink 19
15:43:54:setup_element:INFO: Setting the data phase to 17 for uplink 20
15:43:54:setup_element:INFO: Setting the data phase to 16 for uplink 21
15:43:54:setup_element:INFO: Setting the data phase to 17 for uplink 22
15:43:54:setup_element:INFO: Setting the data phase to 14 for uplink 23
15:43:54:setup_element:INFO: Setting the data phase to 26 for uplink 24
15:43:54:setup_element:INFO: Setting the data phase to 30 for uplink 25
15:43:54:setup_element:INFO: Setting the data phase to 28 for uplink 26
15:43:54:setup_element:INFO: Setting the data phase to 31 for uplink 27
15:43:54:setup_element:INFO: Setting the data phase to 32 for uplink 28
15:43:54:setup_element:INFO: Setting the data phase to 33 for uplink 29
15:43:54:setup_element:INFO: Setting the data phase to 38 for uplink 30
15:43:54:setup_element:INFO: Setting the data phase to 37 for uplink 31
15:43:54:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 35
Window Length: 70
Eye Windows:
Uplink 16: ________________________________________________________________________XXXXXXXX
Uplink 17: ________________________________________________________________________XXXXXXXX
Uplink 18: _______________________________________________________________________XXXXXXXX_
Uplink 19: _______________________________________________________________________XXXXXXXX_
Uplink 20: _______________________________________________________________________XXXXXXXX_
Uplink 21: _______________________________________________________________________XXXXXXXX_
Uplink 22: _______________________________________________________________________XXXXXXXX_
Uplink 23: _______________________________________________________________________XXXXXXXX_
Uplink 24: _______________________________________________________________________XXXXXXX__
Uplink 25: _______________________________________________________________________XXXXXXX__
Uplink 26: _______________________________________________________________________XXXXXXXXX
Uplink 27: _______________________________________________________________________XXXXXXXXX
Uplink 28: ________________________________________________________________________________
Uplink 29: ________________________________________________________________________________
Uplink 30: X_________________________________________________________________________XXXXXX
Uplink 31: X_________________________________________________________________________XXXXXX
Data phase characteristics:
Uplink 16:
Optimal Phase: 19
Window Length: 35
Eye Window: XX___________________________________XXX
Uplink 17:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
Uplink 18:
Optimal Phase: 17
Window Length: 33
Eye Window: X_________________________________XXXXX_
Uplink 19:
Optimal Phase: 13
Window Length: 36
Eye Window: ________________________________XXXX____
Uplink 20:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXXX
Uplink 21:
Optimal Phase: 16
Window Length: 35
Eye Window: __________________________________XXXXX_
Uplink 22:
Optimal Phase: 17
Window Length: 33
Eye Window: X_________________________________XXXXX_
Uplink 23:
Optimal Phase: 14
Window Length: 36
Eye Window: _________________________________XXXX___
Uplink 24:
Optimal Phase: 26
Window Length: 35
Eye Window: ____XXXXX_______________________________
Uplink 25:
Optimal Phase: 30
Window Length: 35
Eye Window: ________XXXXX___________________________
Uplink 26:
Optimal Phase: 28
Window Length: 35
Eye Window: ______XXXXX_____________________________
Uplink 27:
Optimal Phase: 31
Window Length: 33
Eye Window: ________XXXXXXX_________________________
Uplink 28:
Optimal Phase: 32
Window Length: 35
Eye Window: __________XXXXX_________________________
Uplink 29:
Optimal Phase: 33
Window Length: 35
Eye Window: ___________XXXXX________________________
Uplink 30:
Optimal Phase: 38
Window Length: 34
Eye Window: ________________XXXXXX__________________
Uplink 31:
Optimal Phase: 37
Window Length: 33
Eye Window: ______________XXXXXXX___________________
]
15:43:54:setup_element:INFO: Beginning SMX ASICs map scan
15:43:54:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:43:54:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
15:43:54:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
15:43:54:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
15:43:54:uplink:INFO: Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
15:43:54:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 23
15:43:54:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 22
15:43:54:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 30
15:43:54:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 31
15:43:54:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 21
15:43:54:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 20
15:43:54:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28
15:43:54:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 29
15:43:55:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 19
15:43:55:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 18
15:43:55:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26
15:43:55:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 27
15:43:55:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 17
15:43:55:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 16
15:43:55:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 24
15:43:55:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 25
15:43:56:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 23), (1, 22)
ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
ASIC address 0x2: (ASIC uplink, uplink): (0, 21), (1, 20)
ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
ASIC address 0x4: (ASIC uplink, uplink): (0, 19), (1, 18)
ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
ASIC address 0x6: (ASIC uplink, uplink): (0, 17), (1, 16)
ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
Clock Phase Characteristic:
Optimal Phase: 35
Window Length: 70
Eye Windows:
Uplink 16: ________________________________________________________________________XXXXXXXX
Uplink 17: ________________________________________________________________________XXXXXXXX
Uplink 18: _______________________________________________________________________XXXXXXXX_
Uplink 19: _______________________________________________________________________XXXXXXXX_
Uplink 20: _______________________________________________________________________XXXXXXXX_
Uplink 21: _______________________________________________________________________XXXXXXXX_
Uplink 22: _______________________________________________________________________XXXXXXXX_
Uplink 23: _______________________________________________________________________XXXXXXXX_
Uplink 24: _______________________________________________________________________XXXXXXX__
Uplink 25: _______________________________________________________________________XXXXXXX__
Uplink 26: _______________________________________________________________________XXXXXXXXX
Uplink 27: _______________________________________________________________________XXXXXXXXX
Uplink 28: ________________________________________________________________________________
Uplink 29: ________________________________________________________________________________
Uplink 30: X_________________________________________________________________________XXXXXX
Uplink 31: X_________________________________________________________________________XXXXXX
Data phase characteristics:
Uplink 16:
Optimal Phase: 19
Window Length: 35
Eye Window: XX___________________________________XXX
Uplink 17:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
Uplink 18:
Optimal Phase: 17
Window Length: 33
Eye Window: X_________________________________XXXXX_
Uplink 19:
Optimal Phase: 13
Window Length: 36
Eye Window: ________________________________XXXX____
Uplink 20:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXXX
Uplink 21:
Optimal Phase: 16
Window Length: 35
Eye Window: __________________________________XXXXX_
Uplink 22:
Optimal Phase: 17
Window Length: 33
Eye Window: X_________________________________XXXXX_
Uplink 23:
Optimal Phase: 14
Window Length: 36
Eye Window: _________________________________XXXX___
Uplink 24:
Optimal Phase: 26
Window Length: 35
Eye Window: ____XXXXX_______________________________
Uplink 25:
Optimal Phase: 30
Window Length: 35
Eye Window: ________XXXXX___________________________
Uplink 26:
Optimal Phase: 28
Window Length: 35
Eye Window: ______XXXXX_____________________________
Uplink 27:
Optimal Phase: 31
Window Length: 33
Eye Window: ________XXXXXXX_________________________
Uplink 28:
Optimal Phase: 32
Window Length: 35
Eye Window: __________XXXXX_________________________
Uplink 29:
Optimal Phase: 33
Window Length: 35
Eye Window: ___________XXXXX________________________
Uplink 30:
Optimal Phase: 38
Window Length: 34
Eye Window: ________________XXXXXX__________________
Uplink 31:
Optimal Phase: 37
Window Length: 33
Eye Window: ______________XXXXXXX___________________
15:43:57:setup_element:INFO: Performing Elink synchronization
15:43:57:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:43:57:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
15:43:57:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
15:43:57:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
15:43:57:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2
15:43:57:uplink:INFO: Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
15:43:57:ST3_emu:INFO: Number of chips: 8
15:43:57:ST3_emu:INFO: Chip address: 0x0
15:43:57:ST3_emu:INFO: Chip address: 0x1
15:43:57:ST3_emu:INFO: Chip address: 0x2
15:43:57:ST3_emu:INFO: Chip address: 0x3
15:43:57:ST3_emu:INFO: Chip address: 0x4
15:43:57:ST3_emu:INFO: Chip address: 0x5
15:43:57:ST3_emu:INFO: Chip address: 0x6
15:43:57:ST3_emu:INFO: Chip address: 0x7
15:43:58:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:43:58:febtest:INFO: 0-0 | XA-000-08-002-001-006-147-14 | 31.4 | 1230.3
15:43:58:febtest:INFO: 0-1 | XA-000-08-002-001-006-143-09 | 63.2 | 1100.2
15:43:58:febtest:INFO: 0-2 | XA-000-08-002-001-006-140-09 | 40.9 | 1195.1
15:43:59:febtest:INFO: 0-3 | XA-000-08-002-001-006-153-14 | 44.1 | 1189.2
15:43:59:febtest:INFO: 0-4 | XA-000-08-002-001-006-169-07 | 34.6 | 1212.7
15:43:59:febtest:INFO: 0-5 | XA-000-08-002-001-006-163-07 | 53.6 | 1153.7
15:43:59:febtest:INFO: 0-6 | XA-000-08-002-001-006-177-00 | 44.1 | 1177.4
15:44:00:febtest:INFO: 0-7 | XA-000-08-002-001-006-173-07 | 28.2 | 1247.9
15:44:00:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:44:03:ST3_smx:INFO: chip: 0-0 37.726682 C 1183.292940 mV
15:44:03:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:44:03:ST3_smx:INFO: Electrons
15:44:03:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:44:06:ST3_smx:INFO: ----> Checking Analog response
15:44:06:ST3_smx:INFO: ----> Checking broken channels
15:44:06:ST3_smx:INFO: Total # broken ch: 0
15:44:06:ST3_smx:INFO: List FAST: []
15:44:06:ST3_smx:INFO: List SLOW: []
15:44:06:ST3_smx:INFO: Holes
15:44:06:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:44:08:ST3_smx:INFO: ----> Checking Analog response
15:44:08:ST3_smx:INFO: ----> Checking broken channels
15:44:08:ST3_smx:INFO: Total # broken ch: 0
15:44:08:ST3_smx:INFO: List FAST: []
15:44:08:ST3_smx:INFO: List SLOW: []
15:44:08:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:44:09:febtest:INFO: 0-0 | XA-000-08-002-001-006-147-14 | 40.9 | 1183.3
15:44:09:febtest:INFO: 0-1 | XA-000-08-002-001-006-143-09 | 66.4 | 1106.2
15:44:09:febtest:INFO: 0-2 | XA-000-08-002-001-006-140-09 | 40.9 | 1189.2
15:44:09:febtest:INFO: 0-3 | XA-000-08-002-001-006-153-14 | 44.1 | 1189.2
15:44:10:febtest:INFO: 0-4 | XA-000-08-002-001-006-169-07 | 37.7 | 1212.7
15:44:10:febtest:INFO: 0-5 | XA-000-08-002-001-006-163-07 | 56.8 | 1153.7
15:44:10:febtest:INFO: 0-6 | XA-000-08-002-001-006-177-00 | 47.3 | 1177.4
15:44:10:febtest:INFO: 0-7 | XA-000-08-002-001-006-173-07 | 31.4 | 1247.9
15:44:11:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:44:14:ST3_smx:INFO: chip: 0-1 59.984250 C 1118.096875 mV
15:44:14:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:44:14:ST3_smx:INFO: Electrons
15:44:14:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:44:17:ST3_smx:INFO: ----> Checking Analog response
15:44:17:ST3_smx:INFO: ----> Checking broken channels
15:44:17:ST3_smx:INFO: Total # broken ch: 0
15:44:17:ST3_smx:INFO: List FAST: []
15:44:17:ST3_smx:INFO: List SLOW: []
15:44:17:ST3_smx:INFO: Holes
15:44:17:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:44:19:ST3_smx:INFO: ----> Checking Analog response
15:44:19:ST3_smx:INFO: ----> Checking broken channels
15:44:19:ST3_smx:INFO: Total # broken ch: 0
15:44:19:ST3_smx:INFO: List FAST: []
15:44:19:ST3_smx:INFO: List SLOW: []
15:44:19:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:44:20:febtest:INFO: 0-0 | XA-000-08-002-001-006-147-14 | 44.1 | 1183.3
15:44:20:febtest:INFO: 0-1 | XA-000-08-002-001-006-143-09 | 63.2 | 1112.1
15:44:20:febtest:INFO: 0-2 | XA-000-08-002-001-006-140-09 | 44.1 | 1195.1
15:44:20:febtest:INFO: 0-3 | XA-000-08-002-001-006-153-14 | 50.4 | 1183.3
15:44:21:febtest:INFO: 0-4 | XA-000-08-002-001-006-169-07 | 40.9 | 1206.9
15:44:21:febtest:INFO: 0-5 | XA-000-08-002-001-006-163-07 | 60.0 | 1147.8
15:44:21:febtest:INFO: 0-6 | XA-000-08-002-001-006-177-00 | 50.4 | 1177.4
15:44:21:febtest:INFO: 0-7 | XA-000-08-002-001-006-173-07 | 34.6 | 1247.9
15:44:22:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:44:26:ST3_smx:INFO: chip: 0-2 47.250730 C 1177.390875 mV
15:44:26:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:44:26:ST3_smx:INFO: Electrons
15:44:26:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:44:28:ST3_smx:INFO: ----> Checking Analog response
15:44:28:ST3_smx:INFO: ----> Checking broken channels
15:44:28:ST3_smx:INFO: Total # broken ch: 0
15:44:28:ST3_smx:INFO: List FAST: []
15:44:28:ST3_smx:INFO: List SLOW: []
15:44:28:ST3_smx:INFO: Holes
15:44:28:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:44:31:ST3_smx:INFO: ----> Checking Analog response
15:44:31:ST3_smx:INFO: ----> Checking broken channels
15:44:31:ST3_smx:INFO: Total # broken ch: 0
15:44:31:ST3_smx:INFO: List FAST: []
15:44:31:ST3_smx:INFO: List SLOW: []
15:44:31:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:44:31:febtest:INFO: 0-0 | XA-000-08-002-001-006-147-14 | 47.3 | 1177.4
15:44:31:febtest:INFO: 0-1 | XA-000-08-002-001-006-143-09 | 66.4 | 1112.1
15:44:32:febtest:INFO: 0-2 | XA-000-08-002-001-006-140-09 | 50.4 | 1171.5
15:44:32:febtest:INFO: 0-3 | XA-000-08-002-001-006-153-14 | 53.6 | 1183.3
15:44:32:febtest:INFO: 0-4 | XA-000-08-002-001-006-169-07 | 44.1 | 1206.9
15:44:32:febtest:INFO: 0-5 | XA-000-08-002-001-006-163-07 | 63.2 | 1147.8
15:44:32:febtest:INFO: 0-6 | XA-000-08-002-001-006-177-00 | 53.6 | 1177.4
15:44:33:febtest:INFO: 0-7 | XA-000-08-002-001-006-173-07 | 37.7 | 1253.7
15:44:33:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:44:37:ST3_smx:INFO: chip: 0-3 50.430383 C 1177.390875 mV
15:44:37:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:44:37:ST3_smx:INFO: Electrons
15:44:37:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:44:39:ST3_smx:INFO: ----> Checking Analog response
15:44:39:ST3_smx:INFO: ----> Checking broken channels
15:44:40:ST3_smx:INFO: Total # broken ch: 0
15:44:40:ST3_smx:INFO: List FAST: []
15:44:40:ST3_smx:INFO: List SLOW: []
15:44:40:ST3_smx:INFO: Holes
15:44:40:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:44:42:ST3_smx:INFO: ----> Checking Analog response
15:44:42:ST3_smx:INFO: ----> Checking broken channels
15:44:42:ST3_smx:INFO: Total # broken ch: 0
15:44:42:ST3_smx:INFO: List FAST: []
15:44:42:ST3_smx:INFO: List SLOW: []
15:44:42:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:44:42:febtest:INFO: 0-0 | XA-000-08-002-001-006-147-14 | 50.4 | 1177.4
15:44:42:febtest:INFO: 0-1 | XA-000-08-002-001-006-143-09 | 69.6 | 1112.1
15:44:43:febtest:INFO: 0-2 | XA-000-08-002-001-006-140-09 | 53.6 | 1171.5
15:44:43:febtest:INFO: 0-3 | XA-000-08-002-001-006-153-14 | 53.6 | 1177.4
15:44:43:febtest:INFO: 0-4 | XA-000-08-002-001-006-169-07 | 47.3 | 1206.9
15:44:43:febtest:INFO: 0-5 | XA-000-08-002-001-006-163-07 | 66.4 | 1147.8
15:44:44:febtest:INFO: 0-6 | XA-000-08-002-001-006-177-00 | 56.8 | 1171.5
15:44:44:febtest:INFO: 0-7 | XA-000-08-002-001-006-173-07 | 37.7 | 1253.7
15:44:44:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:44:48:ST3_smx:INFO: chip: 0-4 47.250730 C 1195.082160 mV
15:44:48:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:44:48:ST3_smx:INFO: Electrons
15:44:48:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:44:50:ST3_smx:INFO: ----> Checking Analog response
15:44:50:ST3_smx:INFO: ----> Checking broken channels
15:44:50:ST3_smx:INFO: Total # broken ch: 0
15:44:50:ST3_smx:INFO: List FAST: []
15:44:50:ST3_smx:INFO: List SLOW: []
15:44:50:ST3_smx:INFO: Holes
15:44:50:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:44:52:ST3_smx:INFO: ----> Checking Analog response
15:44:52:ST3_smx:INFO: ----> Checking broken channels
15:44:52:ST3_smx:INFO: Total # broken ch: 0
15:44:52:ST3_smx:INFO: List FAST: []
15:44:52:ST3_smx:INFO: List SLOW: []
15:44:52:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:44:52:febtest:INFO: 0-0 | XA-000-08-002-001-006-147-14 | 53.6 | 1177.4
15:44:53:febtest:INFO: 0-1 | XA-000-08-002-001-006-143-09 | 72.8 | 1112.1
15:44:53:febtest:INFO: 0-2 | XA-000-08-002-001-006-140-09 | 56.8 | 1165.6
15:44:53:febtest:INFO: 0-3 | XA-000-08-002-001-006-153-14 | 56.8 | 1171.5
15:44:53:febtest:INFO: 0-4 | XA-000-08-002-001-006-169-07 | 50.4 | 1195.1
15:44:53:febtest:INFO: 0-5 | XA-000-08-002-001-006-163-07 | 69.6 | 1141.9
15:44:54:febtest:INFO: 0-6 | XA-000-08-002-001-006-177-00 | 60.0 | 1171.5
15:44:54:febtest:INFO: 0-7 | XA-000-08-002-001-006-173-07 | 40.9 | 1259.6
15:44:54:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:44:58:ST3_smx:INFO: chip: 0-5 66.365920 C 1147.806000 mV
15:44:58:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:44:58:ST3_smx:INFO: Electrons
15:44:58:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:45:00:ST3_smx:INFO: ----> Checking Analog response
15:45:00:ST3_smx:INFO: ----> Checking broken channels
15:45:00:ST3_smx:INFO: Total # broken ch: 0
15:45:00:ST3_smx:INFO: List FAST: []
15:45:00:ST3_smx:INFO: List SLOW: []
15:45:00:ST3_smx:INFO: Holes
15:45:00:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:45:02:ST3_smx:INFO: ----> Checking Analog response
15:45:02:ST3_smx:INFO: ----> Checking broken channels
15:45:02:ST3_smx:INFO: Total # broken ch: 0
15:45:02:ST3_smx:INFO: List FAST: []
15:45:02:ST3_smx:INFO: List SLOW: []
15:45:02:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:45:02:febtest:INFO: 0-0 | XA-000-08-002-001-006-147-14 | 56.8 | 1177.4
15:45:02:febtest:INFO: 0-1 | XA-000-08-002-001-006-143-09 | 76.0 | 1106.2
15:45:03:febtest:INFO: 0-2 | XA-000-08-002-001-006-140-09 | 60.0 | 1165.6
15:45:03:febtest:INFO: 0-3 | XA-000-08-002-001-006-153-14 | 60.0 | 1171.5
15:45:03:febtest:INFO: 0-4 | XA-000-08-002-001-006-169-07 | 53.6 | 1189.2
15:45:03:febtest:INFO: 0-5 | XA-000-08-002-001-006-163-07 | 69.6 | 1141.9
15:45:04:febtest:INFO: 0-6 | XA-000-08-002-001-006-177-00 | 63.2 | 1171.5
15:45:04:febtest:INFO: 0-7 | XA-000-08-002-001-006-173-07 | 44.1 | 1259.6
15:45:04:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:45:08:ST3_smx:INFO: chip: 0-6 59.984250 C 1165.571835 mV
15:45:08:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:45:08:ST3_smx:INFO: Electrons
15:45:08:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:45:10:ST3_smx:INFO: ----> Checking Analog response
15:45:10:ST3_smx:INFO: ----> Checking broken channels
15:45:10:ST3_smx:INFO: Total # broken ch: 0
15:45:10:ST3_smx:INFO: List FAST: []
15:45:10:ST3_smx:INFO: List SLOW: []
15:45:10:ST3_smx:INFO: Holes
15:45:10:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:45:12:ST3_smx:INFO: ----> Checking Analog response
15:45:12:ST3_smx:INFO: ----> Checking broken channels
15:45:12:ST3_smx:INFO: Total # broken ch: 0
15:45:12:ST3_smx:INFO: List FAST: []
15:45:12:ST3_smx:INFO: List SLOW: []
15:45:12:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:45:12:febtest:INFO: 0-0 | XA-000-08-002-001-006-147-14 | 60.0 | 1171.5
15:45:13:febtest:INFO: 0-1 | XA-000-08-002-001-006-143-09 | 76.0 | 1106.2
15:45:13:febtest:INFO: 0-2 | XA-000-08-002-001-006-140-09 | 63.2 | 1165.6
15:45:13:febtest:INFO: 0-3 | XA-000-08-002-001-006-153-14 | 63.2 | 1171.5
15:45:13:febtest:INFO: 0-4 | XA-000-08-002-001-006-169-07 | 56.8 | 1189.2
15:45:13:febtest:INFO: 0-5 | XA-000-08-002-001-006-163-07 | 72.8 | 1141.9
15:45:14:febtest:INFO: 0-6 | XA-000-08-002-001-006-177-00 | 63.2 | 1165.6
15:45:14:febtest:INFO: 0-7 | XA-000-08-002-001-006-173-07 | 47.3 | 1265.4
15:45:14:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:45:18:ST3_smx:INFO: chip: 0-7 59.984250 C 1200.969315 mV
15:45:18:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:45:18:ST3_smx:INFO: Electrons
15:45:18:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:45:20:ST3_smx:INFO: ----> Checking Analog response
15:45:20:ST3_smx:INFO: ----> Checking broken channels
15:45:20:ST3_smx:INFO: Total # broken ch: 0
15:45:20:ST3_smx:INFO: List FAST: []
15:45:20:ST3_smx:INFO: List SLOW: []
15:45:20:ST3_smx:INFO: Holes
15:45:20:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:45:22:ST3_smx:INFO: ----> Checking Analog response
15:45:22:ST3_smx:INFO: ----> Checking broken channels
15:45:22:ST3_smx:INFO: Total # broken ch: 0
15:45:22:ST3_smx:INFO: List FAST: []
15:45:22:ST3_smx:INFO: List SLOW: []
15:45:22:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:45:22:febtest:INFO: 0-0 | XA-000-08-002-001-006-147-14 | 60.0 | 1171.5
15:45:23:febtest:INFO: 0-1 | XA-000-08-002-001-006-143-09 | 79.2 | 1106.2
15:45:23:febtest:INFO: 0-2 | XA-000-08-002-001-006-140-09 | 63.2 | 1165.6
15:45:23:febtest:INFO: 0-3 | XA-000-08-002-001-006-153-14 | 66.4 | 1165.6
15:45:23:febtest:INFO: 0-4 | XA-000-08-002-001-006-169-07 | 60.0 | 1189.2
15:45:23:febtest:INFO: 0-5 | XA-000-08-002-001-006-163-07 | 72.8 | 1141.9
15:45:24:febtest:INFO: 0-6 | XA-000-08-002-001-006-177-00 | 66.4 | 1165.6
15:45:24:febtest:INFO: 0-7 | XA-000-08-002-001-006-173-07 | 63.2 | 1206.9
############################################################
# S U M M A R Y #
############################################################
{'TEST_NAME': 'FEB-ASIC', 'TEST_DATE': '2023_10_09-15_43_45', 'OPERATOR': 'Alois Alzheimer', 'PROJECT': 'Production', 'SITE': 'GSI', 'SETUP': 'GSI_TEST_SETUP_1', 'ASIC_ID': 'XA-000-08-002-001-006-173-07', 'FUSED_ID': 6359364699117611735, 'HW_ADDR': 7, 'VERS_NO': '2.2', 'CABLE_SET_ID': '', 'IC_TEMP': '0', 'VDDM': '0', 'AUX': '0', 'CSABIAS': '0', 'VDDM_INT': '0', 'ADC_Chi2': 0.0, 'ADC_NDF': 0, 'ADC_P0': 0.0, 'ADC_P1': 0.006824, 'ADC_P2': -2.485e-06, 'ADC_P0err': 0.001, 'ADC_P1err': 0.001, 'ADC_P2err': 1e-05, 'ADC_VREF_P': 58, 'ADC_VREF_N': 30, 'ADC_VREF_T': 128, 'ADC_VREF_TR': 122, 'THR2_GLB': 30, 'LOOP__PLS': 100, 'CALIB_PLS': 250, 'SnsLoop': 5, 'IFED': 31, 'CSA_BIAS': 15, 'CSA_Chi2': 0.0, 'CSA_NDF': 0, 'CSA_P0': 0.0, 'CSA_P1': 0.0, 'CSA_P2': 0.0, 'CSA_P0err': 0.0, 'CSA_P1err': 0.0, 'CSA_P2err': 0.0, 'CONF_FAIL_REG': 0, 'N_BROKEN_DISC': 0, 'N_BROKEN_FAST': '[]', 'N_BROKEN_SLOW': '[]', 'P_BROKEN_DISC': 0, 'P_BROKEN_FAST': '[]', 'P_BROKEN_SLOW': '[]', 'ASIC_QA_category': '', 'N_BROKEN_CABLE': 0, 'LIST_OF_BROKEN_CABLES': 0, 'VI_bInit': ['2.448', '1.5170', '1.846', '2.5580', '7.001', '1.5440', '7.001', '1.5440'], 'VI_aInit': ['0', '0', '0', '0', '0', '0'], 'VI_atEnd': ['0', '0', '0', '0', '0', '0'], 'AMP_CAL': 200, 'PlsLoop': 3, 'N_ANA_PRESENT': 'Analog response OK', 'N_DISC_FAIL_CH': 0, 'N_ANA_FAIL_CH': '0', 'P_ANA_PRESENT': 'Analog response OK', 'P_DISC_FAIL_CH': 0, 'P_ANA_FAIL_CH': '0'}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
15:45:28:ST3_Shared:INFO: Listo of operators:Irakli K.;
15:45:30:ST3_Shared:INFO: /home/cbm/public_html/Production_LogDir//FEB/FEB_2013/B//TestDate_2023_10_09-15_43_45/