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FEB_2013 09.10.23 15:46:05
Info
15:45:54:ST3_hmp4040:INFO: HAMEG,HMP2030,017836163,HW50010002/SW2.30
15:45:55:febtest:INFO: FEB8.2 selected
15:45:55:smx_tester:INFO: Setting Elink clock mode to 160 MHz
15:45:55:febtest:INFO: FEB8.2 selected
15:45:55:smx_tester:INFO: Setting Elink clock mode to 160 MHz
15:45:57:ST3_Shared:INFO: Listo of operators:Irakli K.;
15:46:05:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
15:46:05:ST3_Shared:INFO: --------------------------FEB-ASIC--------------------------
15:46:05:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
15:46:06:febtest:INFO: Tsting FEB with SN 2013
15:46:07:smx_tester:INFO: Scanning setup
15:46:07:elinks:INFO: Disabling clock on downlink 0
15:46:07:elinks:INFO: Disabling clock on downlink 1
15:46:07:elinks:INFO: Disabling clock on downlink 2
15:46:07:elinks:INFO: Disabling clock on downlink 3
15:46:07:elinks:INFO: Disabling clock on downlink 4
15:46:07:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:46:07:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
15:46:07:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:46:07:elinks:INFO: Disabling clock on downlink 0
15:46:07:elinks:INFO: Disabling clock on downlink 1
15:46:07:elinks:INFO: Disabling clock on downlink 2
15:46:07:elinks:INFO: Disabling clock on downlink 3
15:46:07:elinks:INFO: Disabling clock on downlink 4
15:46:07:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:46:07:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
15:46:07:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:46:07:elinks:INFO: Disabling clock on downlink 0
15:46:07:elinks:INFO: Disabling clock on downlink 1
15:46:07:elinks:INFO: Disabling clock on downlink 2
15:46:07:elinks:INFO: Disabling clock on downlink 3
15:46:07:elinks:INFO: Disabling clock on downlink 4
15:46:07:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:46:07:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:46:07:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 16
15:46:07:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 17
15:46:07:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 18
15:46:07:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 19
15:46:07:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 20
15:46:07:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 21
15:46:07:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 22
15:46:07:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 23
15:46:07:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24
15:46:07:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25
15:46:07:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26
15:46:07:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27
15:46:07:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28
15:46:07:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29
15:46:07:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30
15:46:07:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31
15:46:07:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:46:07:elinks:INFO: Disabling clock on downlink 0
15:46:07:elinks:INFO: Disabling clock on downlink 1
15:46:07:elinks:INFO: Disabling clock on downlink 2
15:46:07:elinks:INFO: Disabling clock on downlink 3
15:46:07:elinks:INFO: Disabling clock on downlink 4
15:46:07:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:46:07:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
15:46:08:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:46:08:elinks:INFO: Disabling clock on downlink 0
15:46:08:elinks:INFO: Disabling clock on downlink 1
15:46:08:elinks:INFO: Disabling clock on downlink 2
15:46:08:elinks:INFO: Disabling clock on downlink 3
15:46:08:elinks:INFO: Disabling clock on downlink 4
15:46:08:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:46:08:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
15:46:08:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:46:08:setup_element:INFO: Scanning clock phase
15:46:08:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:46:08:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
15:46:08:setup_element:INFO: Clock phase scan results for group 0, downlink 2
15:46:08:setup_element:INFO: Eye window for uplink 16: _______________________________________________________________________XXXXXXXXX
Clock Delay: 35
15:46:08:setup_element:INFO: Eye window for uplink 17: _______________________________________________________________________XXXXXXXXX
Clock Delay: 35
15:46:08:setup_element:INFO: Eye window for uplink 18: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
15:46:08:setup_element:INFO: Eye window for uplink 19: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
15:46:08:setup_element:INFO: Eye window for uplink 20: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
15:46:08:setup_element:INFO: Eye window for uplink 21: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
15:46:08:setup_element:INFO: Eye window for uplink 22: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
15:46:08:setup_element:INFO: Eye window for uplink 23: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
15:46:08:setup_element:INFO: Eye window for uplink 24: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
15:46:08:setup_element:INFO: Eye window for uplink 25: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
15:46:08:setup_element:INFO: Eye window for uplink 26: ________________________________________________________________________________
Clock Delay: 40
15:46:08:setup_element:INFO: Eye window for uplink 27: ________________________________________________________________________________
Clock Delay: 40
15:46:08:setup_element:INFO: Eye window for uplink 28: ________________________________________________________________________________
Clock Delay: 40
15:46:08:setup_element:INFO: Eye window for uplink 29: ________________________________________________________________________________
Clock Delay: 40
15:46:08:setup_element:INFO: Eye window for uplink 30: _________________________________________________________________________XXXXXXX
Clock Delay: 36
15:46:08:setup_element:INFO: Eye window for uplink 31: _________________________________________________________________________XXXXXXX
Clock Delay: 36
15:46:08:setup_element:INFO: Setting the clock phase to 34 for group 0, downlink 2
15:46:08:setup_element:INFO: Scanning data phases
15:46:08:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:46:08:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
15:46:14:setup_element:INFO: Data phase scan results for group 0, downlink 2
15:46:14:setup_element:INFO: Eye window for uplink 16: XX___________________________________XXX
Data delay found: 19
15:46:14:setup_element:INFO: Eye window for uplink 17: _________________________________XXXX___
Data delay found: 14
15:46:14:setup_element:INFO: Eye window for uplink 18: __________________________________XXXXX_
Data delay found: 16
15:46:14:setup_element:INFO: Eye window for uplink 19: _______________________________XXXXX____
Data delay found: 13
15:46:14:setup_element:INFO: Eye window for uplink 20: __________________________________XXXXX_
Data delay found: 16
15:46:14:setup_element:INFO: Eye window for uplink 21: _________________________________XXXXX__
Data delay found: 15
15:46:14:setup_element:INFO: Eye window for uplink 22: __________________________________XXXX__
Data delay found: 15
15:46:14:setup_element:INFO: Eye window for uplink 23: ________________________________XXXXX___
Data delay found: 14
15:46:14:setup_element:INFO: Eye window for uplink 24: ___XXXXX________________________________
Data delay found: 25
15:46:14:setup_element:INFO: Eye window for uplink 25: ______XXXXX_____________________________
Data delay found: 28
15:46:14:setup_element:INFO: Eye window for uplink 26: ____XXXXXX______________________________
Data delay found: 26
15:46:14:setup_element:INFO: Eye window for uplink 27: _______XXXXXX___________________________
Data delay found: 29
15:46:14:setup_element:INFO: Eye window for uplink 28: _________XXXXX__________________________
Data delay found: 31
15:46:14:setup_element:INFO: Eye window for uplink 29: __________XXXXXX________________________
Data delay found: 32
15:46:14:setup_element:INFO: Eye window for uplink 30: _______________XXXXXXX__________________
Data delay found: 38
15:46:14:setup_element:INFO: Eye window for uplink 31: ______________XXXXX_X___________________
Data delay found: 37
15:46:14:setup_element:INFO: Setting the data phase to 19 for uplink 16
15:46:14:setup_element:INFO: Setting the data phase to 14 for uplink 17
15:46:14:setup_element:INFO: Setting the data phase to 16 for uplink 18
15:46:14:setup_element:INFO: Setting the data phase to 13 for uplink 19
15:46:14:setup_element:INFO: Setting the data phase to 16 for uplink 20
15:46:14:setup_element:INFO: Setting the data phase to 15 for uplink 21
15:46:14:setup_element:INFO: Setting the data phase to 15 for uplink 22
15:46:14:setup_element:INFO: Setting the data phase to 14 for uplink 23
15:46:14:setup_element:INFO: Setting the data phase to 25 for uplink 24
15:46:14:setup_element:INFO: Setting the data phase to 28 for uplink 25
15:46:14:setup_element:INFO: Setting the data phase to 26 for uplink 26
15:46:14:setup_element:INFO: Setting the data phase to 29 for uplink 27
15:46:14:setup_element:INFO: Setting the data phase to 31 for uplink 28
15:46:14:setup_element:INFO: Setting the data phase to 32 for uplink 29
15:46:14:setup_element:INFO: Setting the data phase to 38 for uplink 30
15:46:14:setup_element:INFO: Setting the data phase to 37 for uplink 31
15:46:14:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 34
Window Length: 70
Eye Windows:
Uplink 16: _______________________________________________________________________XXXXXXXXX
Uplink 17: _______________________________________________________________________XXXXXXXXX
Uplink 18: _______________________________________________________________________XXXXXXX__
Uplink 19: _______________________________________________________________________XXXXXXX__
Uplink 20: _______________________________________________________________________XXXXXXXX_
Uplink 21: _______________________________________________________________________XXXXXXXX_
Uplink 22: ______________________________________________________________________XXXXXXXX__
Uplink 23: ______________________________________________________________________XXXXXXXX__
Uplink 24: _______________________________________________________________________XXXXXXX__
Uplink 25: _______________________________________________________________________XXXXXXX__
Uplink 26: ________________________________________________________________________________
Uplink 27: ________________________________________________________________________________
Uplink 28: ________________________________________________________________________________
Uplink 29: ________________________________________________________________________________
Uplink 30: _________________________________________________________________________XXXXXXX
Uplink 31: _________________________________________________________________________XXXXXXX
Data phase characteristics:
Uplink 16:
Optimal Phase: 19
Window Length: 35
Eye Window: XX___________________________________XXX
Uplink 17:
Optimal Phase: 14
Window Length: 36
Eye Window: _________________________________XXXX___
Uplink 18:
Optimal Phase: 16
Window Length: 35
Eye Window: __________________________________XXXXX_
Uplink 19:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 20:
Optimal Phase: 16
Window Length: 35
Eye Window: __________________________________XXXXX_
Uplink 21:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
Uplink 22:
Optimal Phase: 15
Window Length: 36
Eye Window: __________________________________XXXX__
Uplink 23:
Optimal Phase: 14
Window Length: 35
Eye Window: ________________________________XXXXX___
Uplink 24:
Optimal Phase: 25
Window Length: 35
Eye Window: ___XXXXX________________________________
Uplink 25:
Optimal Phase: 28
Window Length: 35
Eye Window: ______XXXXX_____________________________
Uplink 26:
Optimal Phase: 26
Window Length: 34
Eye Window: ____XXXXXX______________________________
Uplink 27:
Optimal Phase: 29
Window Length: 34
Eye Window: _______XXXXXX___________________________
Uplink 28:
Optimal Phase: 31
Window Length: 35
Eye Window: _________XXXXX__________________________
Uplink 29:
Optimal Phase: 32
Window Length: 34
Eye Window: __________XXXXXX________________________
Uplink 30:
Optimal Phase: 38
Window Length: 33
Eye Window: _______________XXXXXXX__________________
Uplink 31:
Optimal Phase: 37
Window Length: 33
Eye Window: ______________XXXXX_X___________________
]
15:46:14:setup_element:INFO: Beginning SMX ASICs map scan
15:46:14:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:46:14:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
15:46:14:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
15:46:14:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
15:46:14:uplink:INFO: Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
15:46:14:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 23
15:46:14:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 22
15:46:14:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 30
15:46:14:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 31
15:46:14:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 21
15:46:14:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 20
15:46:14:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28
15:46:14:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 29
15:46:15:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 19
15:46:15:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 18
15:46:15:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26
15:46:15:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 27
15:46:15:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 17
15:46:15:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 16
15:46:15:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 24
15:46:15:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 25
15:46:16:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 23), (1, 22)
ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
ASIC address 0x2: (ASIC uplink, uplink): (0, 21), (1, 20)
ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
ASIC address 0x4: (ASIC uplink, uplink): (0, 19), (1, 18)
ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
ASIC address 0x6: (ASIC uplink, uplink): (0, 17), (1, 16)
ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
Clock Phase Characteristic:
Optimal Phase: 34
Window Length: 70
Eye Windows:
Uplink 16: _______________________________________________________________________XXXXXXXXX
Uplink 17: _______________________________________________________________________XXXXXXXXX
Uplink 18: _______________________________________________________________________XXXXXXX__
Uplink 19: _______________________________________________________________________XXXXXXX__
Uplink 20: _______________________________________________________________________XXXXXXXX_
Uplink 21: _______________________________________________________________________XXXXXXXX_
Uplink 22: ______________________________________________________________________XXXXXXXX__
Uplink 23: ______________________________________________________________________XXXXXXXX__
Uplink 24: _______________________________________________________________________XXXXXXX__
Uplink 25: _______________________________________________________________________XXXXXXX__
Uplink 26: ________________________________________________________________________________
Uplink 27: ________________________________________________________________________________
Uplink 28: ________________________________________________________________________________
Uplink 29: ________________________________________________________________________________
Uplink 30: _________________________________________________________________________XXXXXXX
Uplink 31: _________________________________________________________________________XXXXXXX
Data phase characteristics:
Uplink 16:
Optimal Phase: 19
Window Length: 35
Eye Window: XX___________________________________XXX
Uplink 17:
Optimal Phase: 14
Window Length: 36
Eye Window: _________________________________XXXX___
Uplink 18:
Optimal Phase: 16
Window Length: 35
Eye Window: __________________________________XXXXX_
Uplink 19:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 20:
Optimal Phase: 16
Window Length: 35
Eye Window: __________________________________XXXXX_
Uplink 21:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
Uplink 22:
Optimal Phase: 15
Window Length: 36
Eye Window: __________________________________XXXX__
Uplink 23:
Optimal Phase: 14
Window Length: 35
Eye Window: ________________________________XXXXX___
Uplink 24:
Optimal Phase: 25
Window Length: 35
Eye Window: ___XXXXX________________________________
Uplink 25:
Optimal Phase: 28
Window Length: 35
Eye Window: ______XXXXX_____________________________
Uplink 26:
Optimal Phase: 26
Window Length: 34
Eye Window: ____XXXXXX______________________________
Uplink 27:
Optimal Phase: 29
Window Length: 34
Eye Window: _______XXXXXX___________________________
Uplink 28:
Optimal Phase: 31
Window Length: 35
Eye Window: _________XXXXX__________________________
Uplink 29:
Optimal Phase: 32
Window Length: 34
Eye Window: __________XXXXXX________________________
Uplink 30:
Optimal Phase: 38
Window Length: 33
Eye Window: _______________XXXXXXX__________________
Uplink 31:
Optimal Phase: 37
Window Length: 33
Eye Window: ______________XXXXX_X___________________
15:46:16:setup_element:INFO: Performing Elink synchronization
15:46:16:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:46:16:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
15:46:16:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
15:46:17:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
15:46:17:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2
15:46:17:uplink:INFO: Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
15:46:17:ST3_emu:INFO: Number of chips: 8
15:46:17:ST3_emu:INFO: Chip address: 0x0
15:46:17:ST3_emu:INFO: Chip address: 0x1
15:46:17:ST3_emu:INFO: Chip address: 0x2
15:46:17:ST3_emu:INFO: Chip address: 0x3
15:46:17:ST3_emu:INFO: Chip address: 0x4
15:46:17:ST3_emu:INFO: Chip address: 0x5
15:46:17:ST3_emu:INFO: Chip address: 0x6
15:46:17:ST3_emu:INFO: Chip address: 0x7
15:46:18:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:46:18:febtest:INFO: 0-0 | XA-000-08-002-001-006-147-14 | 50.4 | 1230.3
15:46:18:febtest:INFO: 0-1 | XA-000-08-002-001-006-143-09 | 82.4 | 1112.1
15:46:18:febtest:INFO: 0-2 | XA-000-08-002-001-006-140-09 | 63.2 | 1177.4
15:46:19:febtest:INFO: 0-3 | XA-000-08-002-001-006-153-14 | 60.0 | 1195.1
15:46:19:febtest:INFO: 0-4 | XA-000-08-002-001-006-169-07 | 60.0 | 1201.0
15:46:19:febtest:INFO: 0-5 | XA-000-08-002-001-006-163-07 | 69.6 | 1171.5
15:46:19:febtest:INFO: 0-6 | XA-000-08-002-001-006-177-00 | 66.4 | 1177.4
15:46:19:febtest:INFO: 0-7 | XA-000-08-002-001-006-173-07 | 44.1 | 1306.1
15:46:19:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:46:24:ST3_smx:INFO: chip: 0-0 56.797143 C 1183.292940 mV
15:46:24:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:46:24:ST3_smx:INFO: Electrons
15:46:24:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:46:26:ST3_smx:INFO: ----> Checking Analog response
15:46:26:ST3_smx:INFO: ----> Checking broken channels
15:46:26:ST3_smx:INFO: Total # broken ch: 0
15:46:26:ST3_smx:INFO: List FAST: []
15:46:26:ST3_smx:INFO: List SLOW: []
15:46:26:ST3_smx:INFO: Holes
15:46:26:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:46:28:ST3_smx:INFO: ----> Checking Analog response
15:46:28:ST3_smx:INFO: ----> Checking broken channels
15:46:29:ST3_smx:INFO: Total # broken ch: 0
15:46:29:ST3_smx:INFO: List FAST: []
15:46:29:ST3_smx:INFO: List SLOW: []
15:46:29:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:46:29:febtest:INFO: 0-0 | XA-000-08-002-001-006-147-14 | 60.0 | 1183.3
15:46:29:febtest:INFO: 0-1 | XA-000-08-002-001-006-143-09 | 82.4 | 1112.1
15:46:29:febtest:INFO: 0-2 | XA-000-08-002-001-006-140-09 | 63.2 | 1177.4
15:46:30:febtest:INFO: 0-3 | XA-000-08-002-001-006-153-14 | 63.2 | 1195.1
15:46:30:febtest:INFO: 0-4 | XA-000-08-002-001-006-169-07 | 60.0 | 1201.0
15:46:30:febtest:INFO: 0-5 | XA-000-08-002-001-006-163-07 | 72.8 | 1165.6
15:46:30:febtest:INFO: 0-6 | XA-000-08-002-001-006-177-00 | 66.4 | 1177.4
15:46:30:febtest:INFO: 0-7 | XA-000-08-002-001-006-173-07 | 44.1 | 1317.7
15:46:31:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:46:35:ST3_smx:INFO: chip: 0-1 75.957063 C 1118.096875 mV
15:46:35:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:46:35:ST3_smx:INFO: Electrons
15:46:35:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:46:38:ST3_smx:INFO: ----> Checking Analog response
15:46:38:ST3_smx:INFO: ----> Checking broken channels
15:46:38:ST3_smx:INFO: Total # broken ch: 0
15:46:38:ST3_smx:INFO: List FAST: []
15:46:38:ST3_smx:INFO: List SLOW: []
15:46:38:ST3_smx:INFO: Holes
15:46:38:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:46:41:ST3_smx:INFO: ----> Checking Analog response
15:46:41:ST3_smx:INFO: ----> Checking broken channels
15:46:41:ST3_smx:INFO: Total # broken ch: 0
15:46:41:ST3_smx:INFO: List FAST: []
15:46:41:ST3_smx:INFO: List SLOW: []
15:46:41:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:46:41:febtest:INFO: 0-0 | XA-000-08-002-001-006-147-14 | 63.2 | 1177.4
15:46:41:febtest:INFO: 0-1 | XA-000-08-002-001-006-143-09 | 79.2 | 1112.1
15:46:42:febtest:INFO: 0-2 | XA-000-08-002-001-006-140-09 | 66.4 | 1177.4
15:46:42:febtest:INFO: 0-3 | XA-000-08-002-001-006-153-14 | 63.2 | 1195.1
15:46:42:febtest:INFO: 0-4 | XA-000-08-002-001-006-169-07 | 60.0 | 1201.0
15:46:42:febtest:INFO: 0-5 | XA-000-08-002-001-006-163-07 | 72.8 | 1165.6
15:46:42:febtest:INFO: 0-6 | XA-000-08-002-001-006-177-00 | 69.6 | 1171.5
15:46:43:febtest:INFO: 0-7 | XA-000-08-002-001-006-173-07 | 44.1 | 1329.2
15:46:43:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:46:47:ST3_smx:INFO: chip: 0-2 66.365920 C 1171.483840 mV
15:46:47:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:46:47:ST3_smx:INFO: Electrons
15:46:47:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:46:49:ST3_smx:INFO: ----> Checking Analog response
15:46:49:ST3_smx:INFO: ----> Checking broken channels
15:46:49:ST3_smx:INFO: Total # broken ch: 0
15:46:49:ST3_smx:INFO: List FAST: []
15:46:49:ST3_smx:INFO: List SLOW: []
15:46:49:ST3_smx:INFO: Holes
15:46:49:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:46:51:ST3_smx:INFO: ----> Checking Analog response
15:46:51:ST3_smx:INFO: ----> Checking broken channels
15:46:52:ST3_smx:INFO: Total # broken ch: 0
15:46:52:ST3_smx:INFO: List FAST: []
15:46:52:ST3_smx:INFO: List SLOW: []
15:46:52:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:46:52:febtest:INFO: 0-0 | XA-000-08-002-001-006-147-14 | 63.2 | 1177.4
15:46:52:febtest:INFO: 0-1 | XA-000-08-002-001-006-143-09 | 82.4 | 1112.1
15:46:52:febtest:INFO: 0-2 | XA-000-08-002-001-006-140-09 | 69.6 | 1165.6
15:46:53:febtest:INFO: 0-3 | XA-000-08-002-001-006-153-14 | 66.4 | 1189.2
15:46:53:febtest:INFO: 0-4 | XA-000-08-002-001-006-169-07 | 63.2 | 1195.1
15:46:53:febtest:INFO: 0-5 | XA-000-08-002-001-006-163-07 | 76.0 | 1165.6
15:46:53:febtest:INFO: 0-6 | XA-000-08-002-001-006-177-00 | 69.6 | 1177.4
15:46:54:febtest:INFO: 0-7 | XA-000-08-002-001-006-173-07 | 47.3 | 1346.5
15:46:54:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:46:58:ST3_smx:INFO: chip: 0-3 66.365920 C 1171.483840 mV
15:46:58:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:46:58:ST3_smx:INFO: Electrons
15:46:58:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:47:00:ST3_smx:INFO: ----> Checking Analog response
15:47:00:ST3_smx:INFO: ----> Checking broken channels
15:47:00:ST3_smx:INFO: Total # broken ch: 0
15:47:00:ST3_smx:INFO: List FAST: []
15:47:00:ST3_smx:INFO: List SLOW: []
15:47:00:ST3_smx:INFO: Holes
15:47:00:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:47:02:ST3_smx:INFO: ----> Checking Analog response
15:47:02:ST3_smx:INFO: ----> Checking broken channels
15:47:02:ST3_smx:INFO: Total # broken ch: 0
15:47:02:ST3_smx:INFO: List FAST: []
15:47:02:ST3_smx:INFO: List SLOW: []
15:47:02:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:47:03:febtest:INFO: 0-0 | XA-000-08-002-001-006-147-14 | 66.4 | 1177.4
15:47:03:febtest:INFO: 0-1 | XA-000-08-002-001-006-143-09 | 82.4 | 1112.1
15:47:03:febtest:INFO: 0-2 | XA-000-08-002-001-006-140-09 | 69.6 | 1165.6
15:47:03:febtest:INFO: 0-3 | XA-000-08-002-001-006-153-14 | 69.6 | 1171.5
15:47:04:febtest:INFO: 0-4 | XA-000-08-002-001-006-169-07 | 63.2 | 1201.0
15:47:04:febtest:INFO: 0-5 | XA-000-08-002-001-006-163-07 | 76.0 | 1165.6
15:47:04:febtest:INFO: 0-6 | XA-000-08-002-001-006-177-00 | 72.8 | 1177.4
15:47:04:febtest:INFO: 0-7 | XA-000-08-002-001-006-173-07 | 47.3 | 1358.0
15:47:05:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:47:08:ST3_smx:INFO: chip: 0-4 63.173842 C 1189.190035 mV
15:47:08:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:47:08:ST3_smx:INFO: Electrons
15:47:08:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:47:10:ST3_smx:INFO: ----> Checking Analog response
15:47:10:ST3_smx:INFO: ----> Checking broken channels
15:47:11:ST3_smx:INFO: Total # broken ch: 0
15:47:11:ST3_smx:INFO: List FAST: []
15:47:11:ST3_smx:INFO: List SLOW: []
15:47:11:ST3_smx:INFO: Holes
15:47:11:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:47:13:ST3_smx:INFO: ----> Checking Analog response
15:47:13:ST3_smx:INFO: ----> Checking broken channels
15:47:13:ST3_smx:INFO: Total # broken ch: 0
15:47:13:ST3_smx:INFO: List FAST: []
15:47:13:ST3_smx:INFO: List SLOW: []
15:47:13:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:47:13:febtest:INFO: 0-0 | XA-000-08-002-001-006-147-14 | 66.4 | 1171.5
15:47:14:febtest:INFO: 0-1 | XA-000-08-002-001-006-143-09 | 85.6 | 1112.1
15:47:14:febtest:INFO: 0-2 | XA-000-08-002-001-006-140-09 | 72.8 | 1165.6
15:47:14:febtest:INFO: 0-3 | XA-000-08-002-001-006-153-14 | 72.8 | 1171.5
15:47:14:febtest:INFO: 0-4 | XA-000-08-002-001-006-169-07 | 66.4 | 1183.3
15:47:15:febtest:INFO: 0-5 | XA-000-08-002-001-006-163-07 | 79.2 | 1159.7
15:47:15:febtest:INFO: 0-6 | XA-000-08-002-001-006-177-00 | 72.8 | 1171.5
15:47:15:febtest:INFO: 0-7 | XA-000-08-002-001-006-173-07 | 44.1 | 1392.5
15:47:15:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:47:19:ST3_smx:INFO: chip: 0-5 79.159080 C 1141.874115 mV
15:47:19:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:47:19:ST3_smx:INFO: Electrons
15:47:19:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:47:22:ST3_smx:INFO: ----> Checking Analog response
15:47:22:ST3_smx:INFO: ----> Checking broken channels
15:47:22:ST3_smx:INFO: Total # broken ch: 0
15:47:22:ST3_smx:INFO: List FAST: []
15:47:22:ST3_smx:INFO: List SLOW: []
15:47:22:ST3_smx:INFO: Holes
15:47:22:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:47:24:ST3_smx:INFO: ----> Checking Analog response
15:47:24:ST3_smx:INFO: ----> Checking broken channels
15:47:25:ST3_smx:INFO: Total # broken ch: 0
15:47:25:ST3_smx:INFO: List FAST: []
15:47:25:ST3_smx:INFO: List SLOW: []
15:47:25:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:47:25:febtest:INFO: 0-0 | XA-000-08-002-001-006-147-14 | 69.6 | 1171.5
15:47:25:febtest:INFO: 0-1 | XA-000-08-002-001-006-143-09 | 85.6 | 1112.1
15:47:25:febtest:INFO: 0-2 | XA-000-08-002-001-006-140-09 | 72.8 | 1165.6
15:47:26:febtest:INFO: 0-3 | XA-000-08-002-001-006-153-14 | 72.8 | 1165.6
15:47:26:febtest:INFO: 0-4 | XA-000-08-002-001-006-169-07 | 66.4 | 1183.3
15:47:26:febtest:INFO: 0-5 | XA-000-08-002-001-006-163-07 | 82.4 | 1141.9
15:47:26:febtest:INFO: 0-6 | XA-000-08-002-001-006-177-00 | 76.0 | 1171.5
15:47:27:febtest:INFO: 0-7 | XA-000-08-002-001-006-173-07 | 44.1 | 1489.0
15:47:27:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:47:31:ST3_smx:INFO: chip: 0-6 72.757530 C 1165.571835 mV
15:47:31:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:47:31:ST3_smx:INFO: Electrons
15:47:31:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:47:33:ST3_smx:INFO: ----> Checking Analog response
15:47:33:ST3_smx:INFO: ----> Checking broken channels
15:47:33:ST3_smx:INFO: Total # broken ch: 0
15:47:33:ST3_smx:INFO: List FAST: []
15:47:33:ST3_smx:INFO: List SLOW: []
15:47:33:ST3_smx:INFO: Holes
15:47:33:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:47:36:ST3_smx:INFO: ----> Checking Analog response
15:47:36:ST3_smx:INFO: ----> Checking broken channels
15:47:36:ST3_smx:INFO: Total # broken ch: 0
15:47:36:ST3_smx:INFO: List FAST: []
15:47:36:ST3_smx:INFO: List SLOW: []
15:47:36:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:47:36:febtest:INFO: 0-0 | XA-000-08-002-001-006-147-14 | 69.6 | 1171.5
15:47:36:febtest:INFO: 0-1 | XA-000-08-002-001-006-143-09 | 88.8 | 1112.1
15:47:37:febtest:INFO: 0-2 | XA-000-08-002-001-006-140-09 | 76.0 | 1159.7
15:47:37:febtest:INFO: 0-3 | XA-000-08-002-001-006-153-14 | 76.0 | 1165.6
15:47:37:febtest:INFO: 0-4 | XA-000-08-002-001-006-169-07 | 69.6 | 1183.3
15:47:37:febtest:INFO: 0-5 | XA-000-08-002-001-006-163-07 | 85.6 | 1141.9
15:47:37:febtest:INFO: 0-6 | XA-000-08-002-001-006-177-00 | 76.0 | 1159.7
15:47:38:febtest:INFO: 0-7 | XA-000-08-002-001-006-173-07 | 44.1 | 1578.5
15:47:38:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:47:42:ST3_smx:INFO: chip: 0-7 59.984250 C 1323.451500 mV
15:47:42:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:47:42:ST3_smx:INFO: Electrons
15:47:42:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:47:45:ST3_smx:INFO: ----> Checking Analog response
15:47:45:ST3_smx:INFO: ----> Checking broken channels
15:47:45:ST3_smx:INFO: Total # broken ch: 0
15:47:45:ST3_smx:INFO: List FAST: []
15:47:45:ST3_smx:INFO: List SLOW: []
15:47:45:ST3_smx:INFO: Holes
15:47:45:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:47:47:ST3_smx:INFO: ----> Checking Analog response
15:47:47:ST3_smx:INFO: ----> Checking broken channels
15:47:48:ST3_smx:INFO: Total # broken ch: 0
15:47:48:ST3_smx:INFO: List FAST: []
15:47:48:ST3_smx:INFO: List SLOW: []
15:47:48:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:47:48:febtest:INFO: 0-0 | XA-000-08-002-001-006-147-14 | 72.8 | 1171.5
15:47:48:febtest:INFO: 0-1 | XA-000-08-002-001-006-143-09 | 88.8 | 1106.2
15:47:48:febtest:INFO: 0-2 | XA-000-08-002-001-006-140-09 | 76.0 | 1159.7
15:47:48:febtest:INFO: 0-3 | XA-000-08-002-001-006-153-14 | 79.2 | 1165.6
15:47:49:febtest:INFO: 0-4 | XA-000-08-002-001-006-169-07 | 72.8 | 1183.3
15:47:49:febtest:INFO: 0-5 | XA-000-08-002-001-006-163-07 | 85.6 | 1141.9
15:47:49:febtest:INFO: 0-6 | XA-000-08-002-001-006-177-00 | 79.2 | 1159.7
15:47:49:febtest:INFO: 0-7 | XA-000-08-002-001-006-173-07 | 60.0 | 1415.3
############################################################
# S U M M A R Y #
############################################################
{'TEST_NAME': 'FEB-ASIC', 'TEST_DATE': '2023_10_09-15_46_05', 'OPERATOR': 'Irakli K.; ', 'PROJECT': 'Production', 'SITE': 'GSI', 'SETUP': 'GSI_TEST_SETUP_1', 'ASIC_ID': 'XA-000-08-002-001-006-173-07', 'FUSED_ID': 6359364699117611735, 'HW_ADDR': 7, 'VERS_NO': '2.2', 'CABLE_SET_ID': '', 'IC_TEMP': '0', 'VDDM': '0', 'AUX': '0', 'CSABIAS': '0', 'VDDM_INT': '0', 'ADC_Chi2': 0.0, 'ADC_NDF': 0, 'ADC_P0': 0.0, 'ADC_P1': 0.006824, 'ADC_P2': -2.485e-06, 'ADC_P0err': 0.001, 'ADC_P1err': 0.001, 'ADC_P2err': 1e-05, 'ADC_VREF_P': 58, 'ADC_VREF_N': 30, 'ADC_VREF_T': 128, 'ADC_VREF_TR': 122, 'THR2_GLB': 30, 'LOOP__PLS': 100, 'CALIB_PLS': 250, 'SnsLoop': 5, 'IFED': 31, 'CSA_BIAS': 15, 'CSA_Chi2': 0.0, 'CSA_NDF': 0, 'CSA_P0': 0.0, 'CSA_P1': 0.0, 'CSA_P2': 0.0, 'CSA_P0err': 0.0, 'CSA_P1err': 0.0, 'CSA_P2err': 0.0, 'CONF_FAIL_REG': 0, 'N_BROKEN_DISC': 0, 'N_BROKEN_FAST': '[]', 'N_BROKEN_SLOW': '[]', 'P_BROKEN_DISC': 0, 'P_BROKEN_FAST': '[]', 'P_BROKEN_SLOW': '[]', 'ASIC_QA_category': '', 'N_BROKEN_CABLE': 0, 'LIST_OF_BROKEN_CABLES': 0, 'VI_bInit': ['2.447', '1.9190', '1.845', '2.5520', '7.000', '1.5540', '7.000', '1.5540'], 'VI_aInit': ['0', '0', '0', '0', '0', '0'], 'VI_atEnd': ['0', '0', '0', '0', '0', '0'], 'AMP_CAL': 200, 'PlsLoop': 1, 'N_ANA_PRESENT': 'Analog response OK', 'N_DISC_FAIL_CH': 0, 'N_ANA_FAIL_CH': '0', 'P_ANA_PRESENT': 'Analog response OK', 'P_DISC_FAIL_CH': 0, 'P_ANA_FAIL_CH': '0'}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
15:48:26:ST3_Shared:INFO: /home/cbm/public_html/Production_LogDir//FEB/FEB_2013/B//TestDate_2023_10_09-15_46_05/