Go Back
FEB_2013 09.10.23 17:29:34
Info
17:29:24:ST3_hmp4040:INFO: HAMEG,HMP2030,017836163,HW50010002/SW2.30
17:29:24:febtest:INFO: FEB8.2 selected
17:29:24:smx_tester:INFO: Setting Elink clock mode to 160 MHz
17:29:34:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
17:29:34:ST3_Shared:INFO: --------------------------FEB-ASIC--------------------------
17:29:34:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
17:29:34:febtest:INFO: Tsting FEB with SN 2013
17:29:35:smx_tester:INFO: Scanning setup
17:29:35:elinks:INFO: Disabling clock on downlink 0
17:29:35:elinks:INFO: Disabling clock on downlink 1
17:29:35:elinks:INFO: Disabling clock on downlink 2
17:29:35:elinks:INFO: Disabling clock on downlink 3
17:29:35:elinks:INFO: Disabling clock on downlink 4
17:29:35:setup_element:INFO: Checking SOS, encoding_mode: SOS
17:29:35:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
17:29:35:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
17:29:35:elinks:INFO: Disabling clock on downlink 0
17:29:35:elinks:INFO: Disabling clock on downlink 1
17:29:35:elinks:INFO: Disabling clock on downlink 2
17:29:35:elinks:INFO: Disabling clock on downlink 3
17:29:35:elinks:INFO: Disabling clock on downlink 4
17:29:35:setup_element:INFO: Checking SOS, encoding_mode: SOS
17:29:35:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
17:29:35:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
17:29:35:elinks:INFO: Disabling clock on downlink 0
17:29:35:elinks:INFO: Disabling clock on downlink 1
17:29:35:elinks:INFO: Disabling clock on downlink 2
17:29:35:elinks:INFO: Disabling clock on downlink 3
17:29:35:elinks:INFO: Disabling clock on downlink 4
17:29:35:setup_element:INFO: Checking SOS, encoding_mode: SOS
17:29:35:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
17:29:36:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 16
17:29:36:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 17
17:29:36:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 18
17:29:36:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 19
17:29:36:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 20
17:29:36:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 21
17:29:36:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 22
17:29:36:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 23
17:29:36:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24
17:29:36:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25
17:29:36:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26
17:29:36:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27
17:29:36:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28
17:29:36:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29
17:29:36:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30
17:29:36:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31
17:29:36:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
17:29:36:elinks:INFO: Disabling clock on downlink 0
17:29:36:elinks:INFO: Disabling clock on downlink 1
17:29:36:elinks:INFO: Disabling clock on downlink 2
17:29:36:elinks:INFO: Disabling clock on downlink 3
17:29:36:elinks:INFO: Disabling clock on downlink 4
17:29:36:setup_element:INFO: Checking SOS, encoding_mode: SOS
17:29:36:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
17:29:36:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
17:29:36:elinks:INFO: Disabling clock on downlink 0
17:29:36:elinks:INFO: Disabling clock on downlink 1
17:29:36:elinks:INFO: Disabling clock on downlink 2
17:29:36:elinks:INFO: Disabling clock on downlink 3
17:29:36:elinks:INFO: Disabling clock on downlink 4
17:29:36:setup_element:INFO: Checking SOS, encoding_mode: SOS
17:29:36:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
17:29:36:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
17:29:36:setup_element:INFO: Scanning clock phase
17:29:36:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
17:29:36:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
17:29:36:setup_element:INFO: Clock phase scan results for group 0, downlink 2
17:29:36:setup_element:INFO: Eye window for uplink 16: ________________________________________________________________________XXXXXXXX
Clock Delay: 35
17:29:36:setup_element:INFO: Eye window for uplink 17: ________________________________________________________________________XXXXXXXX
Clock Delay: 35
17:29:36:setup_element:INFO: Eye window for uplink 18: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
17:29:36:setup_element:INFO: Eye window for uplink 19: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
17:29:36:setup_element:INFO: Eye window for uplink 20: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
17:29:36:setup_element:INFO: Eye window for uplink 21: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
17:29:36:setup_element:INFO: Eye window for uplink 22: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
17:29:36:setup_element:INFO: Eye window for uplink 23: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
17:29:36:setup_element:INFO: Eye window for uplink 24: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
17:29:36:setup_element:INFO: Eye window for uplink 25: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
17:29:36:setup_element:INFO: Eye window for uplink 26: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
17:29:36:setup_element:INFO: Eye window for uplink 27: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
17:29:36:setup_element:INFO: Eye window for uplink 28: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
17:29:36:setup_element:INFO: Eye window for uplink 29: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
17:29:36:setup_element:INFO: Eye window for uplink 30: X________________________________________________________________________XXXXXXX
Clock Delay: 36
17:29:36:setup_element:INFO: Eye window for uplink 31: X________________________________________________________________________XXXXXXX
Clock Delay: 36
17:29:36:setup_element:INFO: Setting the clock phase to 35 for group 0, downlink 2
17:29:36:setup_element:INFO: Scanning data phases
17:29:36:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
17:29:36:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
17:29:42:setup_element:INFO: Data phase scan results for group 0, downlink 2
17:29:42:setup_element:INFO: Eye window for uplink 16: XX___________________________________XXX
Data delay found: 19
17:29:42:setup_element:INFO: Eye window for uplink 17: _________________________________XXXX___
Data delay found: 14
17:29:42:setup_element:INFO: Eye window for uplink 18: __________________________________XXXXX_
Data delay found: 16
17:29:42:setup_element:INFO: Eye window for uplink 19: _______________________________XXXXX____
Data delay found: 13
17:29:42:setup_element:INFO: Eye window for uplink 20: __________________________________XXXXXX
Data delay found: 16
17:29:42:setup_element:INFO: Eye window for uplink 21: _________________________________XXXXX__
Data delay found: 15
17:29:42:setup_element:INFO: Eye window for uplink 22: __________________________________XXXXX_
Data delay found: 16
17:29:42:setup_element:INFO: Eye window for uplink 23: ________________________________XXXXX___
Data delay found: 14
17:29:42:setup_element:INFO: Eye window for uplink 24: ___XXXXX________________________________
Data delay found: 25
17:29:42:setup_element:INFO: Eye window for uplink 25: ______XXXXX_____________________________
Data delay found: 28
17:29:42:setup_element:INFO: Eye window for uplink 26: ____XXXXXX______________________________
Data delay found: 26
17:29:42:setup_element:INFO: Eye window for uplink 27: ________XXXXXX__________________________
Data delay found: 30
17:29:42:setup_element:INFO: Eye window for uplink 28: __________XXXXX_________________________
Data delay found: 32
17:29:42:setup_element:INFO: Eye window for uplink 29: ____________XXXXX_______________________
Data delay found: 34
17:29:42:setup_element:INFO: Eye window for uplink 30: _______________XXXXXX___________________
Data delay found: 37
17:29:42:setup_element:INFO: Eye window for uplink 31: ______________XXXXX_X___________________
Data delay found: 37
17:29:42:setup_element:INFO: Setting the data phase to 19 for uplink 16
17:29:42:setup_element:INFO: Setting the data phase to 14 for uplink 17
17:29:42:setup_element:INFO: Setting the data phase to 16 for uplink 18
17:29:42:setup_element:INFO: Setting the data phase to 13 for uplink 19
17:29:42:setup_element:INFO: Setting the data phase to 16 for uplink 20
17:29:42:setup_element:INFO: Setting the data phase to 15 for uplink 21
17:29:42:setup_element:INFO: Setting the data phase to 16 for uplink 22
17:29:42:setup_element:INFO: Setting the data phase to 14 for uplink 23
17:29:42:setup_element:INFO: Setting the data phase to 25 for uplink 24
17:29:42:setup_element:INFO: Setting the data phase to 28 for uplink 25
17:29:42:setup_element:INFO: Setting the data phase to 26 for uplink 26
17:29:42:setup_element:INFO: Setting the data phase to 30 for uplink 27
17:29:42:setup_element:INFO: Setting the data phase to 32 for uplink 28
17:29:42:setup_element:INFO: Setting the data phase to 34 for uplink 29
17:29:42:setup_element:INFO: Setting the data phase to 37 for uplink 30
17:29:42:setup_element:INFO: Setting the data phase to 37 for uplink 31
17:29:42:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 35
Window Length: 70
Eye Windows:
Uplink 16: ________________________________________________________________________XXXXXXXX
Uplink 17: ________________________________________________________________________XXXXXXXX
Uplink 18: _______________________________________________________________________XXXXXXXX_
Uplink 19: _______________________________________________________________________XXXXXXXX_
Uplink 20: _______________________________________________________________________XXXXXXXX_
Uplink 21: _______________________________________________________________________XXXXXXXX_
Uplink 22: _______________________________________________________________________XXXXXXXX_
Uplink 23: _______________________________________________________________________XXXXXXXX_
Uplink 24: _______________________________________________________________________XXXXXXX__
Uplink 25: _______________________________________________________________________XXXXXXX__
Uplink 26: _______________________________________________________________________XXXXXXXX_
Uplink 27: _______________________________________________________________________XXXXXXXX_
Uplink 28: _______________________________________________________________________XXXXXXXX_
Uplink 29: _______________________________________________________________________XXXXXXXX_
Uplink 30: X________________________________________________________________________XXXXXXX
Uplink 31: X________________________________________________________________________XXXXXXX
Data phase characteristics:
Uplink 16:
Optimal Phase: 19
Window Length: 35
Eye Window: XX___________________________________XXX
Uplink 17:
Optimal Phase: 14
Window Length: 36
Eye Window: _________________________________XXXX___
Uplink 18:
Optimal Phase: 16
Window Length: 35
Eye Window: __________________________________XXXXX_
Uplink 19:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 20:
Optimal Phase: 16
Window Length: 34
Eye Window: __________________________________XXXXXX
Uplink 21:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
Uplink 22:
Optimal Phase: 16
Window Length: 35
Eye Window: __________________________________XXXXX_
Uplink 23:
Optimal Phase: 14
Window Length: 35
Eye Window: ________________________________XXXXX___
Uplink 24:
Optimal Phase: 25
Window Length: 35
Eye Window: ___XXXXX________________________________
Uplink 25:
Optimal Phase: 28
Window Length: 35
Eye Window: ______XXXXX_____________________________
Uplink 26:
Optimal Phase: 26
Window Length: 34
Eye Window: ____XXXXXX______________________________
Uplink 27:
Optimal Phase: 30
Window Length: 34
Eye Window: ________XXXXXX__________________________
Uplink 28:
Optimal Phase: 32
Window Length: 35
Eye Window: __________XXXXX_________________________
Uplink 29:
Optimal Phase: 34
Window Length: 35
Eye Window: ____________XXXXX_______________________
Uplink 30:
Optimal Phase: 37
Window Length: 34
Eye Window: _______________XXXXXX___________________
Uplink 31:
Optimal Phase: 37
Window Length: 33
Eye Window: ______________XXXXX_X___________________
]
17:29:42:setup_element:INFO: Beginning SMX ASICs map scan
17:29:42:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
17:29:42:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
17:29:42:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
17:29:42:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
17:29:42:uplink:INFO: Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
17:29:42:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 23
17:29:42:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 22
17:29:42:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 30
17:29:42:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 31
17:29:43:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 21
17:29:43:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 20
17:29:43:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28
17:29:43:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 29
17:29:43:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 19
17:29:43:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 18
17:29:43:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26
17:29:43:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 27
17:29:43:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 17
17:29:43:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 16
17:29:43:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 24
17:29:44:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 25
17:29:45:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 23), (1, 22)
ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
ASIC address 0x2: (ASIC uplink, uplink): (0, 21), (1, 20)
ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
ASIC address 0x4: (ASIC uplink, uplink): (0, 19), (1, 18)
ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
ASIC address 0x6: (ASIC uplink, uplink): (0, 17), (1, 16)
ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
Clock Phase Characteristic:
Optimal Phase: 35
Window Length: 70
Eye Windows:
Uplink 16: ________________________________________________________________________XXXXXXXX
Uplink 17: ________________________________________________________________________XXXXXXXX
Uplink 18: _______________________________________________________________________XXXXXXXX_
Uplink 19: _______________________________________________________________________XXXXXXXX_
Uplink 20: _______________________________________________________________________XXXXXXXX_
Uplink 21: _______________________________________________________________________XXXXXXXX_
Uplink 22: _______________________________________________________________________XXXXXXXX_
Uplink 23: _______________________________________________________________________XXXXXXXX_
Uplink 24: _______________________________________________________________________XXXXXXX__
Uplink 25: _______________________________________________________________________XXXXXXX__
Uplink 26: _______________________________________________________________________XXXXXXXX_
Uplink 27: _______________________________________________________________________XXXXXXXX_
Uplink 28: _______________________________________________________________________XXXXXXXX_
Uplink 29: _______________________________________________________________________XXXXXXXX_
Uplink 30: X________________________________________________________________________XXXXXXX
Uplink 31: X________________________________________________________________________XXXXXXX
Data phase characteristics:
Uplink 16:
Optimal Phase: 19
Window Length: 35
Eye Window: XX___________________________________XXX
Uplink 17:
Optimal Phase: 14
Window Length: 36
Eye Window: _________________________________XXXX___
Uplink 18:
Optimal Phase: 16
Window Length: 35
Eye Window: __________________________________XXXXX_
Uplink 19:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 20:
Optimal Phase: 16
Window Length: 34
Eye Window: __________________________________XXXXXX
Uplink 21:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
Uplink 22:
Optimal Phase: 16
Window Length: 35
Eye Window: __________________________________XXXXX_
Uplink 23:
Optimal Phase: 14
Window Length: 35
Eye Window: ________________________________XXXXX___
Uplink 24:
Optimal Phase: 25
Window Length: 35
Eye Window: ___XXXXX________________________________
Uplink 25:
Optimal Phase: 28
Window Length: 35
Eye Window: ______XXXXX_____________________________
Uplink 26:
Optimal Phase: 26
Window Length: 34
Eye Window: ____XXXXXX______________________________
Uplink 27:
Optimal Phase: 30
Window Length: 34
Eye Window: ________XXXXXX__________________________
Uplink 28:
Optimal Phase: 32
Window Length: 35
Eye Window: __________XXXXX_________________________
Uplink 29:
Optimal Phase: 34
Window Length: 35
Eye Window: ____________XXXXX_______________________
Uplink 30:
Optimal Phase: 37
Window Length: 34
Eye Window: _______________XXXXXX___________________
Uplink 31:
Optimal Phase: 37
Window Length: 33
Eye Window: ______________XXXXX_X___________________
17:29:45:setup_element:INFO: Performing Elink synchronization
17:29:45:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
17:29:45:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
17:29:45:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
17:29:45:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
17:29:45:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2
17:29:45:uplink:INFO: Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
17:29:45:ST3_emu:INFO: Number of chips: 8
17:29:45:ST3_emu:INFO: Chip address: 0x0
17:29:45:ST3_emu:INFO: Chip address: 0x1
17:29:45:ST3_emu:INFO: Chip address: 0x2
17:29:45:ST3_emu:INFO: Chip address: 0x3
17:29:45:ST3_emu:INFO: Chip address: 0x4
17:29:45:ST3_emu:INFO: Chip address: 0x5
17:29:45:ST3_emu:INFO: Chip address: 0x6
17:29:45:ST3_emu:INFO: Chip address: 0x7
17:29:46:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
17:29:46:febtest:INFO: 0-0 | XA-000-08-002-001-006-147-14 | 40.9 | 1212.7
17:29:47:febtest:INFO: 0-1 | XA-000-08-002-001-006-143-09 | 69.6 | 1106.2
17:29:47:febtest:INFO: 0-2 | XA-000-08-002-001-006-140-09 | 47.3 | 1195.1
17:29:47:febtest:INFO: 0-3 | XA-000-08-002-001-006-153-14 | 47.3 | 1201.0
17:29:47:febtest:INFO: 0-4 | XA-000-08-002-001-006-169-07 | 44.1 | 1201.0
17:29:48:febtest:INFO: 0-5 | XA-000-08-002-001-006-163-07 | 60.0 | 1153.7
17:29:48:febtest:INFO: 0-6 | XA-000-08-002-001-006-177-00 | 50.4 | 1177.4
17:29:48:febtest:INFO: 0-7 | XA-000-08-002-001-006-173-07 | 34.6 | 1253.7
17:29:48:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
17:29:52:ST3_smx:INFO: chip: 0-0 44.073563 C 1183.292940 mV
17:29:52:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
17:29:52:ST3_smx:INFO: Electrons
17:29:52:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
17:29:54:ST3_smx:INFO: ----> Checking Analog response
17:29:54:ST3_smx:INFO: ----> Checking broken channels
17:29:55:ST3_smx:INFO: Total # broken ch: 0
17:29:55:ST3_smx:INFO: List FAST: []
17:29:55:ST3_smx:INFO: List SLOW: []
17:29:55:ST3_smx:INFO: Holes
17:29:55:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
17:29:57:ST3_smx:INFO: ----> Checking Analog response
17:29:57:ST3_smx:INFO: ----> Checking broken channels
17:29:57:ST3_smx:INFO: Total # broken ch: 0
17:29:57:ST3_smx:INFO: List FAST: []
17:29:57:ST3_smx:INFO: List SLOW: []
17:29:57:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
17:29:57:febtest:INFO: 0-0 | XA-000-08-002-001-006-147-14 | 47.3 | 1177.4
17:29:57:febtest:INFO: 0-1 | XA-000-08-002-001-006-143-09 | 72.8 | 1106.2
17:29:58:febtest:INFO: 0-2 | XA-000-08-002-001-006-140-09 | 47.3 | 1189.2
17:29:58:febtest:INFO: 0-3 | XA-000-08-002-001-006-153-14 | 47.3 | 1201.0
17:29:58:febtest:INFO: 0-4 | XA-000-08-002-001-006-169-07 | 44.1 | 1201.0
17:29:58:febtest:INFO: 0-5 | XA-000-08-002-001-006-163-07 | 63.2 | 1153.7
17:29:58:febtest:INFO: 0-6 | XA-000-08-002-001-006-177-00 | 53.6 | 1177.4
17:29:59:febtest:INFO: 0-7 | XA-000-08-002-001-006-173-07 | 37.7 | 1259.6
17:29:59:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
17:30:03:ST3_smx:INFO: chip: 0-1 66.365920 C 1118.096875 mV
17:30:03:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
17:30:03:ST3_smx:INFO: Electrons
17:30:03:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
17:30:05:ST3_smx:INFO: ----> Checking Analog response
17:30:05:ST3_smx:INFO: ----> Checking broken channels
17:30:05:ST3_smx:INFO: Total # broken ch: 0
17:30:05:ST3_smx:INFO: List FAST: []
17:30:05:ST3_smx:INFO: List SLOW: []
17:30:05:ST3_smx:INFO: Holes
17:30:05:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
17:30:07:ST3_smx:INFO: ----> Checking Analog response
17:30:07:ST3_smx:INFO: ----> Checking broken channels
17:30:07:ST3_smx:INFO: Total # broken ch: 0
17:30:07:ST3_smx:INFO: List FAST: []
17:30:07:ST3_smx:INFO: List SLOW: []
17:30:07:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
17:30:08:febtest:INFO: 0-0 | XA-000-08-002-001-006-147-14 | 50.4 | 1177.4
17:30:08:febtest:INFO: 0-1 | XA-000-08-002-001-006-143-09 | 69.6 | 1112.1
17:30:08:febtest:INFO: 0-2 | XA-000-08-002-001-006-140-09 | 50.4 | 1189.2
17:30:08:febtest:INFO: 0-3 | XA-000-08-002-001-006-153-14 | 50.4 | 1195.1
17:30:09:febtest:INFO: 0-4 | XA-000-08-002-001-006-169-07 | 47.3 | 1201.0
17:30:09:febtest:INFO: 0-5 | XA-000-08-002-001-006-163-07 | 66.4 | 1147.8
17:30:09:febtest:INFO: 0-6 | XA-000-08-002-001-006-177-00 | 56.8 | 1177.4
17:30:09:febtest:INFO: 0-7 | XA-000-08-002-001-006-173-07 | 37.7 | 1259.6
17:30:10:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
17:30:13:ST3_smx:INFO: chip: 0-2 53.612520 C 1171.483840 mV
17:30:13:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
17:30:13:ST3_smx:INFO: Electrons
17:30:13:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
17:30:15:ST3_smx:INFO: ----> Checking Analog response
17:30:15:ST3_smx:INFO: ----> Checking broken channels
17:30:15:ST3_smx:INFO: Total # broken ch: 0
17:30:15:ST3_smx:INFO: List FAST: []
17:30:15:ST3_smx:INFO: List SLOW: []
17:30:15:ST3_smx:INFO: Holes
17:30:15:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
17:30:17:ST3_smx:INFO: ----> Checking Analog response
17:30:17:ST3_smx:INFO: ----> Checking broken channels
17:30:18:ST3_smx:INFO: Total # broken ch: 0
17:30:18:ST3_smx:INFO: List FAST: []
17:30:18:ST3_smx:INFO: List SLOW: []
17:30:18:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
17:30:18:febtest:INFO: 0-0 | XA-000-08-002-001-006-147-14 | 53.6 | 1177.4
17:30:18:febtest:INFO: 0-1 | XA-000-08-002-001-006-143-09 | 69.6 | 1112.1
17:30:18:febtest:INFO: 0-2 | XA-000-08-002-001-006-140-09 | 56.8 | 1171.5
17:30:18:febtest:INFO: 0-3 | XA-000-08-002-001-006-153-14 | 53.6 | 1195.1
17:30:19:febtest:INFO: 0-4 | XA-000-08-002-001-006-169-07 | 50.4 | 1201.0
17:30:19:febtest:INFO: 0-5 | XA-000-08-002-001-006-163-07 | 66.4 | 1147.8
17:30:19:febtest:INFO: 0-6 | XA-000-08-002-001-006-177-00 | 56.8 | 1171.5
17:30:19:febtest:INFO: 0-7 | XA-000-08-002-001-006-173-07 | 40.9 | 1265.4
17:30:20:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
17:30:23:ST3_smx:INFO: chip: 0-3 53.612520 C 1177.390875 mV
17:30:23:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
17:30:23:ST3_smx:INFO: Electrons
17:30:23:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
17:30:25:ST3_smx:INFO: ----> Checking Analog response
17:30:25:ST3_smx:INFO: ----> Checking broken channels
17:30:26:ST3_smx:INFO: Total # broken ch: 0
17:30:26:ST3_smx:INFO: List FAST: []
17:30:26:ST3_smx:INFO: List SLOW: []
17:30:26:ST3_smx:INFO: Holes
17:30:26:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
17:30:27:ST3_smx:INFO: ----> Checking Analog response
17:30:27:ST3_smx:INFO: ----> Checking broken channels
17:30:28:ST3_smx:INFO: Total # broken ch: 0
17:30:28:ST3_smx:INFO: List FAST: []
17:30:28:ST3_smx:INFO: List SLOW: []
17:30:28:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
17:30:28:febtest:INFO: 0-0 | XA-000-08-002-001-006-147-14 | 53.6 | 1177.4
17:30:28:febtest:INFO: 0-1 | XA-000-08-002-001-006-143-09 | 72.8 | 1112.1
17:30:28:febtest:INFO: 0-2 | XA-000-08-002-001-006-140-09 | 56.8 | 1171.5
17:30:29:febtest:INFO: 0-3 | XA-000-08-002-001-006-153-14 | 56.8 | 1171.5
17:30:29:febtest:INFO: 0-4 | XA-000-08-002-001-006-169-07 | 50.4 | 1201.0
17:30:29:febtest:INFO: 0-5 | XA-000-08-002-001-006-163-07 | 69.6 | 1141.9
17:30:29:febtest:INFO: 0-6 | XA-000-08-002-001-006-177-00 | 60.0 | 1171.5
17:30:30:febtest:INFO: 0-7 | XA-000-08-002-001-006-173-07 | 40.9 | 1265.4
17:30:30:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
17:30:34:ST3_smx:INFO: chip: 0-4 50.430383 C 1195.082160 mV
17:30:34:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
17:30:34:ST3_smx:INFO: Electrons
17:30:34:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
17:30:36:ST3_smx:INFO: ----> Checking Analog response
17:30:36:ST3_smx:INFO: ----> Checking broken channels
17:30:36:ST3_smx:INFO: Total # broken ch: 0
17:30:36:ST3_smx:INFO: List FAST: []
17:30:36:ST3_smx:INFO: List SLOW: []
17:30:36:ST3_smx:INFO: Holes
17:30:36:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
17:30:38:ST3_smx:INFO: ----> Checking Analog response
17:30:38:ST3_smx:INFO: ----> Checking broken channels
17:30:38:ST3_smx:INFO: Total # broken ch: 0
17:30:38:ST3_smx:INFO: List FAST: []
17:30:38:ST3_smx:INFO: List SLOW: []
17:30:38:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
17:30:38:febtest:INFO: 0-0 | XA-000-08-002-001-006-147-14 | 56.8 | 1177.4
17:30:39:febtest:INFO: 0-1 | XA-000-08-002-001-006-143-09 | 76.0 | 1112.1
17:30:39:febtest:INFO: 0-2 | XA-000-08-002-001-006-140-09 | 60.0 | 1165.6
17:30:39:febtest:INFO: 0-3 | XA-000-08-002-001-006-153-14 | 60.0 | 1171.5
17:30:39:febtest:INFO: 0-4 | XA-000-08-002-001-006-169-07 | 53.6 | 1189.2
17:30:40:febtest:INFO: 0-5 | XA-000-08-002-001-006-163-07 | 72.8 | 1147.8
17:30:40:febtest:INFO: 0-6 | XA-000-08-002-001-006-177-00 | 63.2 | 1171.5
17:30:40:febtest:INFO: 0-7 | XA-000-08-002-001-006-173-07 | 44.1 | 1271.2
17:30:40:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
17:30:44:ST3_smx:INFO: chip: 0-5 69.560482 C 1147.806000 mV
17:30:44:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
17:30:44:ST3_smx:INFO: Electrons
17:30:44:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
17:30:46:ST3_smx:INFO: ----> Checking Analog response
17:30:46:ST3_smx:INFO: ----> Checking broken channels
17:30:47:ST3_smx:INFO: Total # broken ch: 0
17:30:47:ST3_smx:INFO: List FAST: []
17:30:47:ST3_smx:INFO: List SLOW: []
17:30:47:ST3_smx:INFO: Holes
17:30:47:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
17:30:49:ST3_smx:INFO: ----> Checking Analog response
17:30:49:ST3_smx:INFO: ----> Checking broken channels
17:30:49:ST3_smx:INFO: Total # broken ch: 0
17:30:49:ST3_smx:INFO: List FAST: []
17:30:49:ST3_smx:INFO: List SLOW: []
17:30:49:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
17:30:49:febtest:INFO: 0-0 | XA-000-08-002-001-006-147-14 | 60.0 | 1171.5
17:30:49:febtest:INFO: 0-1 | XA-000-08-002-001-006-143-09 | 76.0 | 1106.2
17:30:50:febtest:INFO: 0-2 | XA-000-08-002-001-006-140-09 | 60.0 | 1165.6
17:30:50:febtest:INFO: 0-3 | XA-000-08-002-001-006-153-14 | 63.2 | 1171.5
17:30:50:febtest:INFO: 0-4 | XA-000-08-002-001-006-169-07 | 56.8 | 1189.2
17:30:50:febtest:INFO: 0-5 | XA-000-08-002-001-006-163-07 | 72.8 | 1141.9
17:30:51:febtest:INFO: 0-6 | XA-000-08-002-001-006-177-00 | 66.4 | 1171.5
17:30:51:febtest:INFO: 0-7 | XA-000-08-002-001-006-173-07 | 44.1 | 1277.1
17:30:51:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
17:30:55:ST3_smx:INFO: chip: 0-6 63.173842 C 1165.571835 mV
17:30:55:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
17:30:55:ST3_smx:INFO: Electrons
17:30:55:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
17:30:57:ST3_smx:INFO: ----> Checking Analog response
17:30:57:ST3_smx:INFO: ----> Checking broken channels
17:30:57:ST3_smx:INFO: Total # broken ch: 0
17:30:57:ST3_smx:INFO: List FAST: []
17:30:57:ST3_smx:INFO: List SLOW: []
17:30:57:ST3_smx:INFO: Holes
17:30:57:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
17:30:59:ST3_smx:INFO: ----> Checking Analog response
17:30:59:ST3_smx:INFO: ----> Checking broken channels
17:31:00:ST3_smx:INFO: Total # broken ch: 0
17:31:00:ST3_smx:INFO: List FAST: []
17:31:00:ST3_smx:INFO: List SLOW: []
17:31:00:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
17:31:00:febtest:INFO: 0-0 | XA-000-08-002-001-006-147-14 | 60.0 | 1171.5
17:31:00:febtest:INFO: 0-1 | XA-000-08-002-001-006-143-09 | 79.2 | 1106.2
17:31:00:febtest:INFO: 0-2 | XA-000-08-002-001-006-140-09 | 63.2 | 1159.7
17:31:00:febtest:INFO: 0-3 | XA-000-08-002-001-006-153-14 | 63.2 | 1171.5
17:31:01:febtest:INFO: 0-4 | XA-000-08-002-001-006-169-07 | 56.8 | 1183.3
17:31:01:febtest:INFO: 0-5 | XA-000-08-002-001-006-163-07 | 72.8 | 1141.9
17:31:01:febtest:INFO: 0-6 | XA-000-08-002-001-006-177-00 | 66.4 | 1165.6
17:31:01:febtest:INFO: 0-7 | XA-000-08-002-001-006-173-07 | 44.1 | 1294.5
17:31:02:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
17:31:06:ST3_smx:INFO: chip: 0-7 59.984250 C 1212.728715 mV
17:31:06:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
17:31:06:ST3_smx:INFO: Electrons
17:31:06:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
17:31:08:ST3_smx:INFO: ----> Checking Analog response
17:31:08:ST3_smx:INFO: ----> Checking broken channels
17:31:08:ST3_smx:INFO: Total # broken ch: 0
17:31:08:ST3_smx:INFO: List FAST: []
17:31:08:ST3_smx:INFO: List SLOW: []
17:31:08:ST3_smx:INFO: Holes
17:31:08:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
17:31:10:ST3_smx:INFO: ----> Checking Analog response
17:31:10:ST3_smx:INFO: ----> Checking broken channels
17:31:11:ST3_smx:INFO: Total # broken ch: 0
17:31:11:ST3_smx:INFO: List FAST: []
17:31:11:ST3_smx:INFO: List SLOW: []
17:31:11:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
17:31:11:febtest:INFO: 0-0 | XA-000-08-002-001-006-147-14 | 63.2 | 1171.5
17:31:11:febtest:INFO: 0-1 | XA-000-08-002-001-006-143-09 | 79.2 | 1106.2
17:31:11:febtest:INFO: 0-2 | XA-000-08-002-001-006-140-09 | 66.4 | 1165.6
17:31:11:febtest:INFO: 0-3 | XA-000-08-002-001-006-153-14 | 66.4 | 1165.6
17:31:12:febtest:INFO: 0-4 | XA-000-08-002-001-006-169-07 | 60.0 | 1183.3
17:31:12:febtest:INFO: 0-5 | XA-000-08-002-001-006-163-07 | 76.0 | 1141.9
17:31:12:febtest:INFO: 0-6 | XA-000-08-002-001-006-177-00 | 66.4 | 1165.6
17:31:12:febtest:INFO: 0-7 | XA-000-08-002-001-006-173-07 | 60.0 | 1224.5
############################################################
# S U M M A R Y #
############################################################
{'TEST_NAME': 'FEB-ASIC', 'TEST_DATE': '2023_10_09-17_29_34', 'OPERATOR': 'Alois Alzheimer', 'PROJECT': 'Production', 'SITE': 'GSI', 'SETUP': 'GSI_TEST_SETUP_1', 'ASIC_ID': 'XA-000-08-002-001-006-173-07', 'FUSED_ID': 6359364699117611735, 'HW_ADDR': 7, 'VERS_NO': '2.2', 'CABLE_SET_ID': '', 'IC_TEMP': '0', 'VDDM': '0', 'AUX': '0', 'CSABIAS': '0', 'VDDM_INT': '0', 'ADC_Chi2': 0.0, 'ADC_NDF': 0, 'ADC_P0': 0.0, 'ADC_P1': 0.006824, 'ADC_P2': -2.485e-06, 'ADC_P0err': 0.001, 'ADC_P1err': 0.001, 'ADC_P2err': 1e-05, 'ADC_VREF_P': 58, 'ADC_VREF_N': 30, 'ADC_VREF_T': 128, 'ADC_VREF_TR': 122, 'THR2_GLB': 30, 'LOOP__PLS': 100, 'CALIB_PLS': 250, 'SnsLoop': 5, 'IFED': 31, 'CSA_BIAS': 15, 'CSA_Chi2': 0.0, 'CSA_NDF': 0, 'CSA_P0': 0.0, 'CSA_P1': 0.0, 'CSA_P2': 0.0, 'CSA_P0err': 0.0, 'CSA_P1err': 0.0, 'CSA_P2err': 0.0, 'CONF_FAIL_REG': 0, 'N_BROKEN_DISC': 0, 'N_BROKEN_FAST': '[]', 'N_BROKEN_SLOW': '[]', 'P_BROKEN_DISC': 0, 'P_BROKEN_FAST': '[]', 'P_BROKEN_SLOW': '[]', 'ASIC_QA_category': '', 'N_BROKEN_CABLE': 0, 'LIST_OF_BROKEN_CABLES': 0, 'VI_bInit': ['2.447', '1.9370', '1.846', '2.6730', '7.000', '1.5550', '7.000', '1.5550'], 'VI_aInit': ['0', '0', '0', '0', '0', '0'], 'VI_atEnd': ['0', '0', '0', '0', '0', '0'], 'AMP_CAL': 125, 'PlsLoop': 1, 'N_ANA_PRESENT': 'Analog response OK', 'N_DISC_FAIL_CH': 0, 'N_ANA_FAIL_CH': '0', 'P_ANA_PRESENT': 'Analog response OK', 'P_DISC_FAIL_CH': 0, 'P_ANA_FAIL_CH': '0'}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
17:31:19:ST3_Shared:INFO: /home/cbm/public_html/Production_LogDir//FEB/FEB_2013/TestDate_2023_10_09-17_29_34/