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FEB_2013 12.02.24 14:54:34
TextEdit.txt
14:54:27:ST3_hmp4040:INFO: ROHDE&SCHWARZ,HMP4040,123796,HW50020003/SW2.71
14:54:27:febtest:INFO: FEB 8-2 selected
14:54:27:smx_tester:INFO: Setting Elink clock mode to 160 MHz
14:54:35:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:54:35:ST3_Shared:INFO: --------------------------FEB-ASIC--------------------------
14:54:35:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:54:35:febtest:INFO: Testing FEB with SN 2013
14:54:38:smx_tester:INFO: Scanning setup
14:54:38:elinks:INFO: Disabling clock on downlink 0
14:54:38:elinks:INFO: Disabling clock on downlink 1
14:54:38:elinks:INFO: Disabling clock on downlink 2
14:54:38:elinks:INFO: Disabling clock on downlink 3
14:54:38:elinks:INFO: Disabling clock on downlink 4
14:54:38:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:54:38:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
14:54:38:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:54:38:elinks:INFO: Disabling clock on downlink 0
14:54:38:elinks:INFO: Disabling clock on downlink 1
14:54:38:elinks:INFO: Disabling clock on downlink 2
14:54:38:elinks:INFO: Disabling clock on downlink 3
14:54:38:elinks:INFO: Disabling clock on downlink 4
14:54:38:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:54:38:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
14:54:38:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:54:38:elinks:INFO: Disabling clock on downlink 0
14:54:38:elinks:INFO: Disabling clock on downlink 1
14:54:38:elinks:INFO: Disabling clock on downlink 2
14:54:38:elinks:INFO: Disabling clock on downlink 3
14:54:38:elinks:INFO: Disabling clock on downlink 4
14:54:38:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:54:38:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
14:54:38:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 16
14:54:38:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 17
14:54:38:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 18
14:54:38:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 19
14:54:38:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 20
14:54:38:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 21
14:54:38:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 22
14:54:38:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 23
14:54:38:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24
14:54:38:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25
14:54:38:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26
14:54:38:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27
14:54:38:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28
14:54:38:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29
14:54:38:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30
14:54:38:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31
14:54:38:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:54:38:elinks:INFO: Disabling clock on downlink 0
14:54:38:elinks:INFO: Disabling clock on downlink 1
14:54:38:elinks:INFO: Disabling clock on downlink 2
14:54:38:elinks:INFO: Disabling clock on downlink 3
14:54:38:elinks:INFO: Disabling clock on downlink 4
14:54:38:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:54:38:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
14:54:38:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:54:38:elinks:INFO: Disabling clock on downlink 0
14:54:38:elinks:INFO: Disabling clock on downlink 1
14:54:38:elinks:INFO: Disabling clock on downlink 2
14:54:38:elinks:INFO: Disabling clock on downlink 3
14:54:38:elinks:INFO: Disabling clock on downlink 4
14:54:38:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:54:38:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
14:54:39:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:54:39:setup_element:INFO: Scanning clock phase
14:54:39:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
14:54:39:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
14:54:39:setup_element:INFO: Clock phase scan results for group 0, downlink 2
14:54:39:setup_element:INFO: Eye window for uplink 16: X_______________________________________________________________________XXXXXXXX
Clock Delay: 36
14:54:39:setup_element:INFO: Eye window for uplink 17: X_______________________________________________________________________XXXXXXXX
Clock Delay: 36
14:54:39:setup_element:INFO: Eye window for uplink 18: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
14:54:39:setup_element:INFO: Eye window for uplink 19: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
14:54:39:setup_element:INFO: Eye window for uplink 20: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
14:54:39:setup_element:INFO: Eye window for uplink 21: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
14:54:39:setup_element:INFO: Eye window for uplink 22: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
14:54:39:setup_element:INFO: Eye window for uplink 23: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
14:54:39:setup_element:INFO: Eye window for uplink 24: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
14:54:39:setup_element:INFO: Eye window for uplink 25: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
14:54:39:setup_element:INFO: Eye window for uplink 26: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
14:54:39:setup_element:INFO: Eye window for uplink 27: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
14:54:39:setup_element:INFO: Eye window for uplink 28: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
14:54:39:setup_element:INFO: Eye window for uplink 29: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
14:54:39:setup_element:INFO: Eye window for uplink 30: XX________________________________________________________________________XXXXXX
Clock Delay: 37
14:54:39:setup_element:INFO: Eye window for uplink 31: XX________________________________________________________________________XXXXXX
Clock Delay: 37
14:54:39:setup_element:INFO: Setting the clock phase to 36 for group 0, downlink 2
14:54:39:setup_element:INFO: Scanning data phases
14:54:39:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
14:54:39:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
14:54:44:setup_element:INFO: Data phase scan results for group 0, downlink 2
14:54:45:setup_element:INFO: Eye window for uplink 16: XX___________________________________XXX
Data delay found: 19
14:54:45:setup_element:INFO: Eye window for uplink 17: _________________________________XXXX___
Data delay found: 14
14:54:45:setup_element:INFO: Eye window for uplink 18: __________________________________XXXXX_
Data delay found: 16
14:54:45:setup_element:INFO: Eye window for uplink 19: _______________________________XXXXX____
Data delay found: 13
14:54:45:setup_element:INFO: Eye window for uplink 20: __________________________________XXXXXX
Data delay found: 16
14:54:45:setup_element:INFO: Eye window for uplink 21: _________________________________XXXXX__
Data delay found: 15
14:54:45:setup_element:INFO: Eye window for uplink 22: __________________________________XXXX__
Data delay found: 15
14:54:45:setup_element:INFO: Eye window for uplink 23: ________________________________XXXXX___
Data delay found: 14
14:54:45:setup_element:INFO: Eye window for uplink 24: ___XXXXX________________________________
Data delay found: 25
14:54:45:setup_element:INFO: Eye window for uplink 25: ______XXXXX_____________________________
Data delay found: 28
14:54:45:setup_element:INFO: Eye window for uplink 26: _____XXXXX______________________________
Data delay found: 27
14:54:45:setup_element:INFO: Eye window for uplink 27: ________XXXXXX__________________________
Data delay found: 30
14:54:45:setup_element:INFO: Eye window for uplink 28: _________XXXXX__________________________
Data delay found: 31
14:54:45:setup_element:INFO: Eye window for uplink 29: ___________XXXXX________________________
Data delay found: 33
14:54:45:setup_element:INFO: Eye window for uplink 30: _______________XXXXXX___________________
Data delay found: 37
14:54:45:setup_element:INFO: Eye window for uplink 31: ______________XXXXX_____________________
Data delay found: 36
14:54:45:setup_element:INFO: Setting the data phase to 19 for uplink 16
14:54:45:setup_element:INFO: Setting the data phase to 14 for uplink 17
14:54:45:setup_element:INFO: Setting the data phase to 16 for uplink 18
14:54:45:setup_element:INFO: Setting the data phase to 13 for uplink 19
14:54:45:setup_element:INFO: Setting the data phase to 16 for uplink 20
14:54:45:setup_element:INFO: Setting the data phase to 15 for uplink 21
14:54:45:setup_element:INFO: Setting the data phase to 15 for uplink 22
14:54:45:setup_element:INFO: Setting the data phase to 14 for uplink 23
14:54:45:setup_element:INFO: Setting the data phase to 25 for uplink 24
14:54:45:setup_element:INFO: Setting the data phase to 28 for uplink 25
14:54:45:setup_element:INFO: Setting the data phase to 27 for uplink 26
14:54:45:setup_element:INFO: Setting the data phase to 30 for uplink 27
14:54:45:setup_element:INFO: Setting the data phase to 31 for uplink 28
14:54:45:setup_element:INFO: Setting the data phase to 33 for uplink 29
14:54:45:setup_element:INFO: Setting the data phase to 37 for uplink 30
14:54:45:setup_element:INFO: Setting the data phase to 36 for uplink 31
14:54:45:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 36
Window Length: 69
Eye Windows:
Uplink 16: X_______________________________________________________________________XXXXXXXX
Uplink 17: X_______________________________________________________________________XXXXXXXX
Uplink 18: _______________________________________________________________________XXXXXXXX_
Uplink 19: _______________________________________________________________________XXXXXXXX_
Uplink 20: _______________________________________________________________________XXXXXXXX_
Uplink 21: _______________________________________________________________________XXXXXXXX_
Uplink 22: _______________________________________________________________________XXXXXXXX_
Uplink 23: _______________________________________________________________________XXXXXXXX_
Uplink 24: _______________________________________________________________________XXXXXXX__
Uplink 25: _______________________________________________________________________XXXXXXX__
Uplink 26: _______________________________________________________________________XXXXXXXX_
Uplink 27: _______________________________________________________________________XXXXXXXX_
Uplink 28: _______________________________________________________________________XXXXXXXX_
Uplink 29: _______________________________________________________________________XXXXXXXX_
Uplink 30: XX________________________________________________________________________XXXXXX
Uplink 31: XX________________________________________________________________________XXXXXX
Data phase characteristics:
Uplink 16:
Optimal Phase: 19
Window Length: 35
Eye Window: XX___________________________________XXX
Uplink 17:
Optimal Phase: 14
Window Length: 36
Eye Window: _________________________________XXXX___
Uplink 18:
Optimal Phase: 16
Window Length: 35
Eye Window: __________________________________XXXXX_
Uplink 19:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 20:
Optimal Phase: 16
Window Length: 34
Eye Window: __________________________________XXXXXX
Uplink 21:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
Uplink 22:
Optimal Phase: 15
Window Length: 36
Eye Window: __________________________________XXXX__
Uplink 23:
Optimal Phase: 14
Window Length: 35
Eye Window: ________________________________XXXXX___
Uplink 24:
Optimal Phase: 25
Window Length: 35
Eye Window: ___XXXXX________________________________
Uplink 25:
Optimal Phase: 28
Window Length: 35
Eye Window: ______XXXXX_____________________________
Uplink 26:
Optimal Phase: 27
Window Length: 35
Eye Window: _____XXXXX______________________________
Uplink 27:
Optimal Phase: 30
Window Length: 34
Eye Window: ________XXXXXX__________________________
Uplink 28:
Optimal Phase: 31
Window Length: 35
Eye Window: _________XXXXX__________________________
Uplink 29:
Optimal Phase: 33
Window Length: 35
Eye Window: ___________XXXXX________________________
Uplink 30:
Optimal Phase: 37
Window Length: 34
Eye Window: _______________XXXXXX___________________
Uplink 31:
Optimal Phase: 36
Window Length: 35
Eye Window: ______________XXXXX_____________________
]
14:54:45:setup_element:INFO: Beginning SMX ASICs map scan
14:54:45:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
14:54:45:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
14:54:45:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
14:54:45:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
14:54:45:uplink:INFO: Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
14:54:45:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 23
14:54:45:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 22
14:54:45:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 30
14:54:45:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 31
14:54:45:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 21
14:54:45:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 20
14:54:45:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28
14:54:45:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 29
14:54:45:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 19
14:54:45:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 18
14:54:46:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26
14:54:46:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 27
14:54:46:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 17
14:54:46:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 16
14:54:46:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 24
14:54:46:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 25
14:54:47:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 23), (1, 22)
ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
ASIC address 0x2: (ASIC uplink, uplink): (0, 21), (1, 20)
ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
ASIC address 0x4: (ASIC uplink, uplink): (0, 19), (1, 18)
ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
ASIC address 0x6: (ASIC uplink, uplink): (0, 17), (1, 16)
ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
Clock Phase Characteristic:
Optimal Phase: 36
Window Length: 69
Eye Windows:
Uplink 16: X_______________________________________________________________________XXXXXXXX
Uplink 17: X_______________________________________________________________________XXXXXXXX
Uplink 18: _______________________________________________________________________XXXXXXXX_
Uplink 19: _______________________________________________________________________XXXXXXXX_
Uplink 20: _______________________________________________________________________XXXXXXXX_
Uplink 21: _______________________________________________________________________XXXXXXXX_
Uplink 22: _______________________________________________________________________XXXXXXXX_
Uplink 23: _______________________________________________________________________XXXXXXXX_
Uplink 24: _______________________________________________________________________XXXXXXX__
Uplink 25: _______________________________________________________________________XXXXXXX__
Uplink 26: _______________________________________________________________________XXXXXXXX_
Uplink 27: _______________________________________________________________________XXXXXXXX_
Uplink 28: _______________________________________________________________________XXXXXXXX_
Uplink 29: _______________________________________________________________________XXXXXXXX_
Uplink 30: XX________________________________________________________________________XXXXXX
Uplink 31: XX________________________________________________________________________XXXXXX
Data phase characteristics:
Uplink 16:
Optimal Phase: 19
Window Length: 35
Eye Window: XX___________________________________XXX
Uplink 17:
Optimal Phase: 14
Window Length: 36
Eye Window: _________________________________XXXX___
Uplink 18:
Optimal Phase: 16
Window Length: 35
Eye Window: __________________________________XXXXX_
Uplink 19:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 20:
Optimal Phase: 16
Window Length: 34
Eye Window: __________________________________XXXXXX
Uplink 21:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
Uplink 22:
Optimal Phase: 15
Window Length: 36
Eye Window: __________________________________XXXX__
Uplink 23:
Optimal Phase: 14
Window Length: 35
Eye Window: ________________________________XXXXX___
Uplink 24:
Optimal Phase: 25
Window Length: 35
Eye Window: ___XXXXX________________________________
Uplink 25:
Optimal Phase: 28
Window Length: 35
Eye Window: ______XXXXX_____________________________
Uplink 26:
Optimal Phase: 27
Window Length: 35
Eye Window: _____XXXXX______________________________
Uplink 27:
Optimal Phase: 30
Window Length: 34
Eye Window: ________XXXXXX__________________________
Uplink 28:
Optimal Phase: 31
Window Length: 35
Eye Window: _________XXXXX__________________________
Uplink 29:
Optimal Phase: 33
Window Length: 35
Eye Window: ___________XXXXX________________________
Uplink 30:
Optimal Phase: 37
Window Length: 34
Eye Window: _______________XXXXXX___________________
Uplink 31:
Optimal Phase: 36
Window Length: 35
Eye Window: ______________XXXXX_____________________
14:54:47:setup_element:INFO: Performing Elink synchronization
14:54:47:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
14:54:47:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
14:54:47:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
14:54:47:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
14:54:47:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2
14:54:47:uplink:INFO: Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
14:54:48:ST3_emu:INFO: Number of chips: 8
addr | upli | dwnli | grp | uplinks | uplinks_map
0 | [0] | 2 | 0 | [23] | [(0, 23), (1, 22)]
1 | [0] | 2 | 0 | [30] | [(0, 30), (1, 31)]
2 | [0] | 2 | 0 | [21] | [(0, 21), (1, 20)]
3 | [0] | 2 | 0 | [28] | [(0, 28), (1, 29)]
4 | [0] | 2 | 0 | [19] | [(0, 19), (1, 18)]
5 | [0] | 2 | 0 | [26] | [(0, 26), (1, 27)]
6 | [0] | 2 | 0 | [17] | [(0, 17), (1, 16)]
7 | [0] | 2 | 0 | [24] | [(0, 24), (1, 25)]
14:54:49:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
14:54:49:febtest:INFO: 23-0 | XA-000-08-002-001-006-147-14 | 25.1 | 1230.3
14:54:50:febtest:INFO: 30-1 | XA-000-08-002-001-006-143-09 | 60.0 | 1100.2
14:54:50:febtest:INFO: 21-2 | XA-000-08-002-001-006-140-09 | 37.7 | 1183.3
14:54:50:febtest:INFO: 28-3 | XA-000-08-002-001-006-153-14 | 37.7 | 1189.2
14:54:50:febtest:INFO: 19-4 | XA-000-08-002-001-006-169-07 | 28.2 | 1212.7
14:54:51:febtest:INFO: 26-5 | XA-000-08-002-001-006-163-07 | 47.3 | 1153.7
14:54:51:febtest:INFO: 17-6 | XA-000-08-002-001-006-177-00 | 37.7 | 1189.2
14:54:51:febtest:INFO: 24-7 | XA-000-08-002-001-006-173-07 | 25.1 | 1242.0
14:54:51:ST3_smx:INFO: Configuring SMX FAST
14:54:56:ST3_smx:INFO: chip: 23-0 34.556970 C 1200.969315 mV
14:54:56:ST3_smx:INFO: Electrons
14:54:56:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:55:02:ST3_smx:INFO: ----> Checking Analog response
14:55:02:ST3_smx:INFO: ----> Checking broken channels
14:55:03:ST3_smx:INFO: Total # broken ch: 0
14:55:03:ST3_smx:INFO: List FAST: []
14:55:03:ST3_smx:INFO: List SLOW: []
14:55:03:ST3_smx:INFO: Holes
14:55:03:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:55:08:ST3_smx:INFO: ----> Checking Analog response
14:55:08:ST3_smx:INFO: ----> Checking broken channels
14:55:08:ST3_smx:INFO: Total # broken ch: 0
14:55:08:ST3_smx:INFO: List FAST: []
14:55:08:ST3_smx:INFO: List SLOW: []
14:55:08:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
14:55:08:febtest:INFO: 23-0 | XA-000-08-002-001-006-147-14 | 34.6 | 1195.1
14:55:08:febtest:INFO: 30-1 | XA-000-08-002-001-006-143-09 | 60.0 | 1100.2
14:55:09:febtest:INFO: 21-2 | XA-000-08-002-001-006-140-09 | 37.7 | 1177.4
14:55:09:febtest:INFO: 28-3 | XA-000-08-002-001-006-153-14 | 37.7 | 1189.2
14:55:09:febtest:INFO: 19-4 | XA-000-08-002-001-006-169-07 | 28.2 | 1212.7
14:55:09:febtest:INFO: 26-5 | XA-000-08-002-001-006-163-07 | 47.3 | 1159.7
14:55:09:febtest:INFO: 17-6 | XA-000-08-002-001-006-177-00 | 37.7 | 1183.3
14:55:09:febtest:INFO: 24-7 | XA-000-08-002-001-006-173-07 | 25.1 | 1242.0
14:55:10:ST3_smx:INFO: Configuring SMX FAST
14:55:13:ST3_smx:INFO: chip: 21-2 34.556970 C 1195.082160 mV
14:55:13:ST3_smx:INFO: Electrons
14:55:13:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:55:16:ST3_smx:INFO: ----> Checking Analog response
14:55:16:ST3_smx:INFO: ----> Checking broken channels
14:55:17:ST3_smx:INFO: Total # broken ch: 0
14:55:17:ST3_smx:INFO: List FAST: []
14:55:17:ST3_smx:INFO: List SLOW: []
14:55:17:ST3_smx:INFO: Holes
14:55:17:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:55:19:ST3_smx:INFO: ----> Checking Analog response
14:55:19:ST3_smx:INFO: ----> Checking broken channels
14:55:19:ST3_smx:INFO: Total # broken ch: 0
14:55:19:ST3_smx:INFO: List FAST: []
14:55:19:ST3_smx:INFO: List SLOW: []
14:55:19:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
14:55:20:febtest:INFO: 23-0 | XA-000-08-002-001-006-147-14 | 34.6 | 1195.1
14:55:20:febtest:INFO: 30-1 | XA-000-08-002-001-006-143-09 | 60.0 | 1100.2
14:55:20:febtest:INFO: 21-2 | XA-000-08-002-001-006-140-09 | 37.7 | 1189.2
14:55:20:febtest:INFO: 28-3 | XA-000-08-002-001-006-153-14 | 37.7 | 1189.2
14:55:21:febtest:INFO: 19-4 | XA-000-08-002-001-006-169-07 | 28.2 | 1212.7
14:55:21:febtest:INFO: 26-5 | XA-000-08-002-001-006-163-07 | 47.3 | 1153.7
14:55:21:febtest:INFO: 17-6 | XA-000-08-002-001-006-177-00 | 37.7 | 1183.3
14:55:21:febtest:INFO: 24-7 | XA-000-08-002-001-006-173-07 | 25.1 | 1242.0
14:55:22:ST3_smx:INFO: Configuring SMX FAST
14:55:24:ST3_smx:INFO: chip: 19-4 28.225000 C 1218.600960 mV
14:55:24:ST3_smx:INFO: Electrons
14:55:24:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:55:26:ST3_smx:INFO: ----> Checking Analog response
14:55:26:ST3_smx:INFO: ----> Checking broken channels
14:55:26:ST3_smx:INFO: Total # broken ch: 0
14:55:26:ST3_smx:INFO: List FAST: []
14:55:26:ST3_smx:INFO: List SLOW: []
14:55:26:ST3_smx:INFO: Holes
14:55:26:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:55:28:ST3_smx:INFO: ----> Checking Analog response
14:55:28:ST3_smx:INFO: ----> Checking broken channels
14:55:28:ST3_smx:INFO: Total # broken ch: 0
14:55:28:ST3_smx:INFO: List FAST: []
14:55:28:ST3_smx:INFO: List SLOW: []
14:55:28:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
14:55:29:febtest:INFO: 23-0 | XA-000-08-002-001-006-147-14 | 34.6 | 1195.1
14:55:29:febtest:INFO: 30-1 | XA-000-08-002-001-006-143-09 | 60.0 | 1100.2
14:55:29:febtest:INFO: 21-2 | XA-000-08-002-001-006-140-09 | 37.7 | 1189.2
14:55:29:febtest:INFO: 28-3 | XA-000-08-002-001-006-153-14 | 37.7 | 1189.2
14:55:30:febtest:INFO: 19-4 | XA-000-08-002-001-006-169-07 | 28.2 | 1212.7
14:55:30:febtest:INFO: 26-5 | XA-000-08-002-001-006-163-07 | 47.3 | 1159.7
14:55:30:febtest:INFO: 17-6 | XA-000-08-002-001-006-177-00 | 37.7 | 1183.3
14:55:30:febtest:INFO: 24-7 | XA-000-08-002-001-006-173-07 | 25.1 | 1242.0
14:55:31:ST3_smx:INFO: Configuring SMX FAST
14:55:33:ST3_smx:INFO: chip: 17-6 37.726682 C 1195.082160 mV
14:55:33:ST3_smx:INFO: Electrons
14:55:33:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:55:35:ST3_smx:INFO: ----> Checking Analog response
14:55:35:ST3_smx:INFO: ----> Checking broken channels
14:55:35:ST3_smx:INFO: Total # broken ch: 0
14:55:35:ST3_smx:INFO: List FAST: []
14:55:35:ST3_smx:INFO: List SLOW: []
14:55:35:ST3_smx:INFO: Holes
14:55:35:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:55:37:ST3_smx:INFO: ----> Checking Analog response
14:55:37:ST3_smx:INFO: ----> Checking broken channels
14:55:37:ST3_smx:INFO: Total # broken ch: 0
14:55:37:ST3_smx:INFO: List FAST: []
14:55:37:ST3_smx:INFO: List SLOW: []
14:55:37:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
14:55:38:febtest:INFO: 23-0 | XA-000-08-002-001-006-147-14 | 34.6 | 1195.1
14:55:38:febtest:INFO: 30-1 | XA-000-08-002-001-006-143-09 | 63.2 | 1100.2
14:55:38:febtest:INFO: 21-2 | XA-000-08-002-001-006-140-09 | 34.6 | 1189.2
14:55:38:febtest:INFO: 28-3 | XA-000-08-002-001-006-153-14 | 37.7 | 1189.2
14:55:39:febtest:INFO: 19-4 | XA-000-08-002-001-006-169-07 | 28.2 | 1212.7
14:55:39:febtest:INFO: 26-5 | XA-000-08-002-001-006-163-07 | 47.3 | 1159.7
14:55:39:febtest:INFO: 17-6 | XA-000-08-002-001-006-177-00 | 37.7 | 1189.2
14:55:39:febtest:INFO: 24-7 | XA-000-08-002-001-006-173-07 | 25.1 | 1242.0
############################################################
# S U M M A R Y #
############################################################
{'TEST_NAME': 'FEB-ASIC', 'TEST_DATE': '2024_02_12-14_54_34', 'OPERATOR': 'Alois Alzheimer', 'PROJECT': 'Production', 'SITE': 'GSI', 'SETUP': 'GSI_TEST_SETUP_1', 'ASIC_ID': 'XA-000-08-002-001-006-173-07', 'FUSED_ID': 6359364699117611735, 'HW_ADDR': 7, 'UPLINK': 24, 'VERS_NO': '', 'CABLE_SET_ID': '', 'IC_TEMP': '0', 'VDDM': '0', 'AUX': '0', 'CSABIAS': '0', 'VDDM_INT': '0', 'ADC_Chi2': 0.0, 'ADC_NDF': 0, 'ADC_P0': 0.0, 'ADC_P1': 0.006824, 'ADC_P2': -2.485e-06, 'ADC_P0err': 0.001, 'ADC_P1err': 0.001, 'ADC_P2err': 1e-05, 'ADC_VREF_P': 58, 'ADC_VREF_N': 30, 'ADC_VREF_T': 128, 'ADC_VREF_TR': 122, 'THR2_GLB': 30, 'LOOP__PLS': 100, 'CALIB_PLS': 250, 'SnsLoop': 5, 'IFED': 31, 'CSA_BIAS': 15, 'CSA_Chi2': 0.0, 'CSA_NDF': 0, 'CSA_P0': 0.0, 'CSA_P1': 0.0, 'CSA_P2': 0.0, 'CSA_P0err': 0.0, 'CSA_P1err': 0.0, 'CSA_P2err': 0.0, 'CONF_FAIL_REG': 0, 'N_BROKEN_DISC': 128, 'N_BROKEN_FAST': '', 'N_BROKEN_SLOW': '', 'P_BROKEN_DISC': 128, 'P_BROKEN_FAST': '', 'P_BROKEN_SLOW': '', 'ASIC_QA_category': '', 'N_BROKEN_CABLE': 0, 'LIST_OF_BROKEN_CABLES': 0, 'FEB_SN': '2013', 'FEB_TYPE': 8.2, 'FEB_UPLINKS': 2, 'FEB_A': 1, 'FEB_B': 0, 'ADDR_0': '', 'ADDR_1': '', 'ADDR_2': '', 'ADDR_3': '', 'ADDR_4': '', 'ADDR_5': '', 'ADDR_6': '', 'ADDR_7': '', 'SENSOR_ID': '', 'MODULE_NAME': '', 'MODULE_LADDER': '', 'MODULE_MODULE': '', 'MODULE_SIZE': '', 'MODULE_GRADE': '', 'MODULE_TYPE': '', 'VI_bInit': ['2.451', '0.0003', '1.850', '0.0001', '2.450', '1.9600', '1.850', '2.6790'], 'VI_aInit': ['0', '0', '0', '0', '0', '0'], 'VI_atEnd': ['0', '0', '0', '0', '0', '0'], 'AMP_CAL': 150}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-ASIC
TEST_DATE : 2024_02_12-14_54_34
OPERATOR : Alois Alzheimer
SITE : GSI
SETUP : GSI_TEST_SETUP_1
Set-ID :
---------------------------------------
MODULE_NAME :
FEB_SN : 2013
FEB_TYPE : 8.2
FEB_UPLINKS : 2
FEB_A : 1
FEB_B : 0
---------------------------------------
MODULE_NAME
---------------------------------------
VI_before_Init : ['2.451', '0.0003', '1.850', '0.0001', '2.450', '1.9600', '1.850', '2.6790']
VI_after__Init : ['2.450', '0.0003', '1.850', '0.0000', '2.450', '1.9370', '1.850', '0.3495']
VI_at__the_End : ['2.450', '0.0002', '1.850', '0.0000', '2.450', '1.9370', '1.850', '0.3495']
14:55:41:ST3_Shared:INFO: Listo of operators:Irakli K.;
14:56:13:ST3_Shared:INFO: /home/cbm/public_html/Production_LogDir//FEB/FEB_2013/TestDate_2024_02_12-14_54_34/