15:20:22:ST3_hmp4040:INFO:	ROHDE&SCHWARZ,HMP4040,123796,HW50020003/SW2.71
15:20:23:febtest:INFO:	FEB type: 8.2
15:20:23:febtest:INFO:	FEB SN: 2013
15:20:23:febtest:INFO:	FEB 8-2 selected
15:20:23:smx_tester:INFO:	Setting Elink clock mode to 160 MHz
15:20:31:ST3_Shared:INFO:	Listo of operators:Irakli K.; 
15:20:32:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
15:20:32:ST3_Shared:INFO:	--------------------------FEB-ASIC--------------------------
15:20:32:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
15:20:32:febtest:INFO:	Testing FEB with SN 2013
15:20:35:smx_tester:INFO:	Scanning setup
15:20:35:elinks:INFO:	Disabling clock on downlink 0
15:20:35:elinks:INFO:	Disabling clock on downlink 1
15:20:35:elinks:INFO:	Disabling clock on downlink 2
15:20:35:elinks:INFO:	Disabling clock on downlink 3
15:20:35:elinks:INFO:	Disabling clock on downlink 4
15:20:35:setup_element:INFO:	Checking SOS, encoding_mode: SOS
15:20:35:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
15:20:35:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
15:20:35:elinks:INFO:	Disabling clock on downlink 0
15:20:35:elinks:INFO:	Disabling clock on downlink 1
15:20:35:elinks:INFO:	Disabling clock on downlink 2
15:20:35:elinks:INFO:	Disabling clock on downlink 3
15:20:35:elinks:INFO:	Disabling clock on downlink 4
15:20:35:setup_element:INFO:	Checking SOS, encoding_mode: SOS
15:20:35:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
15:20:35:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
15:20:35:elinks:INFO:	Disabling clock on downlink 0
15:20:35:elinks:INFO:	Disabling clock on downlink 1
15:20:35:elinks:INFO:	Disabling clock on downlink 2
15:20:35:elinks:INFO:	Disabling clock on downlink 3
15:20:35:elinks:INFO:	Disabling clock on downlink 4
15:20:35:setup_element:INFO:	Checking SOS, encoding_mode: SOS
15:20:35:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
15:20:35:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 16
15:20:35:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 17
15:20:35:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 18
15:20:35:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 19
15:20:35:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 20
15:20:35:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 21
15:20:35:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 22
15:20:35:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 23
15:20:35:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 24
15:20:35:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 25
15:20:35:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 26
15:20:35:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 27
15:20:35:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 28
15:20:35:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 29
15:20:35:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 30
15:20:35:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 31
15:20:35:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
15:20:35:elinks:INFO:	Disabling clock on downlink 0
15:20:35:elinks:INFO:	Disabling clock on downlink 1
15:20:35:elinks:INFO:	Disabling clock on downlink 2
15:20:35:elinks:INFO:	Disabling clock on downlink 3
15:20:35:elinks:INFO:	Disabling clock on downlink 4
15:20:35:setup_element:INFO:	Checking SOS, encoding_mode: SOS
15:20:35:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
15:20:35:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
15:20:35:elinks:INFO:	Disabling clock on downlink 0
15:20:35:elinks:INFO:	Disabling clock on downlink 1
15:20:35:elinks:INFO:	Disabling clock on downlink 2
15:20:35:elinks:INFO:	Disabling clock on downlink 3
15:20:35:elinks:INFO:	Disabling clock on downlink 4
15:20:35:setup_element:INFO:	Checking SOS, encoding_mode: SOS
15:20:35:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [4]
15:20:36:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
15:20:36:setup_element:INFO:	Scanning clock phase
15:20:36:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
15:20:36:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
15:20:36:setup_element:INFO:	Clock phase scan results for group 0, downlink 2
15:20:36:setup_element:INFO:	Eye window for uplink 16: X_______________________________________________________________________XXXXXXXX
Clock Delay: 36
15:20:36:setup_element:INFO:	Eye window for uplink 17: X_______________________________________________________________________XXXXXXXX
Clock Delay: 36
15:20:36:setup_element:INFO:	Eye window for uplink 18: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
15:20:36:setup_element:INFO:	Eye window for uplink 19: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
15:20:36:setup_element:INFO:	Eye window for uplink 20: _______________________________________________________________________XXXXXXXXX
Clock Delay: 35
15:20:36:setup_element:INFO:	Eye window for uplink 21: _______________________________________________________________________XXXXXXXXX
Clock Delay: 35
15:20:36:setup_element:INFO:	Eye window for uplink 22: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
15:20:36:setup_element:INFO:	Eye window for uplink 23: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
15:20:36:setup_element:INFO:	Eye window for uplink 24: ________________________________________________________________________XXXXXX__
Clock Delay: 34
15:20:36:setup_element:INFO:	Eye window for uplink 25: ________________________________________________________________________XXXXXX__
Clock Delay: 34
15:20:36:setup_element:INFO:	Eye window for uplink 26: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
15:20:36:setup_element:INFO:	Eye window for uplink 27: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
15:20:36:setup_element:INFO:	Eye window for uplink 28: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
15:20:36:setup_element:INFO:	Eye window for uplink 29: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
15:20:36:setup_element:INFO:	Eye window for uplink 30: X_________________________________________________________________________XXXXXX
Clock Delay: 37
15:20:36:setup_element:INFO:	Eye window for uplink 31: X_________________________________________________________________________XXXXXX
Clock Delay: 37
15:20:36:setup_element:INFO:	Setting the clock phase to 35 for group 0, downlink 2
15:20:36:setup_element:INFO:	Scanning data phases
15:20:36:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
15:20:36:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
15:20:42:setup_element:INFO:	Data phase scan results for group 0, downlink 2
15:20:42:setup_element:INFO:	Eye window for uplink 16: XXX___________________________________XX
Data delay found: 20
15:20:42:setup_element:INFO:	Eye window for uplink 17: __________________________________XXXX__
Data delay found: 15
15:20:42:setup_element:INFO:	Eye window for uplink 18: X_________________________________XXXXX_
Data delay found: 17
15:20:42:setup_element:INFO:	Eye window for uplink 19: ________________________________XXXXX___
Data delay found: 14
15:20:42:setup_element:INFO:	Eye window for uplink 20: X__________________________________XXXXX
Data delay found: 17
15:20:42:setup_element:INFO:	Eye window for uplink 21: __________________________________XXXXX_
Data delay found: 16
15:20:42:setup_element:INFO:	Eye window for uplink 22: X_________________________________XXXXX_
Data delay found: 17
15:20:42:setup_element:INFO:	Eye window for uplink 23: _________________________________XXXX___
Data delay found: 14
15:20:42:setup_element:INFO:	Eye window for uplink 24: ____XXXXX_______________________________
Data delay found: 26
15:20:42:setup_element:INFO:	Eye window for uplink 25: _______XXXXX____________________________
Data delay found: 29
15:20:42:setup_element:INFO:	Eye window for uplink 26: ______XXXXX_____________________________
Data delay found: 28
15:20:42:setup_element:INFO:	Eye window for uplink 27: _________XXXXXX_________________________
Data delay found: 31
15:20:42:setup_element:INFO:	Eye window for uplink 28: ___________XXXXX________________________
Data delay found: 33
15:20:42:setup_element:INFO:	Eye window for uplink 29: ____________XXXXXX______________________
Data delay found: 34
15:20:42:setup_element:INFO:	Eye window for uplink 30: _________________XXXXXX_________________
Data delay found: 39
15:20:42:setup_element:INFO:	Eye window for uplink 31: _______________XXXXXXX__________________
Data delay found: 38
15:20:42:setup_element:INFO:	Setting the data phase to 20 for uplink 16
15:20:42:setup_element:INFO:	Setting the data phase to 15 for uplink 17
15:20:42:setup_element:INFO:	Setting the data phase to 17 for uplink 18
15:20:42:setup_element:INFO:	Setting the data phase to 14 for uplink 19
15:20:42:setup_element:INFO:	Setting the data phase to 17 for uplink 20
15:20:42:setup_element:INFO:	Setting the data phase to 16 for uplink 21
15:20:42:setup_element:INFO:	Setting the data phase to 17 for uplink 22
15:20:42:setup_element:INFO:	Setting the data phase to 14 for uplink 23
15:20:42:setup_element:INFO:	Setting the data phase to 26 for uplink 24
15:20:42:setup_element:INFO:	Setting the data phase to 29 for uplink 25
15:20:42:setup_element:INFO:	Setting the data phase to 28 for uplink 26
15:20:42:setup_element:INFO:	Setting the data phase to 31 for uplink 27
15:20:42:setup_element:INFO:	Setting the data phase to 33 for uplink 28
15:20:42:setup_element:INFO:	Setting the data phase to 34 for uplink 29
15:20:42:setup_element:INFO:	Setting the data phase to 39 for uplink 30
15:20:42:setup_element:INFO:	Setting the data phase to 38 for uplink 31
15:20:42:ST3_emu:ERROR:	[
Setup Element:
  Group: 0
  Downlink: 2
  Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
  ASICs Map: None
  Clock Phase Characteristic:
    Optimal Phase: 35
    Window Length: 70
    Eye Windows:
      Uplink 16: X_______________________________________________________________________XXXXXXXX
      Uplink 17: X_______________________________________________________________________XXXXXXXX
      Uplink 18: _______________________________________________________________________XXXXXXXX_
      Uplink 19: _______________________________________________________________________XXXXXXXX_
      Uplink 20: _______________________________________________________________________XXXXXXXXX
      Uplink 21: _______________________________________________________________________XXXXXXXXX
      Uplink 22: _______________________________________________________________________XXXXXXXX_
      Uplink 23: _______________________________________________________________________XXXXXXXX_
      Uplink 24: ________________________________________________________________________XXXXXX__
      Uplink 25: ________________________________________________________________________XXXXXX__
      Uplink 26: _______________________________________________________________________XXXXXXXX_
      Uplink 27: _______________________________________________________________________XXXXXXXX_
      Uplink 28: _______________________________________________________________________XXXXXXXX_
      Uplink 29: _______________________________________________________________________XXXXXXXX_
      Uplink 30: X_________________________________________________________________________XXXXXX
      Uplink 31: X_________________________________________________________________________XXXXXX
  Data phase characteristics:
    Uplink 16:
      Optimal Phase: 20
      Window Length: 35
      Eye Window: XXX___________________________________XX
    Uplink 17:
      Optimal Phase: 15
      Window Length: 36
      Eye Window: __________________________________XXXX__
    Uplink 18:
      Optimal Phase: 17
      Window Length: 33
      Eye Window: X_________________________________XXXXX_
    Uplink 19:
      Optimal Phase: 14
      Window Length: 35
      Eye Window: ________________________________XXXXX___
    Uplink 20:
      Optimal Phase: 17
      Window Length: 34
      Eye Window: X__________________________________XXXXX
    Uplink 21:
      Optimal Phase: 16
      Window Length: 35
      Eye Window: __________________________________XXXXX_
    Uplink 22:
      Optimal Phase: 17
      Window Length: 33
      Eye Window: X_________________________________XXXXX_
    Uplink 23:
      Optimal Phase: 14
      Window Length: 36
      Eye Window: _________________________________XXXX___
    Uplink 24:
      Optimal Phase: 26
      Window Length: 35
      Eye Window: ____XXXXX_______________________________
    Uplink 25:
      Optimal Phase: 29
      Window Length: 35
      Eye Window: _______XXXXX____________________________
    Uplink 26:
      Optimal Phase: 28
      Window Length: 35
      Eye Window: ______XXXXX_____________________________
    Uplink 27:
      Optimal Phase: 31
      Window Length: 34
      Eye Window: _________XXXXXX_________________________
    Uplink 28:
      Optimal Phase: 33
      Window Length: 35
      Eye Window: ___________XXXXX________________________
    Uplink 29:
      Optimal Phase: 34
      Window Length: 34
      Eye Window: ____________XXXXXX______________________
    Uplink 30:
      Optimal Phase: 39
      Window Length: 34
      Eye Window: _________________XXXXXX_________________
    Uplink 31:
      Optimal Phase: 38
      Window Length: 33
      Eye Window: _______________XXXXXXX__________________
]
15:20:42:setup_element:INFO:	Beginning SMX ASICs map scan
15:20:42:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
15:20:42:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
15:20:42:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
15:20:42:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
15:20:42:uplink:INFO:	Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
15:20:42:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 0, uplink 23
15:20:42:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 1, uplink 22
15:20:42:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 0, uplink 30
15:20:42:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 1, uplink 31
15:20:42:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 0, uplink 21
15:20:42:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 1, uplink 20
15:20:43:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 0, uplink 28
15:20:43:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 1, uplink 29
15:20:43:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 0, uplink 19
15:20:43:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 1, uplink 18
15:20:43:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 0, uplink 26
15:20:43:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 1, uplink 27
15:20:43:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 0, uplink 17
15:20:43:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 1, uplink 16
15:20:43:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 0, uplink 24
15:20:43:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 1, uplink 25
15:20:45:ST3_emu:ERROR:	
Setup Element:
  Group: 0
  Downlink: 2
  Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
  ASICs Map:
    ASIC address 0x0: (ASIC uplink, uplink): (0, 23), (1, 22)
    ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
    ASIC address 0x2: (ASIC uplink, uplink): (0, 21), (1, 20)
    ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
    ASIC address 0x4: (ASIC uplink, uplink): (0, 19), (1, 18)
    ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
    ASIC address 0x6: (ASIC uplink, uplink): (0, 17), (1, 16)
    ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
  Clock Phase Characteristic:
    Optimal Phase: 35
    Window Length: 70
    Eye Windows:
      Uplink 16: X_______________________________________________________________________XXXXXXXX
      Uplink 17: X_______________________________________________________________________XXXXXXXX
      Uplink 18: _______________________________________________________________________XXXXXXXX_
      Uplink 19: _______________________________________________________________________XXXXXXXX_
      Uplink 20: _______________________________________________________________________XXXXXXXXX
      Uplink 21: _______________________________________________________________________XXXXXXXXX
      Uplink 22: _______________________________________________________________________XXXXXXXX_
      Uplink 23: _______________________________________________________________________XXXXXXXX_
      Uplink 24: ________________________________________________________________________XXXXXX__
      Uplink 25: ________________________________________________________________________XXXXXX__
      Uplink 26: _______________________________________________________________________XXXXXXXX_
      Uplink 27: _______________________________________________________________________XXXXXXXX_
      Uplink 28: _______________________________________________________________________XXXXXXXX_
      Uplink 29: _______________________________________________________________________XXXXXXXX_
      Uplink 30: X_________________________________________________________________________XXXXXX
      Uplink 31: X_________________________________________________________________________XXXXXX
  Data phase characteristics:
    Uplink 16:
      Optimal Phase: 20
      Window Length: 35
      Eye Window: XXX___________________________________XX
    Uplink 17:
      Optimal Phase: 15
      Window Length: 36
      Eye Window: __________________________________XXXX__
    Uplink 18:
      Optimal Phase: 17
      Window Length: 33
      Eye Window: X_________________________________XXXXX_
    Uplink 19:
      Optimal Phase: 14
      Window Length: 35
      Eye Window: ________________________________XXXXX___
    Uplink 20:
      Optimal Phase: 17
      Window Length: 34
      Eye Window: X__________________________________XXXXX
    Uplink 21:
      Optimal Phase: 16
      Window Length: 35
      Eye Window: __________________________________XXXXX_
    Uplink 22:
      Optimal Phase: 17
      Window Length: 33
      Eye Window: X_________________________________XXXXX_
    Uplink 23:
      Optimal Phase: 14
      Window Length: 36
      Eye Window: _________________________________XXXX___
    Uplink 24:
      Optimal Phase: 26
      Window Length: 35
      Eye Window: ____XXXXX_______________________________
    Uplink 25:
      Optimal Phase: 29
      Window Length: 35
      Eye Window: _______XXXXX____________________________
    Uplink 26:
      Optimal Phase: 28
      Window Length: 35
      Eye Window: ______XXXXX_____________________________
    Uplink 27:
      Optimal Phase: 31
      Window Length: 34
      Eye Window: _________XXXXXX_________________________
    Uplink 28:
      Optimal Phase: 33
      Window Length: 35
      Eye Window: ___________XXXXX________________________
    Uplink 29:
      Optimal Phase: 34
      Window Length: 34
      Eye Window: ____________XXXXXX______________________
    Uplink 30:
      Optimal Phase: 39
      Window Length: 34
      Eye Window: _________________XXXXXX_________________
    Uplink 31:
      Optimal Phase: 38
      Window Length: 33
      Eye Window: _______________XXXXXXX__________________

15:20:45:setup_element:INFO:	Performing Elink synchronization
15:20:45:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
15:20:45:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
15:20:45:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
15:20:45:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
15:20:45:setup_element:INFO:	Writing SMX Elink masks for group 0, downlink 2
15:20:45:uplink:INFO:	Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
15:20:45:ST3_emu:INFO:	Number of chips: 8
addr  |  upli  |  dwnli  |  grp |  uplinks | uplinks_map
   0  |   [0]   |  2  |  0  |     [23]     |  [(0, 23), (1, 22)]
   1  |   [0]   |  2  |  0  |     [30]     |  [(0, 30), (1, 31)]
   2  |   [0]   |  2  |  0  |     [21]     |  [(0, 21), (1, 20)]
   3  |   [0]   |  2  |  0  |     [28]     |  [(0, 28), (1, 29)]
   4  |   [0]   |  2  |  0  |     [19]     |  [(0, 19), (1, 18)]
   5  |   [0]   |  2  |  0  |     [26]     |  [(0, 26), (1, 27)]
   6  |   [0]   |  2  |  0  |     [17]     |  [(0, 17), (1, 16)]
   7  |   [0]   |  2  |  0  |     [24]     |  [(0, 24), (1, 25)]
FEB type: B FEB_A: 0 FEB_B: 1
15:20:47:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
15:20:47:febtest:INFO:	23-00 | XA-000-08-002-001-006-147-14 |  31.4 | 1212.7
15:20:47:febtest:INFO:	30-01 | XA-000-08-002-001-006-143-09 |  63.2 | 1106.2
15:20:47:febtest:INFO:	21-02 | XA-000-08-002-001-006-140-09 |  40.9 | 1177.4
15:20:47:febtest:INFO:	28-03 | XA-000-08-002-001-006-153-14 |  37.7 | 1189.2
15:20:48:febtest:INFO:	19-04 | XA-000-08-002-001-006-169-07 |  34.6 | 1206.9
15:20:48:febtest:INFO:	26-05 | XA-000-08-002-001-006-163-07 |  50.4 | 1159.7
15:20:48:febtest:INFO:	17-06 | XA-000-08-002-001-006-177-00 |  40.9 | 1177.4
15:20:48:febtest:INFO:	24-07 | XA-000-08-002-001-006-173-07 |  25.1 | 1247.9
15:20:48:ST3_smx:INFO:	Configuring SMX FAST
15:20:50:ST3_smx:INFO:	chip: 23-0 	 37.726682 C 	 1200.969315 mV
15:20:50:ST3_smx:INFO:		Electrons
15:20:50:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
15:20:52:ST3_smx:INFO:	----> Checking Analog response
15:20:52:ST3_smx:INFO:	----> Checking broken channels
15:20:53:ST3_smx:INFO:	Total # broken ch: 0
15:20:53:ST3_smx:INFO:	List FAST: []
15:20:53:ST3_smx:INFO:	List SLOW: []
15:20:53:ST3_smx:INFO:		Holes
15:20:53:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
15:20:55:ST3_smx:INFO:	----> Checking Analog response
15:20:55:ST3_smx:INFO:	----> Checking broken channels
15:20:55:ST3_smx:INFO:	Total # broken ch: 0
15:20:55:ST3_smx:INFO:	List FAST: []
15:20:55:ST3_smx:INFO:	List SLOW: []
15:20:56:ST3_smx:INFO:	Configuring SMX FAST
15:20:58:ST3_smx:INFO:	chip: 30-1 	 56.797143 C 	 1129.995435 mV
15:20:58:ST3_smx:INFO:		Electrons
15:20:58:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
15:21:00:ST3_smx:INFO:	----> Checking Analog response
15:21:00:ST3_smx:INFO:	----> Checking broken channels
15:21:00:ST3_smx:INFO:	Total # broken ch: 0
15:21:00:ST3_smx:INFO:	List FAST: []
15:21:00:ST3_smx:INFO:	List SLOW: []
15:21:00:ST3_smx:INFO:		Holes
15:21:00:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
15:21:02:ST3_smx:INFO:	----> Checking Analog response
15:21:02:ST3_smx:INFO:	----> Checking broken channels
15:21:02:ST3_smx:INFO:	Total # broken ch: 0
15:21:02:ST3_smx:INFO:	List FAST: []
15:21:02:ST3_smx:INFO:	List SLOW: []
15:21:03:ST3_smx:INFO:	Configuring SMX FAST
15:21:05:ST3_smx:INFO:	chip: 21-2 	 37.726682 C 	 1195.082160 mV
15:21:05:ST3_smx:INFO:		Electrons
15:21:05:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
15:21:07:ST3_smx:INFO:	----> Checking Analog response
15:21:07:ST3_smx:INFO:	----> Checking broken channels
15:21:07:ST3_smx:INFO:	Total # broken ch: 0
15:21:07:ST3_smx:INFO:	List FAST: []
15:21:07:ST3_smx:INFO:	List SLOW: []
15:21:07:ST3_smx:INFO:		Holes
15:21:07:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
15:21:09:ST3_smx:INFO:	----> Checking Analog response
15:21:09:ST3_smx:INFO:	----> Checking broken channels
15:21:09:ST3_smx:INFO:	Total # broken ch: 0
15:21:09:ST3_smx:INFO:	List FAST: []
15:21:09:ST3_smx:INFO:	List SLOW: []
15:21:10:ST3_smx:INFO:	Configuring SMX FAST
15:21:12:ST3_smx:INFO:	chip: 28-3 	 34.556970 C 	 1200.969315 mV
15:21:12:ST3_smx:INFO:		Electrons
15:21:12:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
15:21:14:ST3_smx:INFO:	----> Checking Analog response
15:21:14:ST3_smx:INFO:	----> Checking broken channels
15:21:14:ST3_smx:INFO:	Total # broken ch: 0
15:21:14:ST3_smx:INFO:	List FAST: []
15:21:14:ST3_smx:INFO:	List SLOW: []
15:21:14:ST3_smx:INFO:		Holes
15:21:14:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
15:21:16:ST3_smx:INFO:	----> Checking Analog response
15:21:16:ST3_smx:INFO:	----> Checking broken channels
15:21:16:ST3_smx:INFO:	Total # broken ch: 0
15:21:16:ST3_smx:INFO:	List FAST: []
15:21:16:ST3_smx:INFO:	List SLOW: []
15:21:17:ST3_smx:INFO:	Configuring SMX FAST
15:21:19:ST3_smx:INFO:	chip: 19-4 	 31.389742 C 	 1212.728715 mV
15:21:19:ST3_smx:INFO:		Electrons
15:21:19:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
15:21:21:ST3_smx:INFO:	----> Checking Analog response
15:21:21:ST3_smx:INFO:	----> Checking broken channels
15:21:21:ST3_smx:INFO:	Total # broken ch: 0
15:21:21:ST3_smx:INFO:	List FAST: []
15:21:21:ST3_smx:INFO:	List SLOW: []
15:21:21:ST3_smx:INFO:		Holes
15:21:21:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
15:21:23:ST3_smx:INFO:	----> Checking Analog response
15:21:23:ST3_smx:INFO:	----> Checking broken channels
15:21:23:ST3_smx:INFO:	Total # broken ch: 0
15:21:23:ST3_smx:INFO:	List FAST: []
15:21:23:ST3_smx:INFO:	List SLOW: []
15:21:24:ST3_smx:INFO:	Configuring SMX FAST
15:21:26:ST3_smx:INFO:	chip: 26-5 	 47.250730 C 	 1171.483840 mV
15:21:26:ST3_smx:INFO:		Electrons
15:21:26:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
15:21:28:ST3_smx:INFO:	----> Checking Analog response
15:21:28:ST3_smx:INFO:	----> Checking broken channels
15:21:28:ST3_smx:INFO:	Total # broken ch: 0
15:21:28:ST3_smx:INFO:	List FAST: []
15:21:28:ST3_smx:INFO:	List SLOW: []
15:21:28:ST3_smx:INFO:		Holes
15:21:28:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
15:21:30:ST3_smx:INFO:	----> Checking Analog response
15:21:30:ST3_smx:INFO:	----> Checking broken channels
15:21:31:ST3_smx:INFO:	Total # broken ch: 0
15:21:31:ST3_smx:INFO:	List FAST: []
15:21:31:ST3_smx:INFO:	List SLOW: []
15:21:31:ST3_smx:INFO:	Configuring SMX FAST
15:21:33:ST3_smx:INFO:	chip: 17-6 	 40.898880 C 	 1189.190035 mV
15:21:33:ST3_smx:INFO:		Electrons
15:21:33:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
15:21:35:ST3_smx:INFO:	----> Checking Analog response
15:21:35:ST3_smx:INFO:	----> Checking broken channels
15:21:35:ST3_smx:INFO:	Total # broken ch: 0
15:21:35:ST3_smx:INFO:	List FAST: []
15:21:35:ST3_smx:INFO:	List SLOW: []
15:21:35:ST3_smx:INFO:		Holes
15:21:35:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
15:21:37:ST3_smx:INFO:	----> Checking Analog response
15:21:37:ST3_smx:INFO:	----> Checking broken channels
15:21:38:ST3_smx:INFO:	Total # broken ch: 0
15:21:38:ST3_smx:INFO:	List FAST: []
15:21:38:ST3_smx:INFO:	List SLOW: []
15:21:38:ST3_smx:INFO:	Configuring SMX FAST
15:21:40:ST3_smx:INFO:	chip: 24-7 	 37.726682 C 	 1206.851500 mV
15:21:40:ST3_smx:INFO:		Electrons
15:21:40:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
15:21:42:ST3_smx:INFO:	----> Checking Analog response
15:21:42:ST3_smx:INFO:	----> Checking broken channels
15:21:42:ST3_smx:INFO:	Total # broken ch: 0
15:21:42:ST3_smx:INFO:	List FAST: []
15:21:42:ST3_smx:INFO:	List SLOW: []
15:21:42:ST3_smx:INFO:		Holes
15:21:42:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
15:21:44:ST3_smx:INFO:	----> Checking Analog response
15:21:44:ST3_smx:INFO:	----> Checking broken channels
15:21:45:ST3_smx:INFO:	Total # broken ch: 0
15:21:45:ST3_smx:INFO:	List FAST: []
15:21:45:ST3_smx:INFO:	List SLOW: []
15:21:45:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
15:21:46:febtest:INFO:	23-00 | XA-000-08-002-001-006-147-14 |  40.9 | 1195.1
15:21:46:febtest:INFO:	30-01 | XA-000-08-002-001-006-143-09 |  56.8 | 1124.0
15:21:46:febtest:INFO:	21-02 | XA-000-08-002-001-006-140-09 |  40.9 | 1189.2
15:21:46:febtest:INFO:	28-03 | XA-000-08-002-001-006-153-14 |  37.7 | 1195.1
15:21:46:febtest:INFO:	19-04 | XA-000-08-002-001-006-169-07 |  34.6 | 1212.7
15:21:47:febtest:INFO:	26-05 | XA-000-08-002-001-006-163-07 |  47.3 | 1165.6
15:21:47:febtest:INFO:	17-06 | XA-000-08-002-001-006-177-00 |  40.9 | 1189.2
15:21:47:febtest:INFO:	24-07 | XA-000-08-002-001-006-173-07 |  40.9 | 1201.0
############################################################
#                   S U M M A R Y                          #
############################################################
{'TEST_NAME': 'FEB-ASIC', 'TEST_DATE': '24_02_26-15_20_32', 'OPERATOR': 'Irakli K.; ', 'PROJECT': 'GSI', 'SITE': 'GSI', 'SETUP': 'GSI_TEST_SETUP_1', 'ASIC_ID': 'XA-000-08-002-001-006-173-07', 'FUSED_ID': 6359364699117611735, 'HW_ADDR': 7, 'UPLINK': 24, 'VERS_NO': '', 'CABLE_SET_ID': '', 'IC_TEMP': '0', 'VDDM': '0', 'AUX': '0', 'CSABIAS': '0', 'VDDM_INT': '0', 'ADC_Chi2': 0.0, 'ADC_NDF': 0, 'ADC_P0': 0.0, 'ADC_P1': 0.006824, 'ADC_P2': -2.485e-06, 'ADC_P0err': 0.001, 'ADC_P1err': 0.001, 'ADC_P2err': 1e-05, 'ADC_VREF_P': 58, 'ADC_VREF_N': 30, 'ADC_VREF_T': 128, 'ADC_VREF_TR': 122, 'THR2_GLB': 30, 'LOOP__PLS': 100, 'CALIB_PLS': 250, 'SnsLoop': 5, 'IFED': 31, 'CSA_BIAS': 15, 'CSA_Chi2': 0.0, 'CSA_NDF': 0, 'CSA_P0': 0.0, 'CSA_P1': 0.0, 'CSA_P2': 0.0, 'CSA_P0err': 0.0, 'CSA_P1err': 0.0, 'CSA_P2err': 0.0, 'CONF_FAIL_REG': 0, 'N_BROKEN_DISC': 0, 'N_BROKEN_FAST': '[]', 'N_BROKEN_SLOW': '[]', 'P_BROKEN_DISC': 0, 'P_BROKEN_FAST': '[]', 'P_BROKEN_SLOW': '[]', 'ASIC_QA_category': '', 'N_BROKEN_CABLE': 0, 'LIST_OF_BROKEN_CABLES': 0, 'FEB_SN': '2013', 'FEB_TYPE': 8.2, 'FEB_UPLINKS': 2, 'FEB_A': 0, 'FEB_B': 1, 'ADDR_0': '', 'ADDR_1': '', 'ADDR_2': '', 'ADDR_3': '', 'ADDR_4': '', 'ADDR_5': '', 'ADDR_6': '', 'ADDR_7': '', 'SENSOR_ID': '', 'MODULE_NAME': '', 'MODULE_LADDER': '', 'MODULE_MODULE': '', 'MODULE_SIZE': '', 'MODULE_GRADE': '', 'MODULE_TYPE': '', 'VI_bInit': ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.9610', '1.850', '2.6690'], 'VI_aInit': ['0', '0', '0', '0', '0', '0'], 'VI_atEnd': ['0', '0', '0', '0', '0', '0'], 'AMP_CAL': 150, 'PlsLoop': 200, 'N_ANA_PRESENT': 'Analog response OK', 'N_DISC_FAIL_CH': 0, 'N_ANA_FAIL_CH': '0', 'P_ANA_PRESENT': 'Analog response OK', 'P_DISC_FAIL_CH': 0, 'P_ANA_FAIL_CH': '0'}
===============================

{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

############################################################
#                   S U M M A R Y                          #
############################################################
TEST_NAME : FEB-ASIC
TEST_DATE : 24_02_26-15_20_32
OPERATOR  : Irakli K.; 
SITE      : GSI
SETUP     : GSI_TEST_SETUP_1
Set-ID    : 
---------------------------------------
MODULE_NAME : 
FEB_SN : 2013
FEB_TYPE : 8.2
FEB_UPLINKS : 2
FEB_A : 0
FEB_B : 1
---------------------------------------
MODULE_NAME
---------------------------------------
VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.9610', '1.850', '2.6690']
VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.9830', '1.850', '0.3131']
VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.9810', '1.850', '0.3131']