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FEB_2013 23.05.24 15:01:24
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15:01:24:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
15:01:24:ST3_Shared:INFO: FEB-ASIC
15:01:24:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
15:01:24:febtest:INFO: Testing FEB with SN 2013
15:01:25:smx_tester:INFO: Scanning setup
15:01:25:elinks:INFO: Disabling clock on downlink 0
15:01:25:elinks:INFO: Disabling clock on downlink 1
15:01:25:elinks:INFO: Disabling clock on downlink 2
15:01:25:elinks:INFO: Disabling clock on downlink 3
15:01:25:elinks:INFO: Disabling clock on downlink 4
15:01:25:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:01:25:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
15:01:26:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:01:26:elinks:INFO: Disabling clock on downlink 0
15:01:26:elinks:INFO: Disabling clock on downlink 1
15:01:26:elinks:INFO: Disabling clock on downlink 2
15:01:26:elinks:INFO: Disabling clock on downlink 3
15:01:26:elinks:INFO: Disabling clock on downlink 4
15:01:26:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:01:26:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
15:01:26:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:01:26:elinks:INFO: Disabling clock on downlink 0
15:01:26:elinks:INFO: Disabling clock on downlink 1
15:01:26:elinks:INFO: Disabling clock on downlink 2
15:01:26:elinks:INFO: Disabling clock on downlink 3
15:01:26:elinks:INFO: Disabling clock on downlink 4
15:01:26:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:01:26:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:01:26:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 16
15:01:26:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 17
15:01:26:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 18
15:01:26:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 19
15:01:26:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 20
15:01:26:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 21
15:01:26:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 22
15:01:26:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 23
15:01:26:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24
15:01:26:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25
15:01:26:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26
15:01:26:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27
15:01:26:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28
15:01:26:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29
15:01:26:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30
15:01:26:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31
15:01:26:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:01:26:elinks:INFO: Disabling clock on downlink 0
15:01:26:elinks:INFO: Disabling clock on downlink 1
15:01:26:elinks:INFO: Disabling clock on downlink 2
15:01:26:elinks:INFO: Disabling clock on downlink 3
15:01:26:elinks:INFO: Disabling clock on downlink 4
15:01:26:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:01:26:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
15:01:26:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:01:26:elinks:INFO: Disabling clock on downlink 0
15:01:26:elinks:INFO: Disabling clock on downlink 1
15:01:26:elinks:INFO: Disabling clock on downlink 2
15:01:26:elinks:INFO: Disabling clock on downlink 3
15:01:26:elinks:INFO: Disabling clock on downlink 4
15:01:26:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:01:26:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
15:01:26:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:01:26:setup_element:INFO: Scanning clock phase
15:01:26:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:01:26:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
15:01:27:setup_element:INFO: Clock phase scan results for group 0, downlink 2
15:01:27:setup_element:INFO: Eye window for uplink 16: _____________________________________________________________________XXXXXXXXX__
Clock Delay: 33
15:01:27:setup_element:INFO: Eye window for uplink 17: _____________________________________________________________________XXXXXXXXX__
Clock Delay: 33
15:01:27:setup_element:INFO: Eye window for uplink 18: _____________________________________________________________________XXXXXXX____
Clock Delay: 32
15:01:27:setup_element:INFO: Eye window for uplink 19: _____________________________________________________________________XXXXXXX____
Clock Delay: 32
15:01:27:setup_element:INFO: Eye window for uplink 20: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
15:01:27:setup_element:INFO: Eye window for uplink 21: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
15:01:27:setup_element:INFO: Eye window for uplink 22: ____________________________________________________________________XXXXXXXXX___
Clock Delay: 32
15:01:27:setup_element:INFO: Eye window for uplink 23: ____________________________________________________________________XXXXXXXXX___
Clock Delay: 32
15:01:27:setup_element:INFO: Eye window for uplink 24: _____________________________________________________________________XXXXXXX____
Clock Delay: 32
15:01:27:setup_element:INFO: Eye window for uplink 25: _____________________________________________________________________XXXXXXX____
Clock Delay: 32
15:01:27:setup_element:INFO: Eye window for uplink 26: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
15:01:27:setup_element:INFO: Eye window for uplink 27: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
15:01:27:setup_element:INFO: Eye window for uplink 28: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
15:01:27:setup_element:INFO: Eye window for uplink 29: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
15:01:27:setup_element:INFO: Eye window for uplink 30: ________________________________________________________________________XXXXXXX_
Clock Delay: 35
15:01:27:setup_element:INFO: Eye window for uplink 31: ________________________________________________________________________XXXXXXX_
Clock Delay: 35
15:01:27:setup_element:INFO: Setting the clock phase to 33 for group 0, downlink 2
15:01:27:setup_element:INFO: Scanning data phases
15:01:27:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:01:27:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
15:01:32:setup_element:INFO: Data phase scan results for group 0, downlink 2
15:01:32:setup_element:INFO: Eye window for uplink 16: XX____________________________________XX
Data delay found: 19
15:01:32:setup_element:INFO: Eye window for uplink 17: ___________________________________XXXXX
Data delay found: 17
15:01:32:setup_element:INFO: Eye window for uplink 18: ___________________________________XXXXX
Data delay found: 17
15:01:32:setup_element:INFO: Eye window for uplink 19: _________________________________XXXX___
Data delay found: 14
15:01:32:setup_element:INFO: Eye window for uplink 20: X___________________________________XXXX
Data delay found: 18
15:01:32:setup_element:INFO: Eye window for uplink 21: __________________________________XXXXXX
Data delay found: 16
15:01:32:setup_element:INFO: Eye window for uplink 22: X__________________________________XXXXX
Data delay found: 17
15:01:32:setup_element:INFO: Eye window for uplink 23: XXXXX____________________________XXXXXXX
Data delay found: 18
15:01:32:setup_element:INFO: Eye window for uplink 24: ______XXXXX_____________________________
Data delay found: 28
15:01:32:setup_element:INFO: Eye window for uplink 25: ________XXXXX___________________________
Data delay found: 30
15:01:32:setup_element:INFO: Eye window for uplink 26: _______XXXXXX___________________________
Data delay found: 29
15:01:32:setup_element:INFO: Eye window for uplink 27: __________XXXXXX________________________
Data delay found: 32
15:01:32:setup_element:INFO: Eye window for uplink 28: ___________XXXXX________________________
Data delay found: 33
15:01:32:setup_element:INFO: Eye window for uplink 29: _____________XXXXXX_____________________
Data delay found: 35
15:01:32:setup_element:INFO: Eye window for uplink 30: ___________XXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Data delay found: 5
15:01:32:setup_element:INFO: Eye window for uplink 31: ___________XXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Data delay found: 5
15:01:32:setup_element:INFO: Setting the data phase to 19 for uplink 16
15:01:32:setup_element:INFO: Setting the data phase to 17 for uplink 17
15:01:32:setup_element:INFO: Setting the data phase to 17 for uplink 18
15:01:32:setup_element:INFO: Setting the data phase to 14 for uplink 19
15:01:32:setup_element:INFO: Setting the data phase to 18 for uplink 20
15:01:32:setup_element:INFO: Setting the data phase to 16 for uplink 21
15:01:32:setup_element:INFO: Setting the data phase to 17 for uplink 22
15:01:32:setup_element:INFO: Setting the data phase to 18 for uplink 23
15:01:32:setup_element:INFO: Setting the data phase to 28 for uplink 24
15:01:32:setup_element:INFO: Setting the data phase to 30 for uplink 25
15:01:32:setup_element:INFO: Setting the data phase to 29 for uplink 26
15:01:32:setup_element:INFO: Setting the data phase to 32 for uplink 27
15:01:32:setup_element:INFO: Setting the data phase to 33 for uplink 28
15:01:32:setup_element:INFO: Setting the data phase to 35 for uplink 29
15:01:32:setup_element:INFO: Setting the data phase to 5 for uplink 30
15:01:32:setup_element:INFO: Setting the data phase to 5 for uplink 31
15:01:32:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 33
Window Length: 69
Eye Windows:
Uplink 16: _____________________________________________________________________XXXXXXXXX__
Uplink 17: _____________________________________________________________________XXXXXXXXX__
Uplink 18: _____________________________________________________________________XXXXXXX____
Uplink 19: _____________________________________________________________________XXXXXXX____
Uplink 20: _____________________________________________________________________XXXXXXXX___
Uplink 21: _____________________________________________________________________XXXXXXXX___
Uplink 22: ____________________________________________________________________XXXXXXXXX___
Uplink 23: ____________________________________________________________________XXXXXXXXX___
Uplink 24: _____________________________________________________________________XXXXXXX____
Uplink 25: _____________________________________________________________________XXXXXXX____
Uplink 26: _____________________________________________________________________XXXXXXXX___
Uplink 27: _____________________________________________________________________XXXXXXXX___
Uplink 28: ____________________________________________________________________XXXXXXXX____
Uplink 29: ____________________________________________________________________XXXXXXXX____
Uplink 30: ________________________________________________________________________XXXXXXX_
Uplink 31: ________________________________________________________________________XXXXXXX_
Data phase characteristics:
Uplink 16:
Optimal Phase: 19
Window Length: 36
Eye Window: XX____________________________________XX
Uplink 17:
Optimal Phase: 17
Window Length: 35
Eye Window: ___________________________________XXXXX
Uplink 18:
Optimal Phase: 17
Window Length: 35
Eye Window: ___________________________________XXXXX
Uplink 19:
Optimal Phase: 14
Window Length: 36
Eye Window: _________________________________XXXX___
Uplink 20:
Optimal Phase: 18
Window Length: 35
Eye Window: X___________________________________XXXX
Uplink 21:
Optimal Phase: 16
Window Length: 34
Eye Window: __________________________________XXXXXX
Uplink 22:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXXX
Uplink 23:
Optimal Phase: 18
Window Length: 28
Eye Window: XXXXX____________________________XXXXXXX
Uplink 24:
Optimal Phase: 28
Window Length: 35
Eye Window: ______XXXXX_____________________________
Uplink 25:
Optimal Phase: 30
Window Length: 35
Eye Window: ________XXXXX___________________________
Uplink 26:
Optimal Phase: 29
Window Length: 34
Eye Window: _______XXXXXX___________________________
Uplink 27:
Optimal Phase: 32
Window Length: 34
Eye Window: __________XXXXXX________________________
Uplink 28:
Optimal Phase: 33
Window Length: 35
Eye Window: ___________XXXXX________________________
Uplink 29:
Optimal Phase: 35
Window Length: 34
Eye Window: _____________XXXXXX_____________________
Uplink 30:
Optimal Phase: 5
Window Length: 11
Eye Window: ___________XXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Uplink 31:
Optimal Phase: 5
Window Length: 11
Eye Window: ___________XXXXXXXXXXXXXXXXXXXXXXXXXXXXX
]
15:01:32:setup_element:INFO: Beginning SMX ASICs map scan
15:01:32:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:01:32:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
15:01:32:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
15:01:32:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
15:01:32:uplink:INFO: Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
15:01:32:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 23
15:01:32:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 22
15:01:33:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 30
15:01:33:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 31
15:01:33:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 21
15:01:33:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 20
15:01:33:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28
15:01:33:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 29
15:01:33:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 19
15:01:33:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 18
15:01:33:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26
15:01:33:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 27
15:01:34:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 17
15:01:34:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 16
15:01:34:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 24
15:01:34:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 25
15:01:35:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 23), (1, 22)
ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
ASIC address 0x2: (ASIC uplink, uplink): (0, 21), (1, 20)
ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
ASIC address 0x4: (ASIC uplink, uplink): (0, 19), (1, 18)
ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
ASIC address 0x6: (ASIC uplink, uplink): (0, 17), (1, 16)
ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
Clock Phase Characteristic:
Optimal Phase: 33
Window Length: 69
Eye Windows:
Uplink 16: _____________________________________________________________________XXXXXXXXX__
Uplink 17: _____________________________________________________________________XXXXXXXXX__
Uplink 18: _____________________________________________________________________XXXXXXX____
Uplink 19: _____________________________________________________________________XXXXXXX____
Uplink 20: _____________________________________________________________________XXXXXXXX___
Uplink 21: _____________________________________________________________________XXXXXXXX___
Uplink 22: ____________________________________________________________________XXXXXXXXX___
Uplink 23: ____________________________________________________________________XXXXXXXXX___
Uplink 24: _____________________________________________________________________XXXXXXX____
Uplink 25: _____________________________________________________________________XXXXXXX____
Uplink 26: _____________________________________________________________________XXXXXXXX___
Uplink 27: _____________________________________________________________________XXXXXXXX___
Uplink 28: ____________________________________________________________________XXXXXXXX____
Uplink 29: ____________________________________________________________________XXXXXXXX____
Uplink 30: ________________________________________________________________________XXXXXXX_
Uplink 31: ________________________________________________________________________XXXXXXX_
Data phase characteristics:
Uplink 16:
Optimal Phase: 19
Window Length: 36
Eye Window: XX____________________________________XX
Uplink 17:
Optimal Phase: 17
Window Length: 35
Eye Window: ___________________________________XXXXX
Uplink 18:
Optimal Phase: 17
Window Length: 35
Eye Window: ___________________________________XXXXX
Uplink 19:
Optimal Phase: 14
Window Length: 36
Eye Window: _________________________________XXXX___
Uplink 20:
Optimal Phase: 18
Window Length: 35
Eye Window: X___________________________________XXXX
Uplink 21:
Optimal Phase: 16
Window Length: 34
Eye Window: __________________________________XXXXXX
Uplink 22:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXXX
Uplink 23:
Optimal Phase: 18
Window Length: 28
Eye Window: XXXXX____________________________XXXXXXX
Uplink 24:
Optimal Phase: 28
Window Length: 35
Eye Window: ______XXXXX_____________________________
Uplink 25:
Optimal Phase: 30
Window Length: 35
Eye Window: ________XXXXX___________________________
Uplink 26:
Optimal Phase: 29
Window Length: 34
Eye Window: _______XXXXXX___________________________
Uplink 27:
Optimal Phase: 32
Window Length: 34
Eye Window: __________XXXXXX________________________
Uplink 28:
Optimal Phase: 33
Window Length: 35
Eye Window: ___________XXXXX________________________
Uplink 29:
Optimal Phase: 35
Window Length: 34
Eye Window: _____________XXXXXX_____________________
Uplink 30:
Optimal Phase: 5
Window Length: 11
Eye Window: ___________XXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Uplink 31:
Optimal Phase: 5
Window Length: 11
Eye Window: ___________XXXXXXXXXXXXXXXXXXXXXXXXXXXXX
15:01:35:setup_element:INFO: Performing Elink synchronization
15:01:35:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:01:35:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
15:01:35:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
15:01:35:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
15:01:35:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2
15:01:35:uplink:INFO: Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
15:01:35:ST3_emu:INFO: Number of chips: 8
addr | upli | dwnli | grp | uplinks | uplinks_map
0 | [0] | 2 | 0 | [23] | [(0, 23), (1, 22)]
1 | [0] | 2 | 0 | [30] | [(0, 30), (1, 31)]
2 | [0] | 2 | 0 | [21] | [(0, 21), (1, 20)]
3 | [0] | 2 | 0 | [28] | [(0, 28), (1, 29)]
4 | [0] | 2 | 0 | [19] | [(0, 19), (1, 18)]
5 | [0] | 2 | 0 | [26] | [(0, 26), (1, 27)]
6 | [0] | 2 | 0 | [17] | [(0, 17), (1, 16)]
7 | [0] | 2 | 0 | [24] | [(0, 24), (1, 25)]
15:01:36:febtest:INFO: Init all SMX (CSA): 30
15:01:51:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
15:01:51:febtest:INFO: 23-00 | XA-000-08-002-001-006-147-14 | 31.4 | 1165.6
15:01:51:febtest:INFO: 30-01 | XA-000-08-002-001-006-143-09 | 53.6 | 1088.3
15:01:52:febtest:INFO: 21-02 | XA-000-08-002-001-006-140-09 | 34.6 | 1159.7
15:01:52:febtest:INFO: 28-03 | XA-000-08-002-001-006-153-14 | 31.4 | 1159.7
15:01:52:febtest:INFO: 19-04 | XA-000-08-002-001-006-169-07 | 28.2 | 1183.3
15:01:52:febtest:INFO: 26-05 | XA-000-08-002-001-006-163-07 | 40.9 | 1135.9
15:01:53:febtest:INFO: 17-06 | XA-000-08-002-001-006-177-00 | 34.6 | 1165.6
15:01:53:febtest:INFO: 24-07 | XA-000-08-002-001-006-173-07 | 34.6 | 1165.6
15:01:54:febtest:INFO: Set all CSA to ZERO
FEB type: B FEB_A: 0 FEB_B: 1
15:01:56:ST3_smx:INFO: chip: 30-1 53.612520 C 1106.178435 mV
15:01:56:ST3_smx:INFO: Electrons
15:01:56:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
15:01:58:ST3_smx:INFO: ----> Checking Analog response
15:01:58:ST3_smx:INFO: ----> Checking broken channels
15:01:59:ST3_smx:INFO: Total # broken ch: 0
15:01:59:ST3_smx:INFO: List FAST: []
15:01:59:ST3_smx:INFO: List SLOW: []
15:01:59:ST3_smx:INFO: Holes
15:01:59:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
15:02:01:ST3_smx:INFO: ----> Checking Analog response
15:02:01:ST3_smx:INFO: ----> Checking broken channels
15:02:01:ST3_smx:INFO: Total # broken ch: 0
15:02:01:ST3_smx:INFO: List FAST: []
15:02:01:ST3_smx:INFO: List SLOW: []
15:02:03:ST3_smx:INFO: chip: 28-3 31.389742 C 1177.390875 mV
15:02:03:ST3_smx:INFO: Electrons
15:02:03:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
15:02:05:ST3_smx:INFO: ----> Checking Analog response
15:02:05:ST3_smx:INFO: ----> Checking broken channels
15:02:05:ST3_smx:INFO: Total # broken ch: 0
15:02:05:ST3_smx:INFO: List FAST: []
15:02:05:ST3_smx:INFO: List SLOW: []
15:02:05:ST3_smx:INFO: Holes
15:02:05:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
15:02:07:ST3_smx:INFO: ----> Checking Analog response
15:02:07:ST3_smx:INFO: ----> Checking broken channels
15:02:08:ST3_smx:INFO: Total # broken ch: 0
15:02:08:ST3_smx:INFO: List FAST: []
15:02:08:ST3_smx:INFO: List SLOW: []
15:02:09:ST3_smx:INFO: chip: 26-5 40.898880 C 1153.732915 mV
15:02:09:ST3_smx:INFO: Electrons
15:02:09:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
15:02:11:ST3_smx:INFO: ----> Checking Analog response
15:02:11:ST3_smx:INFO: ----> Checking broken channels
15:02:11:ST3_smx:INFO: Total # broken ch: 0
15:02:11:ST3_smx:INFO: List FAST: []
15:02:11:ST3_smx:INFO: List SLOW: []
15:02:11:ST3_smx:INFO: Holes
15:02:11:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
15:02:14:ST3_smx:INFO: ----> Checking Analog response
15:02:14:ST3_smx:INFO: ----> Checking broken channels
15:02:14:ST3_smx:INFO: Total # broken ch: 0
15:02:14:ST3_smx:INFO: List FAST: []
15:02:14:ST3_smx:INFO: List SLOW: []
15:02:15:ST3_smx:INFO: chip: 24-7 34.556970 C 1177.390875 mV
15:02:15:ST3_smx:INFO: Electrons
15:02:15:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
15:02:18:ST3_smx:INFO: ----> Checking Analog response
15:02:18:ST3_smx:INFO: ----> Checking broken channels
15:02:18:ST3_smx:INFO: Total # broken ch: 0
15:02:18:ST3_smx:INFO: List FAST: []
15:02:18:ST3_smx:INFO: List SLOW: []
15:02:18:ST3_smx:INFO: Holes
15:02:18:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
15:02:20:ST3_smx:INFO: ----> Checking Analog response
15:02:20:ST3_smx:INFO: ----> Checking broken channels
15:02:20:ST3_smx:INFO: Total # broken ch: 0
15:02:20:ST3_smx:INFO: List FAST: []
15:02:20:ST3_smx:INFO: List SLOW: []
15:02:20:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
15:02:21:febtest:INFO: 23-00 | XA-000-08-002-001-006-147-14 | 31.4 | 1201.0
15:02:21:febtest:INFO: 30-01 | XA-000-08-002-001-006-143-09 | 53.6 | 1124.0
15:02:21:febtest:INFO: 21-02 | XA-000-08-002-001-006-140-09 | 31.4 | 1195.1
15:02:21:febtest:INFO: 28-03 | XA-000-08-002-001-006-153-14 | 34.6 | 1195.1
15:02:22:febtest:INFO: 19-04 | XA-000-08-002-001-006-169-07 | 28.2 | 1218.6
15:02:22:febtest:INFO: 26-05 | XA-000-08-002-001-006-163-07 | 44.1 | 1171.5
15:02:22:febtest:INFO: 17-06 | XA-000-08-002-001-006-177-00 | 34.6 | 1195.1
15:02:22:febtest:INFO: 24-07 | XA-000-08-002-001-006-173-07 | 37.7 | 1201.0
############################################################
# S U M M A R Y #
############################################################
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-ASIC
TEST_DATE : 24_05_23-15_01_24
OPERATOR : Alois Alzheimer
SITE : GSI | SETUP : GSI_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 2013| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_B
------------------------------------------------------------
MODULE_NAME
------------------------------------------------------------
VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.5360', '1.852', '2.5400']
VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.9860', '1.850', '2.5360']
VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.9690', '1.850', '0.2305']