DTL-STS tests database

FEB_2014 28.11.23 11:09:15

link:
...SMX_0.root
link: XA-000-08-002-001-008-116-06
...SMX_2.root
link: XA-000-08-002-001-006-231-02
...SMX_4.root
link: XA-000-08-002-001-008-138-00
...SMX_6.root
link:
...SMX_1.root
link: XA-000-08-002-001-008-118-06
...SMX_3.root
link: XA-000-08-002-001-008-117-06
...SMX_5.root
link: XA-000-08-002-001-008-113-06
...SMX_7.root
TextEdit.txt
            11:09:07:febtest:INFO:	FEB 8-2 B @ GSI
11:09:15:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
11:09:15:ST3_Shared:INFO:	--------------------------FEB-ASIC--------------------------
11:09:15:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
11:09:15:febtest:INFO:	Tsting FEB with SN 2014
11:09:16:smx_tester:INFO:	Scanning setup
11:09:16:elinks:INFO:	Disabling clock on downlink 0
11:09:16:elinks:INFO:	Disabling clock on downlink 1
11:09:16:elinks:INFO:	Disabling clock on downlink 2
11:09:16:elinks:INFO:	Disabling clock on downlink 3
11:09:16:elinks:INFO:	Disabling clock on downlink 4
11:09:16:setup_element:INFO:	Checking SOS, encoding_mode: SOS
11:09:16:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
11:09:16:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
11:09:16:elinks:INFO:	Disabling clock on downlink 0
11:09:16:elinks:INFO:	Disabling clock on downlink 1
11:09:16:elinks:INFO:	Disabling clock on downlink 2
11:09:16:elinks:INFO:	Disabling clock on downlink 3
11:09:16:elinks:INFO:	Disabling clock on downlink 4
11:09:16:setup_element:INFO:	Checking SOS, encoding_mode: SOS
11:09:16:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
11:09:16:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
11:09:16:elinks:INFO:	Disabling clock on downlink 0
11:09:16:elinks:INFO:	Disabling clock on downlink 1
11:09:16:elinks:INFO:	Disabling clock on downlink 2
11:09:16:elinks:INFO:	Disabling clock on downlink 3
11:09:16:elinks:INFO:	Disabling clock on downlink 4
11:09:16:setup_element:INFO:	Checking SOS, encoding_mode: SOS
11:09:16:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
11:09:17:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 16
11:09:17:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 17
11:09:17:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 18
11:09:17:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 19
11:09:17:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 20
11:09:17:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 21
11:09:17:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 22
11:09:17:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 23
11:09:17:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 24
11:09:17:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 25
11:09:17:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 26
11:09:17:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 27
11:09:17:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 28
11:09:17:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 29
11:09:17:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 30
11:09:17:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 31
11:09:17:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
11:09:17:elinks:INFO:	Disabling clock on downlink 0
11:09:17:elinks:INFO:	Disabling clock on downlink 1
11:09:17:elinks:INFO:	Disabling clock on downlink 2
11:09:17:elinks:INFO:	Disabling clock on downlink 3
11:09:17:elinks:INFO:	Disabling clock on downlink 4
11:09:17:setup_element:INFO:	Checking SOS, encoding_mode: SOS
11:09:17:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
11:09:17:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
11:09:17:elinks:INFO:	Disabling clock on downlink 0
11:09:17:elinks:INFO:	Disabling clock on downlink 1
11:09:17:elinks:INFO:	Disabling clock on downlink 2
11:09:17:elinks:INFO:	Disabling clock on downlink 3
11:09:17:elinks:INFO:	Disabling clock on downlink 4
11:09:17:setup_element:INFO:	Checking SOS, encoding_mode: SOS
11:09:17:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [4]
11:09:17:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
11:09:17:setup_element:INFO:	Scanning clock phase
11:09:17:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
11:09:17:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
11:09:17:setup_element:INFO:	Clock phase scan results for group 0, downlink 2
11:09:17:setup_element:INFO:	Eye window for uplink 16: ________________________________________________________________________XXXXXXXX
Clock Delay: 35
11:09:17:setup_element:INFO:	Eye window for uplink 17: ________________________________________________________________________XXXXXXXX
Clock Delay: 35
11:09:17:setup_element:INFO:	Eye window for uplink 18: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
11:09:17:setup_element:INFO:	Eye window for uplink 19: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
11:09:17:setup_element:INFO:	Eye window for uplink 20: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
11:09:17:setup_element:INFO:	Eye window for uplink 21: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
11:09:17:setup_element:INFO:	Eye window for uplink 22: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
11:09:17:setup_element:INFO:	Eye window for uplink 23: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
11:09:17:setup_element:INFO:	Eye window for uplink 24: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
11:09:17:setup_element:INFO:	Eye window for uplink 25: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
11:09:17:setup_element:INFO:	Eye window for uplink 26: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
11:09:17:setup_element:INFO:	Eye window for uplink 27: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
11:09:17:setup_element:INFO:	Eye window for uplink 28: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
11:09:17:setup_element:INFO:	Eye window for uplink 29: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
11:09:17:setup_element:INFO:	Eye window for uplink 30: _________________________________________________________________________XXXXXXX
Clock Delay: 36
11:09:17:setup_element:INFO:	Eye window for uplink 31: _________________________________________________________________________XXXXXXX
Clock Delay: 36
11:09:17:setup_element:INFO:	Setting the clock phase to 34 for group 0, downlink 2
11:09:17:setup_element:INFO:	Scanning data phases
11:09:17:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
11:09:18:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
11:09:23:setup_element:INFO:	Data phase scan results for group 0, downlink 2
11:09:23:setup_element:INFO:	Eye window for uplink 16: XXX___________________________________XX
Data delay found: 20
11:09:23:setup_element:INFO:	Eye window for uplink 17: __________________________________XXXXX_
Data delay found: 16
11:09:23:setup_element:INFO:	Eye window for uplink 18: XXX__________________________________XXX
Data delay found: 19
11:09:23:setup_element:INFO:	Eye window for uplink 19: __________________________________XXXXX_
Data delay found: 16
11:09:23:setup_element:INFO:	Eye window for uplink 20: ___________________________________XXXX_
Data delay found: 16
11:09:23:setup_element:INFO:	Eye window for uplink 21: _________________________________XXXXXX_
Data delay found: 15
11:09:23:setup_element:INFO:	Eye window for uplink 22: XX__________________________________XXXX
Data delay found: 18
11:09:23:setup_element:INFO:	Eye window for uplink 23: __________________________________XXXXX_
Data delay found: 16
11:09:23:setup_element:INFO:	Eye window for uplink 24: ____XXXX________________________________
Data delay found: 25
11:09:23:setup_element:INFO:	Eye window for uplink 25: _______XXXX_____________________________
Data delay found: 28
11:09:23:setup_element:INFO:	Eye window for uplink 26: _______XXXXX____________________________
Data delay found: 29
11:09:23:setup_element:INFO:	Eye window for uplink 27: ___________XXXXX________________________
Data delay found: 33
11:09:23:setup_element:INFO:	Eye window for uplink 28: _____________XXXX_______________________
Data delay found: 34
11:09:23:setup_element:INFO:	Eye window for uplink 29: _______________XXX______________________
Data delay found: 36
11:09:23:setup_element:INFO:	Eye window for uplink 30: _______________XXXXXX___________________
Data delay found: 37
11:09:23:setup_element:INFO:	Eye window for uplink 31: ______________XXXXX_____________________
Data delay found: 36
11:09:23:setup_element:INFO:	Setting the data phase to 20 for uplink 16
11:09:23:setup_element:INFO:	Setting the data phase to 16 for uplink 17
11:09:23:setup_element:INFO:	Setting the data phase to 19 for uplink 18
11:09:23:setup_element:INFO:	Setting the data phase to 16 for uplink 19
11:09:23:setup_element:INFO:	Setting the data phase to 16 for uplink 20
11:09:23:setup_element:INFO:	Setting the data phase to 15 for uplink 21
11:09:23:setup_element:INFO:	Setting the data phase to 18 for uplink 22
11:09:23:setup_element:INFO:	Setting the data phase to 16 for uplink 23
11:09:23:setup_element:INFO:	Setting the data phase to 25 for uplink 24
11:09:23:setup_element:INFO:	Setting the data phase to 28 for uplink 25
11:09:23:setup_element:INFO:	Setting the data phase to 29 for uplink 26
11:09:23:setup_element:INFO:	Setting the data phase to 33 for uplink 27
11:09:23:setup_element:INFO:	Setting the data phase to 34 for uplink 28
11:09:23:setup_element:INFO:	Setting the data phase to 36 for uplink 29
11:09:23:setup_element:INFO:	Setting the data phase to 37 for uplink 30
11:09:23:setup_element:INFO:	Setting the data phase to 36 for uplink 31
11:09:23:ST3_emu:ERROR:	[
Setup Element:
  Group: 0
  Downlink: 2
  Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
  ASICs Map: None
  Clock Phase Characteristic:
    Optimal Phase: 34
    Window Length: 69
    Eye Windows:
      Uplink 16: ________________________________________________________________________XXXXXXXX
      Uplink 17: ________________________________________________________________________XXXXXXXX
      Uplink 18: _______________________________________________________________________XXXXXXXX_
      Uplink 19: _______________________________________________________________________XXXXXXXX_
      Uplink 20: _______________________________________________________________________XXXXXXX__
      Uplink 21: _______________________________________________________________________XXXXXXX__
      Uplink 22: _______________________________________________________________________XXXXXXXX_
      Uplink 23: _______________________________________________________________________XXXXXXXX_
      Uplink 24: _____________________________________________________________________XXXXXXXX___
      Uplink 25: _____________________________________________________________________XXXXXXXX___
      Uplink 26: _______________________________________________________________________XXXXXXXX_
      Uplink 27: _______________________________________________________________________XXXXXXXX_
      Uplink 28: _______________________________________________________________________XXXXXXXX_
      Uplink 29: _______________________________________________________________________XXXXXXXX_
      Uplink 30: _________________________________________________________________________XXXXXXX
      Uplink 31: _________________________________________________________________________XXXXXXX
  Data phase characteristics:
    Uplink 16:
      Optimal Phase: 20
      Window Length: 35
      Eye Window: XXX___________________________________XX
    Uplink 17:
      Optimal Phase: 16
      Window Length: 35
      Eye Window: __________________________________XXXXX_
    Uplink 18:
      Optimal Phase: 19
      Window Length: 34
      Eye Window: XXX__________________________________XXX
    Uplink 19:
      Optimal Phase: 16
      Window Length: 35
      Eye Window: __________________________________XXXXX_
    Uplink 20:
      Optimal Phase: 16
      Window Length: 36
      Eye Window: ___________________________________XXXX_
    Uplink 21:
      Optimal Phase: 15
      Window Length: 34
      Eye Window: _________________________________XXXXXX_
    Uplink 22:
      Optimal Phase: 18
      Window Length: 34
      Eye Window: XX__________________________________XXXX
    Uplink 23:
      Optimal Phase: 16
      Window Length: 35
      Eye Window: __________________________________XXXXX_
    Uplink 24:
      Optimal Phase: 25
      Window Length: 36
      Eye Window: ____XXXX________________________________
    Uplink 25:
      Optimal Phase: 28
      Window Length: 36
      Eye Window: _______XXXX_____________________________
    Uplink 26:
      Optimal Phase: 29
      Window Length: 35
      Eye Window: _______XXXXX____________________________
    Uplink 27:
      Optimal Phase: 33
      Window Length: 35
      Eye Window: ___________XXXXX________________________
    Uplink 28:
      Optimal Phase: 34
      Window Length: 36
      Eye Window: _____________XXXX_______________________
    Uplink 29:
      Optimal Phase: 36
      Window Length: 37
      Eye Window: _______________XXX______________________
    Uplink 30:
      Optimal Phase: 37
      Window Length: 34
      Eye Window: _______________XXXXXX___________________
    Uplink 31:
      Optimal Phase: 36
      Window Length: 35
      Eye Window: ______________XXXXX_____________________
]
11:09:23:setup_element:INFO:	Beginning SMX ASICs map scan
11:09:23:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
11:09:23:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
11:09:23:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
11:09:23:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
11:09:23:uplink:INFO:	Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
11:09:23:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 0, uplink 23
11:09:23:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 1, uplink 22
11:09:23:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 0, uplink 30
11:09:23:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 1, uplink 31
11:09:24:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 0, uplink 21
11:09:24:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 1, uplink 20
11:09:24:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 0, uplink 28
11:09:24:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 1, uplink 29
11:09:24:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 0, uplink 19
11:09:24:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 1, uplink 18
11:09:24:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 0, uplink 26
11:09:24:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 1, uplink 27
11:09:24:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 0, uplink 17
11:09:24:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 1, uplink 16
11:09:25:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 0, uplink 24
11:09:25:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 1, uplink 25
11:09:26:ST3_emu:ERROR:	
Setup Element:
  Group: 0
  Downlink: 2
  Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
  ASICs Map:
    ASIC address 0x0: (ASIC uplink, uplink): (0, 23), (1, 22)
    ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
    ASIC address 0x2: (ASIC uplink, uplink): (0, 21), (1, 20)
    ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
    ASIC address 0x4: (ASIC uplink, uplink): (0, 19), (1, 18)
    ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
    ASIC address 0x6: (ASIC uplink, uplink): (0, 17), (1, 16)
    ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
  Clock Phase Characteristic:
    Optimal Phase: 34
    Window Length: 69
    Eye Windows:
      Uplink 16: ________________________________________________________________________XXXXXXXX
      Uplink 17: ________________________________________________________________________XXXXXXXX
      Uplink 18: _______________________________________________________________________XXXXXXXX_
      Uplink 19: _______________________________________________________________________XXXXXXXX_
      Uplink 20: _______________________________________________________________________XXXXXXX__
      Uplink 21: _______________________________________________________________________XXXXXXX__
      Uplink 22: _______________________________________________________________________XXXXXXXX_
      Uplink 23: _______________________________________________________________________XXXXXXXX_
      Uplink 24: _____________________________________________________________________XXXXXXXX___
      Uplink 25: _____________________________________________________________________XXXXXXXX___
      Uplink 26: _______________________________________________________________________XXXXXXXX_
      Uplink 27: _______________________________________________________________________XXXXXXXX_
      Uplink 28: _______________________________________________________________________XXXXXXXX_
      Uplink 29: _______________________________________________________________________XXXXXXXX_
      Uplink 30: _________________________________________________________________________XXXXXXX
      Uplink 31: _________________________________________________________________________XXXXXXX
  Data phase characteristics:
    Uplink 16:
      Optimal Phase: 20
      Window Length: 35
      Eye Window: XXX___________________________________XX
    Uplink 17:
      Optimal Phase: 16
      Window Length: 35
      Eye Window: __________________________________XXXXX_
    Uplink 18:
      Optimal Phase: 19
      Window Length: 34
      Eye Window: XXX__________________________________XXX
    Uplink 19:
      Optimal Phase: 16
      Window Length: 35
      Eye Window: __________________________________XXXXX_
    Uplink 20:
      Optimal Phase: 16
      Window Length: 36
      Eye Window: ___________________________________XXXX_
    Uplink 21:
      Optimal Phase: 15
      Window Length: 34
      Eye Window: _________________________________XXXXXX_
    Uplink 22:
      Optimal Phase: 18
      Window Length: 34
      Eye Window: XX__________________________________XXXX
    Uplink 23:
      Optimal Phase: 16
      Window Length: 35
      Eye Window: __________________________________XXXXX_
    Uplink 24:
      Optimal Phase: 25
      Window Length: 36
      Eye Window: ____XXXX________________________________
    Uplink 25:
      Optimal Phase: 28
      Window Length: 36
      Eye Window: _______XXXX_____________________________
    Uplink 26:
      Optimal Phase: 29
      Window Length: 35
      Eye Window: _______XXXXX____________________________
    Uplink 27:
      Optimal Phase: 33
      Window Length: 35
      Eye Window: ___________XXXXX________________________
    Uplink 28:
      Optimal Phase: 34
      Window Length: 36
      Eye Window: _____________XXXX_______________________
    Uplink 29:
      Optimal Phase: 36
      Window Length: 37
      Eye Window: _______________XXX______________________
    Uplink 30:
      Optimal Phase: 37
      Window Length: 34
      Eye Window: _______________XXXXXX___________________
    Uplink 31:
      Optimal Phase: 36
      Window Length: 35
      Eye Window: ______________XXXXX_____________________

11:09:26:setup_element:INFO:	Performing Elink synchronization
11:09:26:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
11:09:26:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
11:09:26:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
11:09:26:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
11:09:26:setup_element:INFO:	Writing SMX Elink masks for group 0, downlink 2
11:09:26:uplink:INFO:	Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
11:09:26:ST3_emu:INFO:	Number of chips: 8
addr  |  upli  |  dwnli  |  grp |  uplinks | uplinks_map
   0  |   [0]   |  2  |  0  |     [23]     |  [(0, 23), (1, 22)]
   1  |   [0]   |  2  |  0  |     [30]     |  [(0, 30), (1, 31)]
   2  |   [0]   |  2  |  0  |     [21]     |  [(0, 21), (1, 20)]
   3  |   [0]   |  2  |  0  |     [28]     |  [(0, 28), (1, 29)]
   4  |   [0]   |  2  |  0  |     [19]     |  [(0, 19), (1, 18)]
   5  |   [0]   |  2  |  0  |     [26]     |  [(0, 26), (1, 27)]
   6  |   [0]   |  2  |  0  |     [17]     |  [(0, 17), (1, 16)]
   7  |   [0]   |  2  |  0  |     [24]     |  [(0, 24), (1, 25)]
11:09:27:febtest:INFO:	 Add. | ASIC-ID                      | T [C] | Vddm [mV]
11:09:27:febtest:INFO:	0-0 | XA-000-08-002-001-008-114-06 |   6.1 | 1288.7
11:09:27:febtest:INFO:	0-1 | XA-000-08-002-001-008-069-15 |  44.1 | 1171.5
11:09:28:febtest:INFO:	0-2 | XA-000-08-002-001-008-116-06 |  34.6 | 1195.1
11:09:28:febtest:INFO:	0-3 | XA-000-08-002-001-008-118-06 |  40.9 | 1177.4
11:09:28:febtest:INFO:	0-4 | XA-000-08-002-001-006-231-02 |  40.9 | 1177.4
11:09:28:febtest:INFO:	0-5 | XA-000-08-002-001-008-117-06 |  21.9 | 1247.9
11:09:29:febtest:INFO:	0-6 | XA-000-08-002-001-008-138-00 |  21.9 | 1236.2
11:09:29:febtest:INFO:	0-7 | XA-000-08-002-001-008-113-06 |  21.9 | 1242.0
11:09:29:ST3_smx:INFO:	PROCESS 1: Configuring AFE with typical values
11:09:32:ST3_smx:INFO:	chip: 0-0 	 25.062742 C 	 1224.468235 mV
11:09:32:ST3_smx:INFO:		Electrons
11:09:32:ST3_smx:INFO:			Injected pulses: 125LSB, amp_cal 7.000000 fC
11:09:34:ST3_smx:INFO:	----> Checking Analog response
11:09:34:ST3_smx:INFO:	----> Checking broken channels
11:09:35:ST3_smx:INFO:	Total # broken ch: 2
11:09:35:ST3_smx:INFO:	List FAST: [9, 54]
11:09:35:ST3_smx:INFO:	List SLOW: []
11:09:35:ST3_smx:INFO:		Holes
11:09:35:ST3_smx:INFO:			Injected pulses: 125LSB, amp_cal 7.000000 fC
11:09:37:ST3_smx:INFO:	----> Checking Analog response
11:09:37:ST3_smx:INFO:	----> Checking broken channels
11:09:37:ST3_smx:INFO:	Total # broken ch: 2
11:09:37:ST3_smx:INFO:	List FAST: [9, 54]
11:09:37:ST3_smx:INFO:	List SLOW: []
11:09:37:febtest:INFO:	 Add. | ASIC-ID                      | T [C] | Vddm [mV]
11:09:37:febtest:INFO:	0-0 | XA-000-08-002-001-008-114-06 |  25.1 | 1224.5
11:09:37:febtest:INFO:	0-1 | XA-000-08-002-001-008-069-15 |  44.1 | 1171.5
11:09:38:febtest:INFO:	0-2 | XA-000-08-002-001-008-116-06 |  34.6 | 1189.2
11:09:38:febtest:INFO:	0-3 | XA-000-08-002-001-008-118-06 |  40.9 | 1177.4
11:09:38:febtest:INFO:	0-4 | XA-000-08-002-001-006-231-02 |  40.9 | 1171.5
11:09:38:febtest:INFO:	0-5 | XA-000-08-002-001-008-117-06 |  18.7 | 1247.9
11:09:39:febtest:INFO:	0-6 | XA-000-08-002-001-008-138-00 |  21.9 | 1236.2
11:09:39:febtest:INFO:	0-7 | XA-000-08-002-001-008-113-06 |  21.9 | 1242.0
11:09:39:ST3_smx:INFO:	PROCESS 1: Configuring AFE with typical values
11:09:43:ST3_smx:INFO:	chip: 0-1 	 44.073563 C 	 1165.571835 mV
11:09:43:ST3_smx:INFO:		Electrons
11:09:43:ST3_smx:INFO:			Injected pulses: 125LSB, amp_cal 7.000000 fC
11:09:45:ST3_smx:INFO:	----> Checking Analog response
11:09:45:ST3_smx:INFO:	----> Checking broken channels
11:09:45:ST3_smx:INFO:	Total # broken ch: 3
11:09:45:ST3_smx:INFO:	List FAST: [43, 67, 102]
11:09:45:ST3_smx:INFO:	List SLOW: []
11:09:45:ST3_smx:INFO:		Holes
11:09:45:ST3_smx:INFO:			Injected pulses: 125LSB, amp_cal 7.000000 fC
11:09:47:ST3_smx:INFO:	----> Checking Analog response
11:09:47:ST3_smx:INFO:	----> Checking broken channels
11:09:48:ST3_smx:INFO:	Total # broken ch: 3
11:09:48:ST3_smx:INFO:	List FAST: [43, 67, 102]
11:09:48:ST3_smx:INFO:	List SLOW: []
11:09:48:febtest:INFO:	 Add. | ASIC-ID                      | T [C] | Vddm [mV]
11:09:48:febtest:INFO:	0-0 | XA-000-08-002-001-008-114-06 |  25.1 | 1224.5
11:09:48:febtest:INFO:	0-1 | XA-000-08-002-001-008-069-15 |  47.3 | 1159.7
11:09:48:febtest:INFO:	0-2 | XA-000-08-002-001-008-116-06 |  34.6 | 1195.1
11:09:48:febtest:INFO:	0-3 | XA-000-08-002-001-008-118-06 |  40.9 | 1177.4
11:09:49:febtest:INFO:	0-4 | XA-000-08-002-001-006-231-02 |  40.9 | 1171.5
11:09:49:febtest:INFO:	0-5 | XA-000-08-002-001-008-117-06 |  21.9 | 1247.9
11:09:49:febtest:INFO:	0-6 | XA-000-08-002-001-008-138-00 |  21.9 | 1236.2
11:09:49:febtest:INFO:	0-7 | XA-000-08-002-001-008-113-06 |  21.9 | 1242.0
11:09:50:ST3_smx:INFO:	PROCESS 1: Configuring AFE with typical values
11:09:53:ST3_smx:INFO:	chip: 0-2 	 37.726682 C 	 1189.190035 mV
11:09:53:ST3_smx:INFO:		Electrons
11:09:53:ST3_smx:INFO:			Injected pulses: 125LSB, amp_cal 7.000000 fC
11:09:55:ST3_smx:INFO:	----> Checking Analog response
11:09:55:ST3_smx:INFO:	----> Checking broken channels
11:09:55:ST3_smx:INFO:	Total # broken ch: 3
11:09:55:ST3_smx:INFO:	List FAST: [15, 93, 123]
11:09:55:ST3_smx:INFO:	List SLOW: []
11:09:55:ST3_smx:INFO:		Holes
11:09:55:ST3_smx:INFO:			Injected pulses: 125LSB, amp_cal 7.000000 fC
11:09:57:ST3_smx:INFO:	----> Checking Analog response
11:09:57:ST3_smx:INFO:	----> Checking broken channels
11:09:58:ST3_smx:INFO:	Total # broken ch: 3
11:09:58:ST3_smx:INFO:	List FAST: [15, 93, 123]
11:09:58:ST3_smx:INFO:	List SLOW: []
11:09:58:febtest:INFO:	 Add. | ASIC-ID                      | T [C] | Vddm [mV]
11:09:58:febtest:INFO:	0-0 | XA-000-08-002-001-008-114-06 |  25.1 | 1224.5
11:09:58:febtest:INFO:	0-1 | XA-000-08-002-001-008-069-15 |  47.3 | 1159.7
11:09:58:febtest:INFO:	0-2 | XA-000-08-002-001-008-116-06 |  37.7 | 1183.3
11:09:59:febtest:INFO:	0-3 | XA-000-08-002-001-008-118-06 |  44.1 | 1177.4
11:09:59:febtest:INFO:	0-4 | XA-000-08-002-001-006-231-02 |  40.9 | 1177.4
11:09:59:febtest:INFO:	0-5 | XA-000-08-002-001-008-117-06 |  21.9 | 1247.9
11:09:59:febtest:INFO:	0-6 | XA-000-08-002-001-008-138-00 |  21.9 | 1236.2
11:10:00:febtest:INFO:	0-7 | XA-000-08-002-001-008-113-06 |  25.1 | 1242.0
11:10:00:ST3_smx:INFO:	PROCESS 1: Configuring AFE with typical values
11:10:04:ST3_smx:INFO:	chip: 0-3 	 31.389742 C 	 1212.728715 mV
11:10:04:ST3_smx:INFO:		Electrons
11:10:04:ST3_smx:INFO:			Injected pulses: 125LSB, amp_cal 7.000000 fC
11:10:06:ST3_smx:INFO:	----> Checking Analog response
11:10:06:ST3_smx:INFO:	----> Checking broken channels
11:10:06:ST3_smx:INFO:	Total # broken ch: 3
11:10:06:ST3_smx:INFO:	List FAST: [83, 95, 117]
11:10:06:ST3_smx:INFO:	List SLOW: []
11:10:06:ST3_smx:INFO:		Holes
11:10:06:ST3_smx:INFO:			Injected pulses: 125LSB, amp_cal 7.000000 fC
11:10:08:ST3_smx:INFO:	----> Checking Analog response
11:10:08:ST3_smx:INFO:	----> Checking broken channels
11:10:08:ST3_smx:INFO:	Total # broken ch: 3
11:10:08:ST3_smx:INFO:	List FAST: [83, 95, 117]
11:10:08:ST3_smx:INFO:	List SLOW: []
11:10:08:febtest:INFO:	 Add. | ASIC-ID                      | T [C] | Vddm [mV]
11:10:08:febtest:INFO:	0-0 | XA-000-08-002-001-008-114-06 |  25.1 | 1224.5
11:10:09:febtest:INFO:	0-1 | XA-000-08-002-001-008-069-15 |  47.3 | 1159.7
11:10:09:febtest:INFO:	0-2 | XA-000-08-002-001-008-116-06 |  37.7 | 1183.3
11:10:09:febtest:INFO:	0-3 | XA-000-08-002-001-008-118-06 |  34.6 | 1206.9
11:10:09:febtest:INFO:	0-4 | XA-000-08-002-001-006-231-02 |  40.9 | 1177.4
11:10:09:febtest:INFO:	0-5 | XA-000-08-002-001-008-117-06 |  21.9 | 1247.9
11:10:10:febtest:INFO:	0-6 | XA-000-08-002-001-008-138-00 |  21.9 | 1236.2
11:10:10:febtest:INFO:	0-7 | XA-000-08-002-001-008-113-06 |  21.9 | 1242.0
11:10:10:ST3_smx:INFO:	PROCESS 1: Configuring AFE with typical values
11:10:14:ST3_smx:INFO:	chip: 0-4 	 40.898880 C 	 1171.483840 mV
11:10:14:ST3_smx:INFO:		Electrons
11:10:14:ST3_smx:INFO:			Injected pulses: 125LSB, amp_cal 7.000000 fC
11:10:16:ST3_smx:INFO:	----> Checking Analog response
11:10:16:ST3_smx:INFO:	----> Checking broken channels
11:10:16:ST3_smx:INFO:	Total # broken ch: 1
11:10:16:ST3_smx:INFO:	List FAST: [57]
11:10:16:ST3_smx:INFO:	List SLOW: []
11:10:16:ST3_smx:INFO:		Holes
11:10:16:ST3_smx:INFO:			Injected pulses: 125LSB, amp_cal 7.000000 fC
11:10:18:ST3_smx:INFO:	----> Checking Analog response
11:10:18:ST3_smx:INFO:	----> Checking broken channels
11:10:18:ST3_smx:INFO:	Total # broken ch: 1
11:10:18:ST3_smx:INFO:	List FAST: [57]
11:10:18:ST3_smx:INFO:	List SLOW: []
11:10:18:febtest:INFO:	 Add. | ASIC-ID                      | T [C] | Vddm [mV]
11:10:18:febtest:INFO:	0-0 | XA-000-08-002-001-008-114-06 |  25.1 | 1224.5
11:10:19:febtest:INFO:	0-1 | XA-000-08-002-001-008-069-15 |  47.3 | 1165.6
11:10:19:febtest:INFO:	0-2 | XA-000-08-002-001-008-116-06 |  37.7 | 1183.3
11:10:19:febtest:INFO:	0-3 | XA-000-08-002-001-008-118-06 |  34.6 | 1212.7
11:10:19:febtest:INFO:	0-4 | XA-000-08-002-001-006-231-02 |  44.1 | 1165.6
11:10:20:febtest:INFO:	0-5 | XA-000-08-002-001-008-117-06 |  21.9 | 1247.9
11:10:20:febtest:INFO:	0-6 | XA-000-08-002-001-008-138-00 |  21.9 | 1236.2
11:10:20:febtest:INFO:	0-7 | XA-000-08-002-001-008-113-06 |  25.1 | 1242.0
11:10:20:ST3_smx:INFO:	PROCESS 1: Configuring AFE with typical values
11:10:24:ST3_smx:INFO:	chip: 0-5 	 28.225000 C 	 1224.468235 mV
11:10:24:ST3_smx:INFO:		Electrons
11:10:24:ST3_smx:INFO:			Injected pulses: 125LSB, amp_cal 7.000000 fC
11:10:26:ST3_smx:INFO:	----> Checking Analog response
11:10:26:ST3_smx:INFO:	----> Checking broken channels
11:10:26:ST3_smx:INFO:	Total # broken ch: 2
11:10:26:ST3_smx:INFO:	List FAST: [21, 99]
11:10:26:ST3_smx:INFO:	List SLOW: []
11:10:26:ST3_smx:INFO:		Holes
11:10:26:ST3_smx:INFO:			Injected pulses: 125LSB, amp_cal 7.000000 fC
11:10:28:ST3_smx:INFO:	----> Checking Analog response
11:10:28:ST3_smx:INFO:	----> Checking broken channels
11:10:28:ST3_smx:INFO:	Total # broken ch: 2
11:10:28:ST3_smx:INFO:	List FAST: [21, 99]
11:10:28:ST3_smx:INFO:	List SLOW: []
11:10:28:febtest:INFO:	 Add. | ASIC-ID                      | T [C] | Vddm [mV]
11:10:29:febtest:INFO:	0-0 | XA-000-08-002-001-008-114-06 |  25.1 | 1224.5
11:10:29:febtest:INFO:	0-1 | XA-000-08-002-001-008-069-15 |  47.3 | 1165.6
11:10:29:febtest:INFO:	0-2 | XA-000-08-002-001-008-116-06 |  37.7 | 1183.3
11:10:29:febtest:INFO:	0-3 | XA-000-08-002-001-008-118-06 |  34.6 | 1212.7
11:10:30:febtest:INFO:	0-4 | XA-000-08-002-001-006-231-02 |  44.1 | 1165.6
11:10:30:febtest:INFO:	0-5 | XA-000-08-002-001-008-117-06 |  28.2 | 1218.6
11:10:30:febtest:INFO:	0-6 | XA-000-08-002-001-008-138-00 |  25.1 | 1236.2
11:10:30:febtest:INFO:	0-7 | XA-000-08-002-001-008-113-06 |  25.1 | 1242.0
11:10:31:ST3_smx:INFO:	PROCESS 1: Configuring AFE with typical values
11:10:34:ST3_smx:INFO:	chip: 0-6 	 28.225000 C 	 1218.600960 mV
11:10:34:ST3_smx:INFO:		Electrons
11:10:34:ST3_smx:INFO:			Injected pulses: 125LSB, amp_cal 7.000000 fC
11:10:36:ST3_smx:INFO:	----> Checking Analog response
11:10:36:ST3_smx:INFO:	----> Checking broken channels
11:10:36:ST3_smx:INFO:	Total # broken ch: 3
11:10:36:ST3_smx:INFO:	List FAST: [7, 34, 36]
11:10:36:ST3_smx:INFO:	List SLOW: []
11:10:36:ST3_smx:INFO:		Holes
11:10:36:ST3_smx:INFO:			Injected pulses: 125LSB, amp_cal 7.000000 fC
11:10:38:ST3_smx:INFO:	----> Checking Analog response
11:10:38:ST3_smx:INFO:	----> Checking broken channels
11:10:39:ST3_smx:INFO:	Total # broken ch: 3
11:10:39:ST3_smx:INFO:	List FAST: [7, 34, 36]
11:10:39:ST3_smx:INFO:	List SLOW: []
11:10:39:febtest:INFO:	 Add. | ASIC-ID                      | T [C] | Vddm [mV]
11:10:39:febtest:INFO:	0-0 | XA-000-08-002-001-008-114-06 |  25.1 | 1224.5
11:10:39:febtest:INFO:	0-1 | XA-000-08-002-001-008-069-15 |  47.3 | 1165.6
11:10:39:febtest:INFO:	0-2 | XA-000-08-002-001-008-116-06 |  37.7 | 1183.3
11:10:40:febtest:INFO:	0-3 | XA-000-08-002-001-008-118-06 |  34.6 | 1212.7
11:10:40:febtest:INFO:	0-4 | XA-000-08-002-001-006-231-02 |  44.1 | 1165.6
11:10:40:febtest:INFO:	0-5 | XA-000-08-002-001-008-117-06 |  28.2 | 1224.5
11:10:40:febtest:INFO:	0-6 | XA-000-08-002-001-008-138-00 |  31.4 | 1212.7
11:10:41:febtest:INFO:	0-7 | XA-000-08-002-001-008-113-06 |  25.1 | 1242.0
11:10:41:ST3_smx:INFO:	PROCESS 1: Configuring AFE with typical values
11:10:44:ST3_smx:INFO:	chip: 0-7 	 28.225000 C 	 1224.468235 mV
11:10:44:ST3_smx:INFO:		Electrons
11:10:44:ST3_smx:INFO:			Injected pulses: 125LSB, amp_cal 7.000000 fC
11:10:46:ST3_smx:INFO:	----> Checking Analog response
11:10:46:ST3_smx:INFO:	----> Checking broken channels
11:10:47:ST3_smx:INFO:	Total # broken ch: 1
11:10:47:ST3_smx:INFO:	List FAST: [41]
11:10:47:ST3_smx:INFO:	List SLOW: []
11:10:47:ST3_smx:INFO:		Holes
11:10:47:ST3_smx:INFO:			Injected pulses: 125LSB, amp_cal 7.000000 fC
11:10:49:ST3_smx:INFO:	----> Checking Analog response
11:10:49:ST3_smx:INFO:	----> Checking broken channels
11:10:49:ST3_smx:INFO:	Total # broken ch: 1
11:10:49:ST3_smx:INFO:	List FAST: [41]
11:10:49:ST3_smx:INFO:	List SLOW: []
11:10:49:febtest:INFO:	 Add. | ASIC-ID                      | T [C] | Vddm [mV]
11:10:49:febtest:INFO:	0-0 | XA-000-08-002-001-008-114-06 |  25.1 | 1224.5
11:10:49:febtest:INFO:	0-1 | XA-000-08-002-001-008-069-15 |  47.3 | 1165.6
11:10:50:febtest:INFO:	0-2 | XA-000-08-002-001-008-116-06 |  37.7 | 1183.3
11:10:50:febtest:INFO:	0-3 | XA-000-08-002-001-008-118-06 |  34.6 | 1212.7
11:10:50:febtest:INFO:	0-4 | XA-000-08-002-001-006-231-02 |  44.1 | 1165.6
11:10:50:febtest:INFO:	0-5 | XA-000-08-002-001-008-117-06 |  28.2 | 1224.5
11:10:50:febtest:INFO:	0-6 | XA-000-08-002-001-008-138-00 |  31.4 | 1212.7
11:10:51:febtest:INFO:	0-7 | XA-000-08-002-001-008-113-06 |  28.2 | 1218.6
############################################################
#                   S U M M A R Y                          #
############################################################
{'TEST_NAME': 'FEB-ASIC', 'TEST_DATE': '2023_11_28-11_09_15', 'OPERATOR': 'Irakli K.; ', 'PROJECT': 'Production', 'SITE': 'GSI', 'SETUP': 'GSI_TEST_SETUP_1', 'ASIC_ID': 'XA-000-08-002-001-008-113-06', 'FUSED_ID': 6359364699117618966, 'HW_ADDR': 7, 'UPLINK': 24, 'VERS_NO': '2.2', 'CABLE_SET_ID': '', 'IC_TEMP': '0', 'VDDM': '0', 'AUX': '0', 'CSABIAS': '0', 'VDDM_INT': '0', 'ADC_Chi2': 0.0, 'ADC_NDF': 0, 'ADC_P0': 0.0, 'ADC_P1': 0.006824, 'ADC_P2': -2.485e-06, 'ADC_P0err': 0.001, 'ADC_P1err': 0.001, 'ADC_P2err': 1e-05, 'ADC_VREF_P': 58, 'ADC_VREF_N': 30, 'ADC_VREF_T': 128, 'ADC_VREF_TR': 122, 'THR2_GLB': 30, 'LOOP__PLS': 100, 'CALIB_PLS': 250, 'SnsLoop': 5, 'IFED': 31, 'CSA_BIAS': 15, 'CSA_Chi2': 0.0, 'CSA_NDF': 0, 'CSA_P0': 0.0, 'CSA_P1': 0.0, 'CSA_P2': 0.0, 'CSA_P0err': 0.0, 'CSA_P1err': 0.0, 'CSA_P2err': 0.0, 'CONF_FAIL_REG': 0, 'N_BROKEN_DISC': 1, 'N_BROKEN_FAST': '[41]', 'N_BROKEN_SLOW': '[]', 'P_BROKEN_DISC': 1, 'P_BROKEN_FAST': '[41]', 'P_BROKEN_SLOW': '[]', 'ASIC_QA_category': '', 'N_BROKEN_CABLE': 0, 'LIST_OF_BROKEN_CABLES': 0, 'FEB_SN': '1086', 'FEB_TYPE': 8.2, 'FEB_UPLINKS': 2, 'FEB_A': 1, 'FEB_B': 0, 'ADDR_0': '', 'ADDR_1': '', 'ADDR_2': '', 'ADDR_3': '', 'ADDR_4': '', 'ADDR_5': '', 'ADDR_6': '', 'ADDR_7': '', 'SENSOR_ID': '', 'MODULE_NAME': '', 'MODULE_LADDER': '', 'MODULE_MODULE': '', 'MODULE_SIZE': '', 'MODULE_GRADE': '', 'MODULE_TYPE': '', 'VI_bInit': ['2.448', '1.4460', '1.846', '2.2830', '7.000', '1.5500', '7.000', '1.5500'], 'VI_aInit': ['2.450', '1.9990', '1.850', '0.3154', '7.000', '1.5560', '7.000', '1.5560'], 'VI_atEnd': ['2.450', '1.9990', '1.850', '0.3153', '7.000', '1.5560', '7.000', '1.5560'], 'AMP_CAL': 125, 'PlsLoop': 3, 'N_ANA_PRESENT': 'Analog response OK', 'N_DISC_FAIL_CH': 0, 'N_ANA_FAIL_CH': '0', 'P_ANA_PRESENT': 'Analog response OK', 'P_DISC_FAIL_CH': 0, 'P_ANA_FAIL_CH': '0'}
===============================

{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

############################################################
#                   S U M M A R Y                          #
############################################################
TEST_NAME : FEB-ASIC
TEST_DATE : 2023_11_28-11_09_15
OPERATOR  : Irakli K.; 
SITE      : GSI
SETUP     : GSI_TEST_SETUP_1
Set-ID    : 
---------------------------------------
MODULE_NAME : 
FEB_SN : 1086
FEB_TYPE : 8.2
FEB_UPLINKS : 2
FEB_A : 1
FEB_B : 0
---------------------------------------
MODULE_NAME
---------------------------------------
VI_before_Init : ['2.448', '1.4460', '1.846', '2.2830', '7.000', '1.5500', '7.000', '1.5500']
VI_after__Init : ['2.450', '1.9830', '1.850', '0.3127', '7.000', '1.5560', '7.000', '1.5560']
VI_at__the_End : ['2.450', '1.9830', '1.850', '0.3127', '7.000', '1.5560', '7.000', '1.5560']
11:11:02:ST3_Shared:INFO:	/home/cbm/public_html/Production_LogDir//FEB/FEB_2014/TestDate_2023_11_28-11_09_15/
Comment.txt