09:54:52:ST3_hmp4040:INFO:	HAMEG,HMP2030,017836163,HW50010002/SW2.30
09:54:52:febtest:INFO:	FEB8.2 selected
09:54:52:febtest:INFO:	FEB8.2 selected
09:54:58:ST3_Shared:INFO:	Listo of operators:Oleksandr S.; 
09:56:40:smx_tester:INFO:	Setting Elink clock mode to 160 MHz
09:56:46:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
09:56:46:ST3_Shared:INFO:	-----------------------FEB-Microcable-----------------------
09:56:46:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
09:56:46:febtest:INFO:	Tsting FEB with SN 2021
09:56:47:smx_tester:INFO:	Scanning setup
09:56:47:elinks:INFO:	Disabling clock on downlink 0
09:56:47:elinks:INFO:	Disabling clock on downlink 1
09:56:47:elinks:INFO:	Disabling clock on downlink 2
09:56:47:elinks:INFO:	Disabling clock on downlink 3
09:56:47:elinks:INFO:	Disabling clock on downlink 4
09:56:47:setup_element:INFO:	Checking SOS, encoding_mode: SOS
09:56:47:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
09:56:48:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
09:56:48:elinks:INFO:	Disabling clock on downlink 0
09:56:48:elinks:INFO:	Disabling clock on downlink 1
09:56:48:elinks:INFO:	Disabling clock on downlink 2
09:56:48:elinks:INFO:	Disabling clock on downlink 3
09:56:48:elinks:INFO:	Disabling clock on downlink 4
09:56:48:setup_element:INFO:	Checking SOS, encoding_mode: SOS
09:56:48:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
09:56:48:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
09:56:48:elinks:INFO:	Disabling clock on downlink 0
09:56:48:elinks:INFO:	Disabling clock on downlink 1
09:56:48:elinks:INFO:	Disabling clock on downlink 2
09:56:48:elinks:INFO:	Disabling clock on downlink 3
09:56:48:elinks:INFO:	Disabling clock on downlink 4
09:56:48:setup_element:INFO:	Checking SOS, encoding_mode: SOS
09:56:48:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
09:56:48:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 24
09:56:48:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 25
09:56:48:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 26
09:56:48:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 27
09:56:48:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 28
09:56:48:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 29
09:56:48:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 30
09:56:48:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 31
09:56:48:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
09:56:48:elinks:INFO:	Disabling clock on downlink 0
09:56:48:elinks:INFO:	Disabling clock on downlink 1
09:56:48:elinks:INFO:	Disabling clock on downlink 2
09:56:48:elinks:INFO:	Disabling clock on downlink 3
09:56:48:elinks:INFO:	Disabling clock on downlink 4
09:56:48:setup_element:INFO:	Checking SOS, encoding_mode: SOS
09:56:48:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
09:56:48:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
09:56:48:elinks:INFO:	Disabling clock on downlink 0
09:56:48:elinks:INFO:	Disabling clock on downlink 1
09:56:48:elinks:INFO:	Disabling clock on downlink 2
09:56:48:elinks:INFO:	Disabling clock on downlink 3
09:56:48:elinks:INFO:	Disabling clock on downlink 4
09:56:48:setup_element:INFO:	Checking SOS, encoding_mode: SOS
09:56:48:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [4]
09:56:48:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
09:56:48:setup_element:INFO:	Scanning clock phase
09:56:48:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
09:56:48:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
09:56:49:setup_element:INFO:	Clock phase scan results for group 0, downlink 2
09:56:49:setup_element:INFO:	Eye window for uplink 24: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
09:56:49:setup_element:INFO:	Eye window for uplink 25: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
09:56:49:setup_element:INFO:	Eye window for uplink 26: _____________________________________________________________________XXXXXXXXXX_
Clock Delay: 33
09:56:49:setup_element:INFO:	Eye window for uplink 27: _____________________________________________________________________XXXXXXXXXX_
Clock Delay: 33
09:56:49:setup_element:INFO:	Eye window for uplink 28: _____________________________________________________________________XXXXXXX____
Clock Delay: 32
09:56:49:setup_element:INFO:	Eye window for uplink 29: _____________________________________________________________________XXXXXXX____
Clock Delay: 32
09:56:49:setup_element:INFO:	Eye window for uplink 30: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
09:56:49:setup_element:INFO:	Eye window for uplink 31: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
09:56:49:setup_element:INFO:	Setting the clock phase to 33 for group 0, downlink 2
09:56:49:setup_element:INFO:	Scanning data phases
09:56:49:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
09:56:49:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
09:56:54:setup_element:INFO:	Data phase scan results for group 0, downlink 2
09:56:54:setup_element:INFO:	Eye window for uplink 24: ____XXXXXX______________________________
Data delay found: 26
09:56:54:setup_element:INFO:	Eye window for uplink 25: _______XXXXX____________________________
Data delay found: 29
09:56:54:setup_element:INFO:	Eye window for uplink 26: _______XXXXX____________________________
Data delay found: 29
09:56:54:setup_element:INFO:	Eye window for uplink 27: __________XXXXXX________________________
Data delay found: 32
09:56:54:setup_element:INFO:	Eye window for uplink 28: _________XXXXX__________________________
Data delay found: 31
09:56:54:setup_element:INFO:	Eye window for uplink 29: __________XXXXX_________________________
Data delay found: 32
09:56:54:setup_element:INFO:	Eye window for uplink 30: _________________XXXXXX_________________
Data delay found: 39
09:56:54:setup_element:INFO:	Eye window for uplink 31: _______________XXXXXXX__________________
Data delay found: 38
09:56:54:setup_element:INFO:	Setting the data phase to 26 for uplink 24
09:56:54:setup_element:INFO:	Setting the data phase to 29 for uplink 25
09:56:54:setup_element:INFO:	Setting the data phase to 29 for uplink 26
09:56:54:setup_element:INFO:	Setting the data phase to 32 for uplink 27
09:56:54:setup_element:INFO:	Setting the data phase to 31 for uplink 28
09:56:54:setup_element:INFO:	Setting the data phase to 32 for uplink 29
09:56:54:setup_element:INFO:	Setting the data phase to 39 for uplink 30
09:56:54:setup_element:INFO:	Setting the data phase to 38 for uplink 31
09:56:54:ST3_emu:ERROR:	[
Setup Element:
  Group: 0
  Downlink: 2
  Uplinks: [24, 25, 26, 27, 28, 29, 30, 31]
  ASICs Map: None
  Clock Phase Characteristic:
    Optimal Phase: 33
    Window Length: 70
    Eye Windows:
      Uplink 24: _____________________________________________________________________XXXXXXXX___
      Uplink 25: _____________________________________________________________________XXXXXXXX___
      Uplink 26: _____________________________________________________________________XXXXXXXXXX_
      Uplink 27: _____________________________________________________________________XXXXXXXXXX_
      Uplink 28: _____________________________________________________________________XXXXXXX____
      Uplink 29: _____________________________________________________________________XXXXXXX____
      Uplink 30: _______________________________________________________________________XXXXXXX__
      Uplink 31: _______________________________________________________________________XXXXXXX__
  Data phase characteristics:
    Uplink 24:
      Optimal Phase: 26
      Window Length: 34
      Eye Window: ____XXXXXX______________________________
    Uplink 25:
      Optimal Phase: 29
      Window Length: 35
      Eye Window: _______XXXXX____________________________
    Uplink 26:
      Optimal Phase: 29
      Window Length: 35
      Eye Window: _______XXXXX____________________________
    Uplink 27:
      Optimal Phase: 32
      Window Length: 34
      Eye Window: __________XXXXXX________________________
    Uplink 28:
      Optimal Phase: 31
      Window Length: 35
      Eye Window: _________XXXXX__________________________
    Uplink 29:
      Optimal Phase: 32
      Window Length: 35
      Eye Window: __________XXXXX_________________________
    Uplink 30:
      Optimal Phase: 39
      Window Length: 34
      Eye Window: _________________XXXXXX_________________
    Uplink 31:
      Optimal Phase: 38
      Window Length: 33
      Eye Window: _______________XXXXXXX__________________
]
09:56:54:setup_element:INFO:	Beginning SMX ASICs map scan
09:56:54:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
09:56:54:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
09:56:54:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
09:56:54:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
09:56:54:uplink:INFO:	Setting uplinks mask [24, 25, 26, 27, 28, 29, 30, 31]
09:56:54:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 0, uplink 30
09:56:54:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 1, uplink 31
09:56:55:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 0, uplink 28
09:56:55:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 1, uplink 29
09:56:55:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 0, uplink 26
09:56:55:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 1, uplink 27
09:56:55:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 0, uplink 24
09:56:55:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 1, uplink 25
09:56:57:ST3_emu:ERROR:	
Setup Element:
  Group: 0
  Downlink: 2
  Uplinks: [24, 25, 26, 27, 28, 29, 30, 31]
  ASICs Map:
    ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
    ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
    ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
    ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
  Clock Phase Characteristic:
    Optimal Phase: 33
    Window Length: 70
    Eye Windows:
      Uplink 24: _____________________________________________________________________XXXXXXXX___
      Uplink 25: _____________________________________________________________________XXXXXXXX___
      Uplink 26: _____________________________________________________________________XXXXXXXXXX_
      Uplink 27: _____________________________________________________________________XXXXXXXXXX_
      Uplink 28: _____________________________________________________________________XXXXXXX____
      Uplink 29: _____________________________________________________________________XXXXXXX____
      Uplink 30: _______________________________________________________________________XXXXXXX__
      Uplink 31: _______________________________________________________________________XXXXXXX__
  Data phase characteristics:
    Uplink 24:
      Optimal Phase: 26
      Window Length: 34
      Eye Window: ____XXXXXX______________________________
    Uplink 25:
      Optimal Phase: 29
      Window Length: 35
      Eye Window: _______XXXXX____________________________
    Uplink 26:
      Optimal Phase: 29
      Window Length: 35
      Eye Window: _______XXXXX____________________________
    Uplink 27:
      Optimal Phase: 32
      Window Length: 34
      Eye Window: __________XXXXXX________________________
    Uplink 28:
      Optimal Phase: 31
      Window Length: 35
      Eye Window: _________XXXXX__________________________
    Uplink 29:
      Optimal Phase: 32
      Window Length: 35
      Eye Window: __________XXXXX_________________________
    Uplink 30:
      Optimal Phase: 39
      Window Length: 34
      Eye Window: _________________XXXXXX_________________
    Uplink 31:
      Optimal Phase: 38
      Window Length: 33
      Eye Window: _______________XXXXXXX__________________

09:56:57:setup_element:INFO:	Performing Elink synchronization
09:56:57:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
09:56:57:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
09:56:57:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
09:56:57:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
09:56:57:setup_element:INFO:	Writing SMX Elink masks for group 0, downlink 2
09:56:57:uplink:INFO:	Enabling uplinks [24, 25, 26, 27, 28, 29, 30, 31]
09:56:57:ST3_emu:INFO:	Number of chips: 4
09:56:57:ST3_emu:INFO:	Chip address:  	0x1
09:56:57:ST3_emu:INFO:	Chip address:  	0x3
09:56:57:ST3_emu:INFO:	Chip address:  	0x5
09:56:57:ST3_emu:INFO:	Chip address:  	0x7
09:56:58:febtest:INFO:	 Add. | ASIC-ID                      | T [C] | Vddm [mV]
09:56:58:febtest:INFO:	0-1 | XA-000-08-002-002-006-003-02 |   3.0 | 1271.2
09:56:58:febtest:INFO:	0-3 | XA-000-08-001-064-050-176-10 |  25.1 | 1201.0
09:56:58:febtest:INFO:	0-5 | XA-000-08-001-064-052-056-05 |  12.4 | 1236.2
09:56:59:febtest:INFO:	0-7 | XA-000-08-001-064-050-208-01 |  25.1 | 1195.1
09:56:59:ST3_smx:INFO:	PROCESS 1: Configuring AFE with typical values
09:57:02:ST3_smx:INFO:	chip: 0-1 	 12.438562 C 	 1224.468235 mV
09:57:02:ST3_smx:INFO:	# loops 0
09:57:04:ST3_smx:INFO:	# loops 1
09:57:06:ST3_smx:INFO:	# loops 2
09:57:08:ST3_smx:INFO:	# loops 3
09:57:09:ST3_smx:INFO:	# loops 4
09:57:11:ST3_smx:INFO:	Total # of broken channels: 0
09:57:11:ST3_smx:INFO:	List of broken channels: []
09:57:11:ST3_smx:INFO:	Total # of broken channels: 0
09:57:11:ST3_smx:INFO:	List of broken channels: []
09:57:12:ST3_smx:INFO:	PROCESS 1: Configuring AFE with typical values
09:57:16:ST3_smx:INFO:	chip: 0-3 	 28.225000 C 	 1177.390875 mV
09:57:16:ST3_smx:INFO:	# loops 0
09:57:18:ST3_smx:INFO:	# loops 1
09:57:19:ST3_smx:INFO:	# loops 2
09:57:21:ST3_smx:INFO:	# loops 3
09:57:23:ST3_smx:INFO:	# loops 4
09:57:25:ST3_smx:INFO:	Total # of broken channels: 0
09:57:25:ST3_smx:INFO:	List of broken channels: []
09:57:25:ST3_smx:INFO:	Total # of broken channels: 0
09:57:25:ST3_smx:INFO:	List of broken channels: []
09:57:25:ST3_smx:INFO:	PROCESS 1: Configuring AFE with typical values
09:57:29:ST3_smx:INFO:	chip: 0-5 	 15.590880 C 	 1212.728715 mV
09:57:29:ST3_smx:INFO:	# loops 0
09:57:31:ST3_smx:INFO:	# loops 1
09:57:32:ST3_smx:INFO:	# loops 2
09:57:34:ST3_smx:INFO:	# loops 3
09:57:36:ST3_smx:INFO:	# loops 4
09:57:38:ST3_smx:INFO:	Total # of broken channels: 0
09:57:38:ST3_smx:INFO:	List of broken channels: []
09:57:38:ST3_smx:INFO:	Total # of broken channels: 0
09:57:38:ST3_smx:INFO:	List of broken channels: []
09:57:38:ST3_smx:INFO:	PROCESS 1: Configuring AFE with typical values
09:57:42:ST3_smx:INFO:	chip: 0-7 	 31.389742 C 	 1159.654860 mV
09:57:42:ST3_smx:INFO:	# loops 0
09:57:44:ST3_smx:INFO:	# loops 1
09:57:46:ST3_smx:INFO:	# loops 2
09:57:47:ST3_smx:INFO:	# loops 3
09:57:49:ST3_smx:INFO:	# loops 4
09:57:51:ST3_smx:INFO:	Total # of broken channels: 0
09:57:51:ST3_smx:INFO:	List of broken channels: []
09:57:51:ST3_smx:INFO:	Total # of broken channels: 0
09:57:51:ST3_smx:INFO:	List of broken channels: []
09:57:51:febtest:INFO:	 Add. | ASIC-ID                      | T [C] | Vddm [mV]
09:57:51:febtest:INFO:	0-1 | XA-000-08-002-002-006-003-02 |  15.6 | 1212.7
09:57:52:febtest:INFO:	0-3 | XA-000-08-001-064-050-176-10 |  31.4 | 1165.6
09:57:52:febtest:INFO:	0-5 | XA-000-08-001-064-052-056-05 |  15.6 | 1206.9
09:57:52:febtest:INFO:	0-7 | XA-000-08-001-064-050-208-01 |  34.6 | 1159.7
09:58:03:ST3_Shared:INFO:	/home/cbm/public_html/Production_LogDir//FEB/FEB_2021/B//TestDate_2023_09_21-09_56_46/