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FEB_2027 20.11.23 16:05:53
TextEdit.txt
16:05:48:ST3_hmp4040:INFO: HAMEG,HMP2030,017836163,HW50010002/SW2.30
16:05:49:febtest:INFO: FEB8.2 selected
16:05:49:smx_tester:INFO: Setting Elink clock mode to 160 MHz
16:05:53:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
16:05:53:ST3_Shared:INFO: --------------------------FEB-ASIC--------------------------
16:05:53:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
16:05:53:febtest:INFO: Tsting FEB with SN 2027
16:05:54:smx_tester:INFO: Scanning setup
16:05:54:elinks:INFO: Disabling clock on downlink 0
16:05:54:elinks:INFO: Disabling clock on downlink 1
16:05:54:elinks:INFO: Disabling clock on downlink 2
16:05:54:elinks:INFO: Disabling clock on downlink 3
16:05:54:elinks:INFO: Disabling clock on downlink 4
16:05:54:setup_element:INFO: Checking SOS, encoding_mode: SOS
16:05:54:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
16:05:54:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
16:05:54:elinks:INFO: Disabling clock on downlink 0
16:05:54:elinks:INFO: Disabling clock on downlink 1
16:05:54:elinks:INFO: Disabling clock on downlink 2
16:05:54:elinks:INFO: Disabling clock on downlink 3
16:05:54:elinks:INFO: Disabling clock on downlink 4
16:05:54:setup_element:INFO: Checking SOS, encoding_mode: SOS
16:05:54:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
16:05:54:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
16:05:54:elinks:INFO: Disabling clock on downlink 0
16:05:54:elinks:INFO: Disabling clock on downlink 1
16:05:54:elinks:INFO: Disabling clock on downlink 2
16:05:54:elinks:INFO: Disabling clock on downlink 3
16:05:54:elinks:INFO: Disabling clock on downlink 4
16:05:54:setup_element:INFO: Checking SOS, encoding_mode: SOS
16:05:54:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
16:05:55:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 16
16:05:55:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 17
16:05:55:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 18
16:05:55:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 19
16:05:55:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 20
16:05:55:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 21
16:05:55:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 22
16:05:55:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 23
16:05:55:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24
16:05:55:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25
16:05:55:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26
16:05:55:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27
16:05:55:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28
16:05:55:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29
16:05:55:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30
16:05:55:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31
16:05:55:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
16:05:55:elinks:INFO: Disabling clock on downlink 0
16:05:55:elinks:INFO: Disabling clock on downlink 1
16:05:55:elinks:INFO: Disabling clock on downlink 2
16:05:55:elinks:INFO: Disabling clock on downlink 3
16:05:55:elinks:INFO: Disabling clock on downlink 4
16:05:55:setup_element:INFO: Checking SOS, encoding_mode: SOS
16:05:55:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
16:05:55:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
16:05:55:elinks:INFO: Disabling clock on downlink 0
16:05:55:elinks:INFO: Disabling clock on downlink 1
16:05:55:elinks:INFO: Disabling clock on downlink 2
16:05:55:elinks:INFO: Disabling clock on downlink 3
16:05:55:elinks:INFO: Disabling clock on downlink 4
16:05:55:setup_element:INFO: Checking SOS, encoding_mode: SOS
16:05:55:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
16:05:55:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
16:05:55:setup_element:INFO: Scanning clock phase
16:05:55:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
16:05:55:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
16:05:55:setup_element:INFO: Clock phase scan results for group 0, downlink 2
16:05:55:setup_element:INFO: Eye window for uplink 16: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
16:05:55:setup_element:INFO: Eye window for uplink 17: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
16:05:55:setup_element:INFO: Eye window for uplink 18: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
16:05:55:setup_element:INFO: Eye window for uplink 19: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
16:05:55:setup_element:INFO: Eye window for uplink 20: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
16:05:55:setup_element:INFO: Eye window for uplink 21: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
16:05:55:setup_element:INFO: Eye window for uplink 22: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
16:05:55:setup_element:INFO: Eye window for uplink 23: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
16:05:55:setup_element:INFO: Eye window for uplink 24: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
16:05:55:setup_element:INFO: Eye window for uplink 25: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
16:05:55:setup_element:INFO: Eye window for uplink 26: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
16:05:55:setup_element:INFO: Eye window for uplink 27: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
16:05:55:setup_element:INFO: Eye window for uplink 28: ______________________________________________________________________XXXXXXX___
Clock Delay: 33
16:05:55:setup_element:INFO: Eye window for uplink 29: ______________________________________________________________________XXXXXXX___
Clock Delay: 33
16:05:55:setup_element:INFO: Eye window for uplink 30: ________________________________________________________________________XXXXXX__
Clock Delay: 34
16:05:55:setup_element:INFO: Eye window for uplink 31: ________________________________________________________________________XXXXXX__
Clock Delay: 34
16:05:55:setup_element:INFO: Setting the clock phase to 33 for group 0, downlink 2
16:05:55:setup_element:INFO: Scanning data phases
16:05:55:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
16:05:56:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
16:06:01:setup_element:INFO: Data phase scan results for group 0, downlink 2
16:06:01:setup_element:INFO: Eye window for uplink 16: __________________________________XXXXX_
Data delay found: 16
16:06:01:setup_element:INFO: Eye window for uplink 17: ______________________________XXXXX_____
Data delay found: 12
16:06:01:setup_element:INFO: Eye window for uplink 18: X_________________________________XXXXXX
Data delay found: 17
16:06:01:setup_element:INFO: Eye window for uplink 19: ________________________________XXXXX___
Data delay found: 14
16:06:01:setup_element:INFO: Eye window for uplink 20: X__________________________________XXXXX
Data delay found: 17
16:06:01:setup_element:INFO: Eye window for uplink 21: _________________________________XXXXXXX
Data delay found: 16
16:06:01:setup_element:INFO: Eye window for uplink 22: __________________________________XXXX__
Data delay found: 15
16:06:01:setup_element:INFO: Eye window for uplink 23: ________________________________XXXXX___
Data delay found: 14
16:06:01:setup_element:INFO: Eye window for uplink 24: ____XXXXXX______________________________
Data delay found: 26
16:06:01:setup_element:INFO: Eye window for uplink 25: ______XXXXXX____________________________
Data delay found: 28
16:06:01:setup_element:INFO: Eye window for uplink 26: ___XXXXX________________________________
Data delay found: 25
16:06:01:setup_element:INFO: Eye window for uplink 27: ______XXXXX_____________________________
Data delay found: 28
16:06:01:setup_element:INFO: Eye window for uplink 28: ________XXXXX___________________________
Data delay found: 30
16:06:01:setup_element:INFO: Eye window for uplink 29: __________XXXXX_________________________
Data delay found: 32
16:06:01:setup_element:INFO: Eye window for uplink 30: ___________XXXXXX_______________________
Data delay found: 33
16:06:01:setup_element:INFO: Eye window for uplink 31: __________XXXXXX________________________
Data delay found: 32
16:06:01:setup_element:INFO: Setting the data phase to 16 for uplink 16
16:06:01:setup_element:INFO: Setting the data phase to 12 for uplink 17
16:06:01:setup_element:INFO: Setting the data phase to 17 for uplink 18
16:06:01:setup_element:INFO: Setting the data phase to 14 for uplink 19
16:06:01:setup_element:INFO: Setting the data phase to 17 for uplink 20
16:06:01:setup_element:INFO: Setting the data phase to 16 for uplink 21
16:06:01:setup_element:INFO: Setting the data phase to 15 for uplink 22
16:06:01:setup_element:INFO: Setting the data phase to 14 for uplink 23
16:06:01:setup_element:INFO: Setting the data phase to 26 for uplink 24
16:06:01:setup_element:INFO: Setting the data phase to 28 for uplink 25
16:06:01:setup_element:INFO: Setting the data phase to 25 for uplink 26
16:06:01:setup_element:INFO: Setting the data phase to 28 for uplink 27
16:06:01:setup_element:INFO: Setting the data phase to 30 for uplink 28
16:06:01:setup_element:INFO: Setting the data phase to 32 for uplink 29
16:06:01:setup_element:INFO: Setting the data phase to 33 for uplink 30
16:06:01:setup_element:INFO: Setting the data phase to 32 for uplink 31
16:06:01:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 33
Window Length: 70
Eye Windows:
Uplink 16: _______________________________________________________________________XXXXXXX__
Uplink 17: _______________________________________________________________________XXXXXXX__
Uplink 18: _______________________________________________________________________XXXXXXX__
Uplink 19: _______________________________________________________________________XXXXXXX__
Uplink 20: _______________________________________________________________________XXXXXXXX_
Uplink 21: _______________________________________________________________________XXXXXXXX_
Uplink 22: ______________________________________________________________________XXXXXXXX__
Uplink 23: ______________________________________________________________________XXXXXXXX__
Uplink 24: _______________________________________________________________________XXXXXXX__
Uplink 25: _______________________________________________________________________XXXXXXX__
Uplink 26: _____________________________________________________________________XXXXXXXX___
Uplink 27: _____________________________________________________________________XXXXXXXX___
Uplink 28: ______________________________________________________________________XXXXXXX___
Uplink 29: ______________________________________________________________________XXXXXXX___
Uplink 30: ________________________________________________________________________XXXXXX__
Uplink 31: ________________________________________________________________________XXXXXX__
Data phase characteristics:
Uplink 16:
Optimal Phase: 16
Window Length: 35
Eye Window: __________________________________XXXXX_
Uplink 17:
Optimal Phase: 12
Window Length: 35
Eye Window: ______________________________XXXXX_____
Uplink 18:
Optimal Phase: 17
Window Length: 33
Eye Window: X_________________________________XXXXXX
Uplink 19:
Optimal Phase: 14
Window Length: 35
Eye Window: ________________________________XXXXX___
Uplink 20:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXXX
Uplink 21:
Optimal Phase: 16
Window Length: 33
Eye Window: _________________________________XXXXXXX
Uplink 22:
Optimal Phase: 15
Window Length: 36
Eye Window: __________________________________XXXX__
Uplink 23:
Optimal Phase: 14
Window Length: 35
Eye Window: ________________________________XXXXX___
Uplink 24:
Optimal Phase: 26
Window Length: 34
Eye Window: ____XXXXXX______________________________
Uplink 25:
Optimal Phase: 28
Window Length: 34
Eye Window: ______XXXXXX____________________________
Uplink 26:
Optimal Phase: 25
Window Length: 35
Eye Window: ___XXXXX________________________________
Uplink 27:
Optimal Phase: 28
Window Length: 35
Eye Window: ______XXXXX_____________________________
Uplink 28:
Optimal Phase: 30
Window Length: 35
Eye Window: ________XXXXX___________________________
Uplink 29:
Optimal Phase: 32
Window Length: 35
Eye Window: __________XXXXX_________________________
Uplink 30:
Optimal Phase: 33
Window Length: 34
Eye Window: ___________XXXXXX_______________________
Uplink 31:
Optimal Phase: 32
Window Length: 34
Eye Window: __________XXXXXX________________________
]
16:06:01:setup_element:INFO: Beginning SMX ASICs map scan
16:06:01:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
16:06:01:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
16:06:01:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
16:06:01:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
16:06:01:uplink:INFO: Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
16:06:01:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 23
16:06:01:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 22
16:06:01:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 30
16:06:01:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 31
16:06:01:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 21
16:06:02:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 20
16:06:02:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28
16:06:02:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 29
16:06:02:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 19
16:06:02:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 18
16:06:02:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26
16:06:02:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 27
16:06:02:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 17
16:06:02:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 16
16:06:02:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 24
16:06:02:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 25
16:06:04:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 23), (1, 22)
ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
ASIC address 0x2: (ASIC uplink, uplink): (0, 21), (1, 20)
ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
ASIC address 0x4: (ASIC uplink, uplink): (0, 19), (1, 18)
ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
ASIC address 0x6: (ASIC uplink, uplink): (0, 17), (1, 16)
ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
Clock Phase Characteristic:
Optimal Phase: 33
Window Length: 70
Eye Windows:
Uplink 16: _______________________________________________________________________XXXXXXX__
Uplink 17: _______________________________________________________________________XXXXXXX__
Uplink 18: _______________________________________________________________________XXXXXXX__
Uplink 19: _______________________________________________________________________XXXXXXX__
Uplink 20: _______________________________________________________________________XXXXXXXX_
Uplink 21: _______________________________________________________________________XXXXXXXX_
Uplink 22: ______________________________________________________________________XXXXXXXX__
Uplink 23: ______________________________________________________________________XXXXXXXX__
Uplink 24: _______________________________________________________________________XXXXXXX__
Uplink 25: _______________________________________________________________________XXXXXXX__
Uplink 26: _____________________________________________________________________XXXXXXXX___
Uplink 27: _____________________________________________________________________XXXXXXXX___
Uplink 28: ______________________________________________________________________XXXXXXX___
Uplink 29: ______________________________________________________________________XXXXXXX___
Uplink 30: ________________________________________________________________________XXXXXX__
Uplink 31: ________________________________________________________________________XXXXXX__
Data phase characteristics:
Uplink 16:
Optimal Phase: 16
Window Length: 35
Eye Window: __________________________________XXXXX_
Uplink 17:
Optimal Phase: 12
Window Length: 35
Eye Window: ______________________________XXXXX_____
Uplink 18:
Optimal Phase: 17
Window Length: 33
Eye Window: X_________________________________XXXXXX
Uplink 19:
Optimal Phase: 14
Window Length: 35
Eye Window: ________________________________XXXXX___
Uplink 20:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXXX
Uplink 21:
Optimal Phase: 16
Window Length: 33
Eye Window: _________________________________XXXXXXX
Uplink 22:
Optimal Phase: 15
Window Length: 36
Eye Window: __________________________________XXXX__
Uplink 23:
Optimal Phase: 14
Window Length: 35
Eye Window: ________________________________XXXXX___
Uplink 24:
Optimal Phase: 26
Window Length: 34
Eye Window: ____XXXXXX______________________________
Uplink 25:
Optimal Phase: 28
Window Length: 34
Eye Window: ______XXXXXX____________________________
Uplink 26:
Optimal Phase: 25
Window Length: 35
Eye Window: ___XXXXX________________________________
Uplink 27:
Optimal Phase: 28
Window Length: 35
Eye Window: ______XXXXX_____________________________
Uplink 28:
Optimal Phase: 30
Window Length: 35
Eye Window: ________XXXXX___________________________
Uplink 29:
Optimal Phase: 32
Window Length: 35
Eye Window: __________XXXXX_________________________
Uplink 30:
Optimal Phase: 33
Window Length: 34
Eye Window: ___________XXXXXX_______________________
Uplink 31:
Optimal Phase: 32
Window Length: 34
Eye Window: __________XXXXXX________________________
16:06:04:setup_element:INFO: Performing Elink synchronization
16:06:04:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
16:06:04:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
16:06:04:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
16:06:04:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
16:06:04:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2
16:06:04:uplink:INFO: Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
16:06:04:ST3_emu:INFO: Number of chips: 8
addr | upli | dwnli | grp | uplinks | uplinks_map
0 | [0] | 2 | 0 | [23] | [(0, 23), (1, 22)]
1 | [0] | 2 | 0 | [30] | [(0, 30), (1, 31)]
2 | [0] | 2 | 0 | [21] | [(0, 21), (1, 20)]
3 | [0] | 2 | 0 | [28] | [(0, 28), (1, 29)]
4 | [0] | 2 | 0 | [19] | [(0, 19), (1, 18)]
5 | [0] | 2 | 0 | [26] | [(0, 26), (1, 27)]
6 | [0] | 2 | 0 | [17] | [(0, 17), (1, 16)]
7 | [0] | 2 | 0 | [24] | [(0, 24), (1, 25)]
16:06:05:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:06:05:febtest:INFO: 0-0 | XA-000-08-002-000-001-221-11 | 47.3 | 1165.6
16:06:06:febtest:INFO: 0-1 | XA-000-08-001-064-050-160-13 | 44.1 | 1189.2
16:06:06:febtest:INFO: 0-2 | XA-000-08-002-000-001-045-13 | 50.4 | 1171.5
16:06:06:febtest:INFO: 0-3 | XA-000-08-001-064-051-128-14 | 53.6 | 1147.8
16:06:06:febtest:INFO: 0-4 | XA-000-08-001-064-051-080-06 | 40.9 | 1195.1
16:06:07:febtest:INFO: 0-5 | XA-000-08-001-064-051-136-14 | 44.1 | 1183.3
16:06:07:febtest:INFO: 0-6 | XA-000-08-001-064-051-088-06 | 40.9 | 1189.2
16:06:07:febtest:INFO: 0-7 | XA-000-08-001-064-051-184-07 | 50.4 | 1159.7
16:06:07:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:06:11:ST3_smx:INFO: chip: 0-0 47.250730 C 1165.571835 mV
16:06:11:ST3_smx:INFO: Electrons
16:06:11:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:06:13:ST3_smx:INFO: ----> Checking Analog response
16:06:13:ST3_smx:INFO: ----> Checking broken channels
16:06:13:ST3_smx:INFO: Total # broken ch: 3
16:06:13:ST3_smx:INFO: List FAST: [12, 66, 121]
16:06:13:ST3_smx:INFO: List SLOW: []
16:06:13:ST3_smx:INFO: Holes
16:06:13:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:06:15:ST3_smx:INFO: ----> Checking Analog response
16:06:15:ST3_smx:INFO: ----> Checking broken channels
16:06:15:ST3_smx:INFO: Total # broken ch: 3
16:06:15:ST3_smx:INFO: List FAST: [12, 66, 121]
16:06:15:ST3_smx:INFO: List SLOW: []
16:06:15:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:06:16:febtest:INFO: 0-0 | XA-000-08-002-000-001-221-11 | 50.4 | 1159.7
16:06:16:febtest:INFO: 0-1 | XA-000-08-001-064-050-160-13 | 44.1 | 1189.2
16:06:16:febtest:INFO: 0-2 | XA-000-08-002-000-001-045-13 | 50.4 | 1171.5
16:06:16:febtest:INFO: 0-3 | XA-000-08-001-064-051-128-14 | 53.6 | 1147.8
16:06:17:febtest:INFO: 0-4 | XA-000-08-001-064-051-080-06 | 40.9 | 1195.1
16:06:17:febtest:INFO: 0-5 | XA-000-08-001-064-051-136-14 | 44.1 | 1183.3
16:06:17:febtest:INFO: 0-6 | XA-000-08-001-064-051-088-06 | 44.1 | 1189.2
16:06:17:febtest:INFO: 0-7 | XA-000-08-001-064-051-184-07 | 50.4 | 1159.7
16:06:18:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:06:21:ST3_smx:INFO: chip: 0-1 47.250730 C 1177.390875 mV
16:06:21:ST3_smx:INFO: Electrons
16:06:21:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:06:23:ST3_smx:INFO: ----> Checking Analog response
16:06:23:ST3_smx:INFO: ----> Checking broken channels
16:06:23:ST3_smx:INFO: Total # broken ch: 3
16:06:23:ST3_smx:INFO: List FAST: [52, 74, 90]
16:06:23:ST3_smx:INFO: List SLOW: []
16:06:23:ST3_smx:INFO: Holes
16:06:23:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:06:25:ST3_smx:INFO: ----> Checking Analog response
16:06:25:ST3_smx:INFO: ----> Checking broken channels
16:06:26:ST3_smx:INFO: Total # broken ch: 3
16:06:26:ST3_smx:INFO: List FAST: [52, 74, 90]
16:06:26:ST3_smx:INFO: List SLOW: []
16:06:26:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:06:26:febtest:INFO: 0-0 | XA-000-08-002-000-001-221-11 | 50.4 | 1159.7
16:06:26:febtest:INFO: 0-1 | XA-000-08-001-064-050-160-13 | 50.4 | 1171.5
16:06:26:febtest:INFO: 0-2 | XA-000-08-002-000-001-045-13 | 47.3 | 1171.5
16:06:27:febtest:INFO: 0-3 | XA-000-08-001-064-051-128-14 | 53.6 | 1147.8
16:06:27:febtest:INFO: 0-4 | XA-000-08-001-064-051-080-06 | 40.9 | 1195.1
16:06:27:febtest:INFO: 0-5 | XA-000-08-001-064-051-136-14 | 44.1 | 1183.3
16:06:27:febtest:INFO: 0-6 | XA-000-08-001-064-051-088-06 | 44.1 | 1189.2
16:06:27:febtest:INFO: 0-7 | XA-000-08-001-064-051-184-07 | 50.4 | 1165.6
16:06:28:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:06:31:ST3_smx:INFO: chip: 0-2 59.984250 C 1135.937260 mV
16:06:31:ST3_smx:INFO: Electrons
16:06:31:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:06:33:ST3_smx:INFO: ----> Checking Analog response
16:06:33:ST3_smx:INFO: ----> Checking broken channels
16:06:33:ST3_smx:INFO: Total # broken ch: 3
16:06:33:ST3_smx:INFO: List FAST: [26, 43, 117]
16:06:33:ST3_smx:INFO: List SLOW: []
16:06:33:ST3_smx:INFO: Holes
16:06:33:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:06:35:ST3_smx:INFO: ----> Checking Analog response
16:06:35:ST3_smx:INFO: ----> Checking broken channels
16:06:36:ST3_smx:INFO: Total # broken ch: 3
16:06:36:ST3_smx:INFO: List FAST: [26, 43, 117]
16:06:36:ST3_smx:INFO: List SLOW: []
16:06:36:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:06:36:febtest:INFO: 0-0 | XA-000-08-002-000-001-221-11 | 50.4 | 1159.7
16:06:36:febtest:INFO: 0-1 | XA-000-08-001-064-050-160-13 | 50.4 | 1171.5
16:06:36:febtest:INFO: 0-2 | XA-000-08-002-000-001-045-13 | 60.0 | 1130.0
16:06:37:febtest:INFO: 0-3 | XA-000-08-001-064-051-128-14 | 53.6 | 1147.8
16:06:37:febtest:INFO: 0-4 | XA-000-08-001-064-051-080-06 | 44.1 | 1195.1
16:06:37:febtest:INFO: 0-5 | XA-000-08-001-064-051-136-14 | 44.1 | 1183.3
16:06:37:febtest:INFO: 0-6 | XA-000-08-001-064-051-088-06 | 44.1 | 1189.2
16:06:37:febtest:INFO: 0-7 | XA-000-08-001-064-051-184-07 | 50.4 | 1159.7
16:06:38:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:06:41:ST3_smx:INFO: chip: 0-3 53.612520 C 1153.732915 mV
16:06:41:ST3_smx:INFO: Electrons
16:06:41:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:06:43:ST3_smx:INFO: ----> Checking Analog response
16:06:43:ST3_smx:INFO: ----> Checking broken channels
16:06:44:ST3_smx:INFO: Total # broken ch: 2
16:06:44:ST3_smx:INFO: List FAST: [5, 40]
16:06:44:ST3_smx:INFO: List SLOW: []
16:06:44:ST3_smx:INFO: Holes
16:06:44:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:06:45:ST3_smx:INFO: ----> Checking Analog response
16:06:45:ST3_smx:INFO: ----> Checking broken channels
16:06:46:ST3_smx:INFO: Total # broken ch: 2
16:06:46:ST3_smx:INFO: List FAST: [5, 40]
16:06:46:ST3_smx:INFO: List SLOW: []
16:06:46:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:06:46:febtest:INFO: 0-0 | XA-000-08-002-000-001-221-11 | 50.4 | 1159.7
16:06:46:febtest:INFO: 0-1 | XA-000-08-001-064-050-160-13 | 50.4 | 1177.4
16:06:46:febtest:INFO: 0-2 | XA-000-08-002-000-001-045-13 | 60.0 | 1130.0
16:06:47:febtest:INFO: 0-3 | XA-000-08-001-064-051-128-14 | 56.8 | 1147.8
16:06:47:febtest:INFO: 0-4 | XA-000-08-001-064-051-080-06 | 40.9 | 1195.1
16:06:47:febtest:INFO: 0-5 | XA-000-08-001-064-051-136-14 | 44.1 | 1183.3
16:06:47:febtest:INFO: 0-6 | XA-000-08-001-064-051-088-06 | 44.1 | 1189.2
16:06:47:febtest:INFO: 0-7 | XA-000-08-001-064-051-184-07 | 50.4 | 1165.6
16:06:48:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:06:51:ST3_smx:INFO: chip: 0-4 53.612520 C 1159.654860 mV
16:06:51:ST3_smx:INFO: Electrons
16:06:51:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:06:53:ST3_smx:INFO: ----> Checking Analog response
16:06:53:ST3_smx:INFO: ----> Checking broken channels
16:06:54:ST3_smx:INFO: Total # broken ch: 6
16:06:54:ST3_smx:INFO: List FAST: [1, 5, 33, 41, 53, 56]
16:06:54:ST3_smx:INFO: List SLOW: []
16:06:54:ST3_smx:INFO: Holes
16:06:54:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:06:56:ST3_smx:INFO: ----> Checking Analog response
16:06:56:ST3_smx:INFO: ----> Checking broken channels
16:06:56:ST3_smx:INFO: Total # broken ch: 6
16:06:56:ST3_smx:INFO: List FAST: [1, 5, 33, 41, 53, 56]
16:06:56:ST3_smx:INFO: List SLOW: []
16:06:56:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:06:56:febtest:INFO: 0-0 | XA-000-08-002-000-001-221-11 | 50.4 | 1165.6
16:06:56:febtest:INFO: 0-1 | XA-000-08-001-064-050-160-13 | 50.4 | 1177.4
16:06:57:febtest:INFO: 0-2 | XA-000-08-002-000-001-045-13 | 60.0 | 1130.0
16:06:57:febtest:INFO: 0-3 | XA-000-08-001-064-051-128-14 | 56.8 | 1147.8
16:06:57:febtest:INFO: 0-4 | XA-000-08-001-064-051-080-06 | 53.6 | 1159.7
16:06:57:febtest:INFO: 0-5 | XA-000-08-001-064-051-136-14 | 44.1 | 1183.3
16:06:58:febtest:INFO: 0-6 | XA-000-08-001-064-051-088-06 | 44.1 | 1189.2
16:06:58:febtest:INFO: 0-7 | XA-000-08-001-064-051-184-07 | 53.6 | 1165.6
16:06:58:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:07:02:ST3_smx:INFO: chip: 0-5 47.250730 C 1171.483840 mV
16:07:02:ST3_smx:INFO: Electrons
16:07:02:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:07:04:ST3_smx:INFO: ----> Checking Analog response
16:07:04:ST3_smx:INFO: ----> Checking broken channels
16:07:04:ST3_smx:INFO: Total # broken ch: 2
16:07:04:ST3_smx:INFO: List FAST: [26, 102]
16:07:04:ST3_smx:INFO: List SLOW: []
16:07:04:ST3_smx:INFO: Holes
16:07:04:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:07:06:ST3_smx:INFO: ----> Checking Analog response
16:07:06:ST3_smx:INFO: ----> Checking broken channels
16:07:06:ST3_smx:INFO: Total # broken ch: 2
16:07:06:ST3_smx:INFO: List FAST: [26, 102]
16:07:06:ST3_smx:INFO: List SLOW: []
16:07:06:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:07:06:febtest:INFO: 0-0 | XA-000-08-002-000-001-221-11 | 50.4 | 1165.6
16:07:07:febtest:INFO: 0-1 | XA-000-08-001-064-050-160-13 | 50.4 | 1177.4
16:07:07:febtest:INFO: 0-2 | XA-000-08-002-000-001-045-13 | 60.0 | 1130.0
16:07:07:febtest:INFO: 0-3 | XA-000-08-001-064-051-128-14 | 56.8 | 1153.7
16:07:07:febtest:INFO: 0-4 | XA-000-08-001-064-051-080-06 | 53.6 | 1159.7
16:07:07:febtest:INFO: 0-5 | XA-000-08-001-064-051-136-14 | 50.4 | 1171.5
16:07:08:febtest:INFO: 0-6 | XA-000-08-001-064-051-088-06 | 44.1 | 1189.2
16:07:08:febtest:INFO: 0-7 | XA-000-08-001-064-051-184-07 | 50.4 | 1165.6
16:07:08:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:07:12:ST3_smx:INFO: chip: 0-6 53.612520 C 1159.654860 mV
16:07:12:ST3_smx:INFO: Electrons
16:07:12:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:07:14:ST3_smx:INFO: ----> Checking Analog response
16:07:14:ST3_smx:INFO: ----> Checking broken channels
16:07:14:ST3_smx:INFO: Total # broken ch: 4
16:07:14:ST3_smx:INFO: List FAST: [1, 74, 89]
16:07:14:ST3_smx:INFO: List SLOW: [1]
16:07:14:ST3_smx:INFO: Holes
16:07:14:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:07:16:ST3_smx:INFO: ----> Checking Analog response
16:07:16:ST3_smx:INFO: ----> Checking broken channels
16:07:16:ST3_smx:INFO: Total # broken ch: 4
16:07:16:ST3_smx:INFO: List FAST: [1, 74, 89]
16:07:16:ST3_smx:INFO: List SLOW: [1]
16:07:16:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:07:17:febtest:INFO: 0-0 | XA-000-08-002-000-001-221-11 | 50.4 | 1159.7
16:07:17:febtest:INFO: 0-1 | XA-000-08-001-064-050-160-13 | 50.4 | 1177.4
16:07:17:febtest:INFO: 0-2 | XA-000-08-002-000-001-045-13 | 60.0 | 1135.9
16:07:17:febtest:INFO: 0-3 | XA-000-08-001-064-051-128-14 | 56.8 | 1153.7
16:07:17:febtest:INFO: 0-4 | XA-000-08-001-064-051-080-06 | 53.6 | 1159.7
16:07:18:febtest:INFO: 0-5 | XA-000-08-001-064-051-136-14 | 50.4 | 1165.6
16:07:18:febtest:INFO: 0-6 | XA-000-08-001-064-051-088-06 | 53.6 | 1153.7
16:07:18:febtest:INFO: 0-7 | XA-000-08-001-064-051-184-07 | 50.4 | 1165.6
16:07:18:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:07:22:ST3_smx:INFO: chip: 0-7 50.430383 C 1171.483840 mV
16:07:22:ST3_smx:INFO: Electrons
16:07:22:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:07:24:ST3_smx:INFO: ----> Checking Analog response
16:07:24:ST3_smx:INFO: ----> Checking broken channels
16:07:24:ST3_smx:INFO: Total # broken ch: 1
16:07:24:ST3_smx:INFO: List FAST: [96]
16:07:24:ST3_smx:INFO: List SLOW: []
16:07:24:ST3_smx:INFO: Holes
16:07:24:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:07:26:ST3_smx:INFO: ----> Checking Analog response
16:07:26:ST3_smx:INFO: ----> Checking broken channels
16:07:27:ST3_smx:INFO: Total # broken ch: 1
16:07:27:ST3_smx:INFO: List FAST: [96]
16:07:27:ST3_smx:INFO: List SLOW: []
16:07:27:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:07:27:febtest:INFO: 0-0 | XA-000-08-002-000-001-221-11 | 50.4 | 1165.6
16:07:27:febtest:INFO: 0-1 | XA-000-08-001-064-050-160-13 | 50.4 | 1177.4
16:07:27:febtest:INFO: 0-2 | XA-000-08-002-000-001-045-13 | 60.0 | 1135.9
16:07:28:febtest:INFO: 0-3 | XA-000-08-001-064-051-128-14 | 56.8 | 1153.7
16:07:28:febtest:INFO: 0-4 | XA-000-08-001-064-051-080-06 | 53.6 | 1159.7
16:07:28:febtest:INFO: 0-5 | XA-000-08-001-064-051-136-14 | 50.4 | 1171.5
16:07:28:febtest:INFO: 0-6 | XA-000-08-001-064-051-088-06 | 53.6 | 1153.7
16:07:29:febtest:INFO: 0-7 | XA-000-08-001-064-051-184-07 | 53.6 | 1165.6
############################################################
# S U M M A R Y #
############################################################
{'TEST_NAME': 'FEB-ASIC', 'TEST_DATE': '2023_11_20-16_05_53', 'OPERATOR': 'Alois Alzheimer', 'PROJECT': 'Production', 'SITE': 'GSI', 'SETUP': 'GSI_TEST_SETUP_1', 'ASIC_ID': 'XA-000-08-001-064-051-184-07', 'FUSED_ID': 6359364698915421063, 'HW_ADDR': 7, 'UPLINK': 24, 'VERS_NO': '2.2', 'CABLE_SET_ID': '', 'IC_TEMP': '0', 'VDDM': '0', 'AUX': '0', 'CSABIAS': '0', 'VDDM_INT': '0', 'ADC_Chi2': 0.0, 'ADC_NDF': 0, 'ADC_P0': 0.0, 'ADC_P1': 0.006824, 'ADC_P2': -2.485e-06, 'ADC_P0err': 0.001, 'ADC_P1err': 0.001, 'ADC_P2err': 1e-05, 'ADC_VREF_P': 58, 'ADC_VREF_N': 30, 'ADC_VREF_T': 128, 'ADC_VREF_TR': 122, 'THR2_GLB': 30, 'LOOP__PLS': 100, 'CALIB_PLS': 250, 'SnsLoop': 5, 'IFED': 31, 'CSA_BIAS': 15, 'CSA_Chi2': 0.0, 'CSA_NDF': 0, 'CSA_P0': 0.0, 'CSA_P1': 0.0, 'CSA_P2': 0.0, 'CSA_P0err': 0.0, 'CSA_P1err': 0.0, 'CSA_P2err': 0.0, 'CONF_FAIL_REG': 0, 'N_BROKEN_DISC': 1, 'N_BROKEN_FAST': '[96]', 'N_BROKEN_SLOW': '[]', 'P_BROKEN_DISC': 1, 'P_BROKEN_FAST': '[96]', 'P_BROKEN_SLOW': '[]', 'ASIC_QA_category': '', 'N_BROKEN_CABLE': 0, 'LIST_OF_BROKEN_CABLES': 0, 'ADDR_0': '', 'ADDR_1': '', 'ADDR_2': '', 'ADDR_3': '', 'ADDR_4': '', 'ADDR_5': '', 'ADDR_6': '', 'ADDR_7': '', 'SENSOR_ID': '', 'MODULE_NAME': '', 'MODULE_LADDER': '', 'MODULE_MODULE': '', 'MODULE_SIZE': '', 'MODULE_GRADE': '', 'MODULE_TYPE': '', 'VI_bInit': ['2.447', '1.8670', '1.845', '2.9430', '7.001', '1.5580', '7.001', '1.5580'], 'VI_aInit': ['0', '0', '0', '0', '0', '0'], 'VI_atEnd': ['0', '0', '0', '0', '0', '0'], 'AMP_CAL': 125, 'PlsLoop': 3, 'N_ANA_PRESENT': 'Analog response OK', 'N_DISC_FAIL_CH': 0, 'N_ANA_FAIL_CH': '0', 'P_ANA_PRESENT': 'Analog response OK', 'P_DISC_FAIL_CH': 0, 'P_ANA_FAIL_CH': '0'}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-ASIC
TEST_DATE : 2023_11_20-16_05_53
OPERATOR : Alois Alzheimer
SITE : GSI
SETUP : GSI_TEST_SETUP_1
Set-ID :
---------------------------------------
MODULE_NAME
---------------------------------------
VI_before_Init : ['2.447', '1.8670', '1.845', '2.9430', '7.001', '1.5580', '7.001', '1.5580']
VI_after__Init : ['2.450', '2.0240', '1.850', '0.3299', '7.000', '1.5520', '7.000', '1.5520']
VI_at__the_End : ['2.450', '2.0240', '1.850', '0.3299', '7.000', '1.5520', '7.000', '1.5520']
16:07:39:ST3_Shared:INFO: /home/cbm/public_html/Production_LogDir//FEB/FEB_2027/TestDate_2023_11_20-16_05_53/