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FEB_2027 20.11.23 15:50:22
Info
15:50:18:ST3_hmp4040:INFO: HAMEG,HMP2030,017836163,HW50010002/SW2.30
15:50:19:febtest:INFO: FEB8.2 selected
15:50:19:smx_tester:INFO: Setting Elink clock mode to 160 MHz
15:50:22:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
15:50:22:ST3_Shared:INFO: --------------------------FEB-ASIC--------------------------
15:50:22:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
15:50:23:febtest:INFO: Tsting FEB with SN 2027
15:50:24:smx_tester:INFO: Scanning setup
15:50:24:elinks:INFO: Disabling clock on downlink 0
15:50:24:elinks:INFO: Disabling clock on downlink 1
15:50:24:elinks:INFO: Disabling clock on downlink 2
15:50:24:elinks:INFO: Disabling clock on downlink 3
15:50:24:elinks:INFO: Disabling clock on downlink 4
15:50:24:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:50:24:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
15:50:24:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:50:24:elinks:INFO: Disabling clock on downlink 0
15:50:24:elinks:INFO: Disabling clock on downlink 1
15:50:24:elinks:INFO: Disabling clock on downlink 2
15:50:24:elinks:INFO: Disabling clock on downlink 3
15:50:24:elinks:INFO: Disabling clock on downlink 4
15:50:24:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:50:24:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
15:50:24:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:50:24:elinks:INFO: Disabling clock on downlink 0
15:50:24:elinks:INFO: Disabling clock on downlink 1
15:50:24:elinks:INFO: Disabling clock on downlink 2
15:50:24:elinks:INFO: Disabling clock on downlink 3
15:50:24:elinks:INFO: Disabling clock on downlink 4
15:50:24:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:50:24:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:50:25:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 16
15:50:25:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 17
15:50:25:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 18
15:50:25:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 19
15:50:25:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 20
15:50:25:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 21
15:50:25:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 22
15:50:25:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 23
15:50:25:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24
15:50:25:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25
15:50:25:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26
15:50:25:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27
15:50:25:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28
15:50:25:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29
15:50:25:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30
15:50:25:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31
15:50:25:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:50:25:elinks:INFO: Disabling clock on downlink 0
15:50:25:elinks:INFO: Disabling clock on downlink 1
15:50:25:elinks:INFO: Disabling clock on downlink 2
15:50:25:elinks:INFO: Disabling clock on downlink 3
15:50:25:elinks:INFO: Disabling clock on downlink 4
15:50:25:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:50:25:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
15:50:25:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:50:25:elinks:INFO: Disabling clock on downlink 0
15:50:25:elinks:INFO: Disabling clock on downlink 1
15:50:25:elinks:INFO: Disabling clock on downlink 2
15:50:25:elinks:INFO: Disabling clock on downlink 3
15:50:25:elinks:INFO: Disabling clock on downlink 4
15:50:25:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:50:25:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
15:50:25:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:50:25:setup_element:INFO: Scanning clock phase
15:50:25:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:50:25:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
15:50:25:setup_element:INFO: Clock phase scan results for group 0, downlink 2
15:50:25:setup_element:INFO: Eye window for uplink 16: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
15:50:25:setup_element:INFO: Eye window for uplink 17: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
15:50:25:setup_element:INFO: Eye window for uplink 18: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
15:50:25:setup_element:INFO: Eye window for uplink 19: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
15:50:25:setup_element:INFO: Eye window for uplink 20: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
15:50:25:setup_element:INFO: Eye window for uplink 21: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
15:50:25:setup_element:INFO: Eye window for uplink 22: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
15:50:25:setup_element:INFO: Eye window for uplink 23: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
15:50:25:setup_element:INFO: Eye window for uplink 24: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
15:50:25:setup_element:INFO: Eye window for uplink 25: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
15:50:25:setup_element:INFO: Eye window for uplink 26: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
15:50:25:setup_element:INFO: Eye window for uplink 27: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
15:50:25:setup_element:INFO: Eye window for uplink 28: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
15:50:25:setup_element:INFO: Eye window for uplink 29: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
15:50:25:setup_element:INFO: Eye window for uplink 30: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
15:50:25:setup_element:INFO: Eye window for uplink 31: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
15:50:25:setup_element:INFO: Setting the clock phase to 33 for group 0, downlink 2
15:50:25:setup_element:INFO: Scanning data phases
15:50:25:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:50:25:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
15:50:31:setup_element:INFO: Data phase scan results for group 0, downlink 2
15:50:31:setup_element:INFO: Eye window for uplink 16: ___________________________________XXXX_
Data delay found: 16
15:50:31:setup_element:INFO: Eye window for uplink 17: _______________________________XXXX_____
Data delay found: 12
15:50:31:setup_element:INFO: Eye window for uplink 18: X_________________________________XXXXXX
Data delay found: 17
15:50:31:setup_element:INFO: Eye window for uplink 19: ________________________________XXXXX___
Data delay found: 14
15:50:31:setup_element:INFO: Eye window for uplink 20: X__________________________________XXXXX
Data delay found: 17
15:50:31:setup_element:INFO: Eye window for uplink 21: __________________________________XXXXXX
Data delay found: 16
15:50:31:setup_element:INFO: Eye window for uplink 22: __________________________________XXXX__
Data delay found: 15
15:50:31:setup_element:INFO: Eye window for uplink 23: ________________________________XXXX____
Data delay found: 13
15:50:31:setup_element:INFO: Eye window for uplink 24: ____XXXXX_______________________________
Data delay found: 26
15:50:31:setup_element:INFO: Eye window for uplink 25: ______XXXXXX____________________________
Data delay found: 28
15:50:31:setup_element:INFO: Eye window for uplink 26: __XXXXXX________________________________
Data delay found: 24
15:50:31:setup_element:INFO: Eye window for uplink 27: ______XXXXXX____________________________
Data delay found: 28
15:50:31:setup_element:INFO: Eye window for uplink 28: _________XXXXX__________________________
Data delay found: 31
15:50:31:setup_element:INFO: Eye window for uplink 29: ___________XXXXX________________________
Data delay found: 33
15:50:31:setup_element:INFO: Eye window for uplink 30: ____________XXXXXX______________________
Data delay found: 34
15:50:31:setup_element:INFO: Eye window for uplink 31: ___________XXXXXX_______________________
Data delay found: 33
15:50:31:setup_element:INFO: Setting the data phase to 16 for uplink 16
15:50:31:setup_element:INFO: Setting the data phase to 12 for uplink 17
15:50:31:setup_element:INFO: Setting the data phase to 17 for uplink 18
15:50:31:setup_element:INFO: Setting the data phase to 14 for uplink 19
15:50:31:setup_element:INFO: Setting the data phase to 17 for uplink 20
15:50:31:setup_element:INFO: Setting the data phase to 16 for uplink 21
15:50:31:setup_element:INFO: Setting the data phase to 15 for uplink 22
15:50:31:setup_element:INFO: Setting the data phase to 13 for uplink 23
15:50:31:setup_element:INFO: Setting the data phase to 26 for uplink 24
15:50:31:setup_element:INFO: Setting the data phase to 28 for uplink 25
15:50:31:setup_element:INFO: Setting the data phase to 24 for uplink 26
15:50:31:setup_element:INFO: Setting the data phase to 28 for uplink 27
15:50:31:setup_element:INFO: Setting the data phase to 31 for uplink 28
15:50:31:setup_element:INFO: Setting the data phase to 33 for uplink 29
15:50:31:setup_element:INFO: Setting the data phase to 34 for uplink 30
15:50:31:setup_element:INFO: Setting the data phase to 33 for uplink 31
15:50:31:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 33
Window Length: 70
Eye Windows:
Uplink 16: _______________________________________________________________________XXXXXXX__
Uplink 17: _______________________________________________________________________XXXXXXX__
Uplink 18: _______________________________________________________________________XXXXXXX__
Uplink 19: _______________________________________________________________________XXXXXXX__
Uplink 20: _______________________________________________________________________XXXXXXXX_
Uplink 21: _______________________________________________________________________XXXXXXXX_
Uplink 22: ______________________________________________________________________XXXXXXXX__
Uplink 23: ______________________________________________________________________XXXXXXXX__
Uplink 24: _______________________________________________________________________XXXXXXXX_
Uplink 25: _______________________________________________________________________XXXXXXXX_
Uplink 26: _____________________________________________________________________XXXXXXXX___
Uplink 27: _____________________________________________________________________XXXXXXXX___
Uplink 28: ______________________________________________________________________XXXXXXXX__
Uplink 29: ______________________________________________________________________XXXXXXXX__
Uplink 30: _______________________________________________________________________XXXXXXX__
Uplink 31: _______________________________________________________________________XXXXXXX__
Data phase characteristics:
Uplink 16:
Optimal Phase: 16
Window Length: 36
Eye Window: ___________________________________XXXX_
Uplink 17:
Optimal Phase: 12
Window Length: 36
Eye Window: _______________________________XXXX_____
Uplink 18:
Optimal Phase: 17
Window Length: 33
Eye Window: X_________________________________XXXXXX
Uplink 19:
Optimal Phase: 14
Window Length: 35
Eye Window: ________________________________XXXXX___
Uplink 20:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXXX
Uplink 21:
Optimal Phase: 16
Window Length: 34
Eye Window: __________________________________XXXXXX
Uplink 22:
Optimal Phase: 15
Window Length: 36
Eye Window: __________________________________XXXX__
Uplink 23:
Optimal Phase: 13
Window Length: 36
Eye Window: ________________________________XXXX____
Uplink 24:
Optimal Phase: 26
Window Length: 35
Eye Window: ____XXXXX_______________________________
Uplink 25:
Optimal Phase: 28
Window Length: 34
Eye Window: ______XXXXXX____________________________
Uplink 26:
Optimal Phase: 24
Window Length: 34
Eye Window: __XXXXXX________________________________
Uplink 27:
Optimal Phase: 28
Window Length: 34
Eye Window: ______XXXXXX____________________________
Uplink 28:
Optimal Phase: 31
Window Length: 35
Eye Window: _________XXXXX__________________________
Uplink 29:
Optimal Phase: 33
Window Length: 35
Eye Window: ___________XXXXX________________________
Uplink 30:
Optimal Phase: 34
Window Length: 34
Eye Window: ____________XXXXXX______________________
Uplink 31:
Optimal Phase: 33
Window Length: 34
Eye Window: ___________XXXXXX_______________________
]
15:50:31:setup_element:INFO: Beginning SMX ASICs map scan
15:50:31:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:50:31:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
15:50:31:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
15:50:31:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
15:50:31:uplink:INFO: Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
15:50:31:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 23
15:50:31:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 22
15:50:31:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 30
15:50:31:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 31
15:50:31:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 21
15:50:31:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 20
15:50:32:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28
15:50:32:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 29
15:50:32:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 19
15:50:32:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 18
15:50:32:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26
15:50:32:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 27
15:50:32:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 17
15:50:32:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 16
15:50:32:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 24
15:50:32:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 25
15:50:34:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 23), (1, 22)
ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
ASIC address 0x2: (ASIC uplink, uplink): (0, 21), (1, 20)
ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
ASIC address 0x4: (ASIC uplink, uplink): (0, 19), (1, 18)
ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
ASIC address 0x6: (ASIC uplink, uplink): (0, 17), (1, 16)
ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
Clock Phase Characteristic:
Optimal Phase: 33
Window Length: 70
Eye Windows:
Uplink 16: _______________________________________________________________________XXXXXXX__
Uplink 17: _______________________________________________________________________XXXXXXX__
Uplink 18: _______________________________________________________________________XXXXXXX__
Uplink 19: _______________________________________________________________________XXXXXXX__
Uplink 20: _______________________________________________________________________XXXXXXXX_
Uplink 21: _______________________________________________________________________XXXXXXXX_
Uplink 22: ______________________________________________________________________XXXXXXXX__
Uplink 23: ______________________________________________________________________XXXXXXXX__
Uplink 24: _______________________________________________________________________XXXXXXXX_
Uplink 25: _______________________________________________________________________XXXXXXXX_
Uplink 26: _____________________________________________________________________XXXXXXXX___
Uplink 27: _____________________________________________________________________XXXXXXXX___
Uplink 28: ______________________________________________________________________XXXXXXXX__
Uplink 29: ______________________________________________________________________XXXXXXXX__
Uplink 30: _______________________________________________________________________XXXXXXX__
Uplink 31: _______________________________________________________________________XXXXXXX__
Data phase characteristics:
Uplink 16:
Optimal Phase: 16
Window Length: 36
Eye Window: ___________________________________XXXX_
Uplink 17:
Optimal Phase: 12
Window Length: 36
Eye Window: _______________________________XXXX_____
Uplink 18:
Optimal Phase: 17
Window Length: 33
Eye Window: X_________________________________XXXXXX
Uplink 19:
Optimal Phase: 14
Window Length: 35
Eye Window: ________________________________XXXXX___
Uplink 20:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXXX
Uplink 21:
Optimal Phase: 16
Window Length: 34
Eye Window: __________________________________XXXXXX
Uplink 22:
Optimal Phase: 15
Window Length: 36
Eye Window: __________________________________XXXX__
Uplink 23:
Optimal Phase: 13
Window Length: 36
Eye Window: ________________________________XXXX____
Uplink 24:
Optimal Phase: 26
Window Length: 35
Eye Window: ____XXXXX_______________________________
Uplink 25:
Optimal Phase: 28
Window Length: 34
Eye Window: ______XXXXXX____________________________
Uplink 26:
Optimal Phase: 24
Window Length: 34
Eye Window: __XXXXXX________________________________
Uplink 27:
Optimal Phase: 28
Window Length: 34
Eye Window: ______XXXXXX____________________________
Uplink 28:
Optimal Phase: 31
Window Length: 35
Eye Window: _________XXXXX__________________________
Uplink 29:
Optimal Phase: 33
Window Length: 35
Eye Window: ___________XXXXX________________________
Uplink 30:
Optimal Phase: 34
Window Length: 34
Eye Window: ____________XXXXXX______________________
Uplink 31:
Optimal Phase: 33
Window Length: 34
Eye Window: ___________XXXXXX_______________________
15:50:34:setup_element:INFO: Performing Elink synchronization
15:50:34:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:50:34:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
15:50:34:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
15:50:34:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
15:50:34:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2
15:50:34:uplink:INFO: Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
15:50:34:ST3_emu:INFO: Number of chips: 8
addr | upli | dwnli | grp | uplinks | uplinks_map
0 | [0] | 2 | 0 | [23] | [(0, 23), (1, 22)]
1 | [0] | 2 | 0 | [30] | [(0, 30), (1, 31)]
2 | [0] | 2 | 0 | [21] | [(0, 21), (1, 20)]
3 | [0] | 2 | 0 | [28] | [(0, 28), (1, 29)]
4 | [0] | 2 | 0 | [19] | [(0, 19), (1, 18)]
5 | [0] | 2 | 0 | [26] | [(0, 26), (1, 27)]
6 | [0] | 2 | 0 | [17] | [(0, 17), (1, 16)]
7 | [0] | 2 | 0 | [24] | [(0, 24), (1, 25)]
15:50:35:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:50:35:febtest:INFO: 0-0 | XA-000-08-002-000-001-221-11 | 47.3 | 1171.5
15:50:36:febtest:INFO: 0-1 | XA-000-08-001-064-050-160-13 | 40.9 | 1201.0
15:50:36:febtest:INFO: 0-2 | XA-000-08-002-000-001-045-13 | 47.3 | 1171.5
15:50:36:febtest:INFO: 0-3 | XA-000-08-001-064-051-128-14 | 56.8 | 1141.9
15:50:36:febtest:INFO: 0-4 | XA-000-08-001-064-051-080-06 | 40.9 | 1201.0
15:50:36:febtest:INFO: 0-5 | XA-000-08-001-064-051-136-14 | 44.1 | 1177.4
15:50:37:febtest:INFO: 0-6 | XA-000-08-001-064-051-088-06 | 40.9 | 1195.1
15:50:37:febtest:INFO: 0-7 | XA-000-08-001-064-051-184-07 | 50.4 | 1159.7
15:50:37:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:50:41:ST3_smx:INFO: chip: 0-0 47.250730 C 1165.571835 mV
15:50:41:ST3_smx:INFO: Electrons
15:50:41:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
15:50:43:ST3_smx:INFO: ----> Checking Analog response
15:50:43:ST3_smx:INFO: ----> Checking broken channels
15:50:43:ST3_smx:INFO: Total # broken ch: 4
15:50:43:ST3_smx:INFO: List FAST: [9, 69, 71, 89]
15:50:43:ST3_smx:INFO: List SLOW: []
15:50:43:ST3_smx:INFO: Holes
15:50:43:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
15:50:45:ST3_smx:INFO: ----> Checking Analog response
15:50:45:ST3_smx:INFO: ----> Checking broken channels
15:50:45:ST3_smx:INFO: Total # broken ch: 4
15:50:45:ST3_smx:INFO: List FAST: [9, 69, 71, 89]
15:50:45:ST3_smx:INFO: List SLOW: []
15:50:45:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:50:46:febtest:INFO: 0-0 | XA-000-08-002-000-001-221-11 | 50.4 | 1159.7
15:50:46:febtest:INFO: 0-1 | XA-000-08-001-064-050-160-13 | 40.9 | 1201.0
15:50:46:febtest:INFO: 0-2 | XA-000-08-002-000-001-045-13 | 47.3 | 1171.5
15:50:46:febtest:INFO: 0-3 | XA-000-08-001-064-051-128-14 | 56.8 | 1141.9
15:50:47:febtest:INFO: 0-4 | XA-000-08-001-064-051-080-06 | 40.9 | 1201.0
15:50:47:febtest:INFO: 0-5 | XA-000-08-001-064-051-136-14 | 44.1 | 1183.3
15:50:47:febtest:INFO: 0-6 | XA-000-08-001-064-051-088-06 | 40.9 | 1195.1
15:50:47:febtest:INFO: 0-7 | XA-000-08-001-064-051-184-07 | 50.4 | 1159.7
15:50:48:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:50:51:ST3_smx:INFO: chip: 0-1 47.250730 C 1177.390875 mV
15:50:51:ST3_smx:INFO: Electrons
15:50:51:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
15:50:53:ST3_smx:INFO: ----> Checking Analog response
15:50:53:ST3_smx:INFO: ----> Checking broken channels
15:50:54:ST3_smx:INFO: Total # broken ch: 3
15:50:54:ST3_smx:INFO: List FAST: [102, 110, 126]
15:50:54:ST3_smx:INFO: List SLOW: []
15:50:54:ST3_smx:INFO: Holes
15:50:54:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
15:50:56:ST3_smx:INFO: ----> Checking Analog response
15:50:56:ST3_smx:INFO: ----> Checking broken channels
15:50:56:ST3_smx:INFO: Total # broken ch: 3
15:50:56:ST3_smx:INFO: List FAST: [102, 110, 126]
15:50:56:ST3_smx:INFO: List SLOW: []
15:50:56:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:50:56:febtest:INFO: 0-0 | XA-000-08-002-000-001-221-11 | 50.4 | 1165.6
15:50:56:febtest:INFO: 0-1 | XA-000-08-001-064-050-160-13 | 50.4 | 1171.5
15:50:57:febtest:INFO: 0-2 | XA-000-08-002-000-001-045-13 | 47.3 | 1171.5
15:50:57:febtest:INFO: 0-3 | XA-000-08-001-064-051-128-14 | 56.8 | 1147.8
15:50:57:febtest:INFO: 0-4 | XA-000-08-001-064-051-080-06 | 40.9 | 1201.0
15:50:57:febtest:INFO: 0-5 | XA-000-08-001-064-051-136-14 | 44.1 | 1183.3
15:50:57:febtest:INFO: 0-6 | XA-000-08-001-064-051-088-06 | 40.9 | 1195.1
15:50:58:febtest:INFO: 0-7 | XA-000-08-001-064-051-184-07 | 50.4 | 1165.6
15:50:58:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:51:02:ST3_smx:INFO: chip: 0-2 59.984250 C 1135.937260 mV
15:51:02:ST3_smx:INFO: Electrons
15:51:02:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
15:51:04:ST3_smx:INFO: ----> Checking Analog response
15:51:04:ST3_smx:INFO: ----> Checking broken channels
15:51:04:ST3_smx:INFO: Total # broken ch: 2
15:51:04:ST3_smx:INFO: List FAST: [68, 96]
15:51:04:ST3_smx:INFO: List SLOW: []
15:51:04:ST3_smx:INFO: Holes
15:51:04:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
15:51:06:ST3_smx:INFO: ----> Checking Analog response
15:51:06:ST3_smx:INFO: ----> Checking broken channels
15:51:06:ST3_smx:INFO: Total # broken ch: 2
15:51:06:ST3_smx:INFO: List FAST: [68, 96]
15:51:06:ST3_smx:INFO: List SLOW: []
15:51:06:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:51:06:febtest:INFO: 0-0 | XA-000-08-002-000-001-221-11 | 50.4 | 1165.6
15:51:07:febtest:INFO: 0-1 | XA-000-08-001-064-050-160-13 | 50.4 | 1177.4
15:51:07:febtest:INFO: 0-2 | XA-000-08-002-000-001-045-13 | 60.0 | 1130.0
15:51:07:febtest:INFO: 0-3 | XA-000-08-001-064-051-128-14 | 56.8 | 1141.9
15:51:07:febtest:INFO: 0-4 | XA-000-08-001-064-051-080-06 | 40.9 | 1201.0
15:51:08:febtest:INFO: 0-5 | XA-000-08-001-064-051-136-14 | 44.1 | 1183.3
15:51:08:febtest:INFO: 0-6 | XA-000-08-001-064-051-088-06 | 40.9 | 1195.1
15:51:08:febtest:INFO: 0-7 | XA-000-08-001-064-051-184-07 | 50.4 | 1165.6
15:51:08:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:51:12:ST3_smx:INFO: chip: 0-3 53.612520 C 1153.732915 mV
15:51:12:ST3_smx:INFO: Electrons
15:51:12:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
15:51:14:ST3_smx:INFO: ----> Checking Analog response
15:51:14:ST3_smx:INFO: ----> Checking broken channels
15:51:14:ST3_smx:INFO: Total # broken ch: 5
15:51:14:ST3_smx:INFO: List FAST: [31, 35, 43, 45, 110]
15:51:14:ST3_smx:INFO: List SLOW: []
15:51:14:ST3_smx:INFO: Holes
15:51:14:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
15:51:16:ST3_smx:INFO: ----> Checking Analog response
15:51:16:ST3_smx:INFO: ----> Checking broken channels
15:51:16:ST3_smx:INFO: Total # broken ch: 5
15:51:16:ST3_smx:INFO: List FAST: [31, 35, 43, 45, 110]
15:51:16:ST3_smx:INFO: List SLOW: []
15:51:16:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:51:17:febtest:INFO: 0-0 | XA-000-08-002-000-001-221-11 | 50.4 | 1165.6
15:51:17:febtest:INFO: 0-1 | XA-000-08-001-064-050-160-13 | 50.4 | 1177.4
15:51:17:febtest:INFO: 0-2 | XA-000-08-002-000-001-045-13 | 60.0 | 1130.0
15:51:17:febtest:INFO: 0-3 | XA-000-08-001-064-051-128-14 | 56.8 | 1147.8
15:51:18:febtest:INFO: 0-4 | XA-000-08-001-064-051-080-06 | 40.9 | 1201.0
15:51:18:febtest:INFO: 0-5 | XA-000-08-001-064-051-136-14 | 44.1 | 1183.3
15:51:18:febtest:INFO: 0-6 | XA-000-08-001-064-051-088-06 | 40.9 | 1195.1
15:51:18:febtest:INFO: 0-7 | XA-000-08-001-064-051-184-07 | 50.4 | 1165.6
15:51:19:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:51:22:ST3_smx:INFO: chip: 0-4 53.612520 C 1165.571835 mV
15:51:22:ST3_smx:INFO: Electrons
15:51:22:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
15:51:24:ST3_smx:INFO: ----> Checking Analog response
15:51:24:ST3_smx:INFO: ----> Checking broken channels
15:51:25:ST3_smx:INFO: Total # broken ch: 4
15:51:25:ST3_smx:INFO: List FAST: [39, 74, 76, 117]
15:51:25:ST3_smx:INFO: List SLOW: []
15:51:25:ST3_smx:INFO: Holes
15:51:25:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
15:51:26:ST3_smx:INFO: ----> Checking Analog response
15:51:26:ST3_smx:INFO: ----> Checking broken channels
15:51:27:ST3_smx:INFO: Total # broken ch: 4
15:51:27:ST3_smx:INFO: List FAST: [39, 74, 76, 117]
15:51:27:ST3_smx:INFO: List SLOW: []
15:51:27:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:51:27:febtest:INFO: 0-0 | XA-000-08-002-000-001-221-11 | 50.4 | 1165.6
15:51:27:febtest:INFO: 0-1 | XA-000-08-001-064-050-160-13 | 50.4 | 1177.4
15:51:27:febtest:INFO: 0-2 | XA-000-08-002-000-001-045-13 | 60.0 | 1130.0
15:51:28:febtest:INFO: 0-3 | XA-000-08-001-064-051-128-14 | 56.8 | 1153.7
15:51:28:febtest:INFO: 0-4 | XA-000-08-001-064-051-080-06 | 53.6 | 1165.6
15:51:28:febtest:INFO: 0-5 | XA-000-08-001-064-051-136-14 | 47.3 | 1183.3
15:51:28:febtest:INFO: 0-6 | XA-000-08-001-064-051-088-06 | 40.9 | 1195.1
15:51:29:febtest:INFO: 0-7 | XA-000-08-001-064-051-184-07 | 53.6 | 1165.6
15:51:29:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:51:32:ST3_smx:INFO: chip: 0-5 50.430383 C 1171.483840 mV
15:51:32:ST3_smx:INFO: Electrons
15:51:33:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
15:51:35:ST3_smx:INFO: ----> Checking Analog response
15:51:35:ST3_smx:INFO: ----> Checking broken channels
15:51:35:ST3_smx:INFO: Total # broken ch: 2
15:51:35:ST3_smx:INFO: List FAST: [9, 20]
15:51:35:ST3_smx:INFO: List SLOW: []
15:51:35:ST3_smx:INFO: Holes
15:51:35:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
15:51:37:ST3_smx:INFO: ----> Checking Analog response
15:51:37:ST3_smx:INFO: ----> Checking broken channels
15:51:37:ST3_smx:INFO: Total # broken ch: 2
15:51:37:ST3_smx:INFO: List FAST: [9, 20]
15:51:37:ST3_smx:INFO: List SLOW: []
15:51:37:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:51:37:febtest:INFO: 0-0 | XA-000-08-002-000-001-221-11 | 50.4 | 1165.6
15:51:37:febtest:INFO: 0-1 | XA-000-08-001-064-050-160-13 | 50.4 | 1177.4
15:51:38:febtest:INFO: 0-2 | XA-000-08-002-000-001-045-13 | 60.0 | 1130.0
15:51:38:febtest:INFO: 0-3 | XA-000-08-001-064-051-128-14 | 53.6 | 1153.7
15:51:38:febtest:INFO: 0-4 | XA-000-08-001-064-051-080-06 | 53.6 | 1165.6
15:51:38:febtest:INFO: 0-5 | XA-000-08-001-064-051-136-14 | 50.4 | 1171.5
15:51:39:febtest:INFO: 0-6 | XA-000-08-001-064-051-088-06 | 40.9 | 1195.1
15:51:39:febtest:INFO: 0-7 | XA-000-08-001-064-051-184-07 | 50.4 | 1165.6
15:51:39:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:51:43:ST3_smx:INFO: chip: 0-6 50.430383 C 1159.654860 mV
15:51:43:ST3_smx:INFO: Electrons
15:51:43:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
15:51:45:ST3_smx:INFO: ----> Checking Analog response
15:51:45:ST3_smx:INFO: ----> Checking broken channels
15:51:45:ST3_smx:INFO: Total # broken ch: 4
15:51:45:ST3_smx:INFO: List FAST: [1, 38, 54]
15:51:45:ST3_smx:INFO: List SLOW: [1]
15:51:45:ST3_smx:INFO: Holes
15:51:45:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
15:51:47:ST3_smx:INFO: ----> Checking Analog response
15:51:47:ST3_smx:INFO: ----> Checking broken channels
15:51:47:ST3_smx:INFO: Total # broken ch: 4
15:51:47:ST3_smx:INFO: List FAST: [1, 38, 54]
15:51:47:ST3_smx:INFO: List SLOW: [1]
15:51:47:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:51:48:febtest:INFO: 0-0 | XA-000-08-002-000-001-221-11 | 50.4 | 1165.6
15:51:48:febtest:INFO: 0-1 | XA-000-08-001-064-050-160-13 | 50.4 | 1177.4
15:51:48:febtest:INFO: 0-2 | XA-000-08-002-000-001-045-13 | 60.0 | 1135.9
15:51:48:febtest:INFO: 0-3 | XA-000-08-001-064-051-128-14 | 56.8 | 1153.7
15:51:48:febtest:INFO: 0-4 | XA-000-08-001-064-051-080-06 | 53.6 | 1165.6
15:51:49:febtest:INFO: 0-5 | XA-000-08-001-064-051-136-14 | 50.4 | 1171.5
15:51:49:febtest:INFO: 0-6 | XA-000-08-001-064-051-088-06 | 53.6 | 1153.7
15:51:49:febtest:INFO: 0-7 | XA-000-08-001-064-051-184-07 | 53.6 | 1165.6
15:51:49:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:51:53:ST3_smx:INFO: chip: 0-7 50.430383 C 1171.483840 mV
15:51:53:ST3_smx:INFO: Electrons
15:51:53:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
15:51:55:ST3_smx:INFO: ----> Checking Analog response
15:51:55:ST3_smx:INFO: ----> Checking broken channels
15:51:55:ST3_smx:INFO: Total # broken ch: 4
15:51:55:ST3_smx:INFO: List FAST: [75, 80, 81, 125]
15:51:55:ST3_smx:INFO: List SLOW: []
15:51:55:ST3_smx:INFO: Holes
15:51:55:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
15:51:57:ST3_smx:INFO: ----> Checking Analog response
15:51:57:ST3_smx:INFO: ----> Checking broken channels
15:51:57:ST3_smx:INFO: Total # broken ch: 4
15:51:57:ST3_smx:INFO: List FAST: [75, 80, 81, 125]
15:51:57:ST3_smx:INFO: List SLOW: []
15:51:57:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:51:58:febtest:INFO: 0-0 | XA-000-08-002-000-001-221-11 | 50.4 | 1165.6
15:51:58:febtest:INFO: 0-1 | XA-000-08-001-064-050-160-13 | 50.4 | 1171.5
15:51:58:febtest:INFO: 0-2 | XA-000-08-002-000-001-045-13 | 60.0 | 1135.9
15:51:58:febtest:INFO: 0-3 | XA-000-08-001-064-051-128-14 | 56.8 | 1153.7
15:51:59:febtest:INFO: 0-4 | XA-000-08-001-064-051-080-06 | 53.6 | 1165.6
15:51:59:febtest:INFO: 0-5 | XA-000-08-001-064-051-136-14 | 50.4 | 1171.5
15:51:59:febtest:INFO: 0-6 | XA-000-08-001-064-051-088-06 | 53.6 | 1153.7
15:51:59:febtest:INFO: 0-7 | XA-000-08-001-064-051-184-07 | 50.4 | 1165.6
############################################################
# S U M M A R Y #
############################################################
{'TEST_NAME': 'FEB-ASIC', 'TEST_DATE': '2023_11_20-15_50_22', 'OPERATOR': 'Alois Alzheimer', 'PROJECT': 'Production', 'SITE': 'GSI', 'SETUP': 'GSI_TEST_SETUP_1', 'ASIC_ID': 'XA-000-08-001-064-051-184-07', 'FUSED_ID': 6359364698915421063, 'HW_ADDR': 7, 'UPLINK': 24, 'VERS_NO': '2.2', 'CABLE_SET_ID': '', 'IC_TEMP': '0', 'VDDM': '0', 'AUX': '0', 'CSABIAS': '0', 'VDDM_INT': '0', 'ADC_Chi2': 0.0, 'ADC_NDF': 0, 'ADC_P0': 0.0, 'ADC_P1': 0.006824, 'ADC_P2': -2.485e-06, 'ADC_P0err': 0.001, 'ADC_P1err': 0.001, 'ADC_P2err': 1e-05, 'ADC_VREF_P': 58, 'ADC_VREF_N': 30, 'ADC_VREF_T': 128, 'ADC_VREF_TR': 122, 'THR2_GLB': 30, 'LOOP__PLS': 100, 'CALIB_PLS': 250, 'SnsLoop': 5, 'IFED': 31, 'CSA_BIAS': 15, 'CSA_Chi2': 0.0, 'CSA_NDF': 0, 'CSA_P0': 0.0, 'CSA_P1': 0.0, 'CSA_P2': 0.0, 'CSA_P0err': 0.0, 'CSA_P1err': 0.0, 'CSA_P2err': 0.0, 'CONF_FAIL_REG': 0, 'N_BROKEN_DISC': 4, 'N_BROKEN_FAST': '[75, 80, 81, 125]', 'N_BROKEN_SLOW': '[]', 'P_BROKEN_DISC': 4, 'P_BROKEN_FAST': '[75, 80, 81, 125]', 'P_BROKEN_SLOW': '[]', 'ASIC_QA_category': '', 'N_BROKEN_CABLE': 0, 'LIST_OF_BROKEN_CABLES': 0, 'ADDR_0': '', 'ADDR_1': '', 'ADDR_2': '', 'ADDR_3': '', 'ADDR_4': '', 'ADDR_5': '', 'ADDR_6': '', 'ADDR_7': '', 'SENSOR_ID': '', 'MODULE_NAME': '', 'MODULE_LADDER': '', 'MODULE_MODULE': '', 'MODULE_SIZE': '', 'MODULE_GRADE': '', 'MODULE_TYPE': '', 'VI_bInit': ['2.448', '1.8440', '1.845', '2.9370', '7.000', '1.5560', '7.000', '1.5560'], 'VI_aInit': ['0', '0', '0', '0', '0', '0'], 'VI_atEnd': ['0', '0', '0', '0', '0', '0'], 'AMP_CAL': 125, 'PlsLoop': 3, 'N_ANA_PRESENT': 'Analog response OK', 'N_DISC_FAIL_CH': 0, 'N_ANA_FAIL_CH': '0', 'P_ANA_PRESENT': 'Analog response OK', 'P_DISC_FAIL_CH': 0, 'P_ANA_FAIL_CH': '0'}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-ASIC
TEST_DATE : 2023_11_20-15_50_22
OPERATOR : Alois Alzheimer
SITE : GSI
SETUP : GSI_TEST_SETUP_1
Set-ID :
---------------------------------------
MODULE_NAME
---------------------------------------
VI_before_Init : ['2.448', '1.8440', '1.845', '2.9370', '7.000', '1.5560', '7.000', '1.5560']
VI_after__Init : ['2.450', '2.0240', '1.850', '0.3300', '7.000', '1.5520', '7.000', '1.5520']
VI_at__the_End : ['2.450', '2.0240', '1.850', '0.3300', '7.000', '1.5520', '7.000', '1.5520']
15:52:03:ST3_Shared:INFO: /home/cbm/public_html/Production_LogDir//FEB/FEB_2027/TestDate_2023_11_20-15_50_22/