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FEB_2029 20.11.23 16:30:22
TextEdit.txt
16:29:49:ST3_hmp4040:INFO: HAMEG,HMP2030,017836163,HW50010002/SW2.30
16:29:50:febtest:INFO: FEB8.2 selected
16:29:50:smx_tester:INFO: Setting Elink clock mode to 160 MHz
16:30:22:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
16:30:22:ST3_Shared:INFO: --------------------------FEB-ASIC--------------------------
16:30:22:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
16:30:23:febtest:INFO: Tsting FEB with SN 2029
16:30:24:smx_tester:INFO: Scanning setup
16:30:24:elinks:INFO: Disabling clock on downlink 0
16:30:24:elinks:INFO: Disabling clock on downlink 1
16:30:24:elinks:INFO: Disabling clock on downlink 2
16:30:24:elinks:INFO: Disabling clock on downlink 3
16:30:24:elinks:INFO: Disabling clock on downlink 4
16:30:24:setup_element:INFO: Checking SOS, encoding_mode: SOS
16:30:24:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
16:30:24:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
16:30:24:elinks:INFO: Disabling clock on downlink 0
16:30:24:elinks:INFO: Disabling clock on downlink 1
16:30:24:elinks:INFO: Disabling clock on downlink 2
16:30:24:elinks:INFO: Disabling clock on downlink 3
16:30:24:elinks:INFO: Disabling clock on downlink 4
16:30:24:setup_element:INFO: Checking SOS, encoding_mode: SOS
16:30:24:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
16:30:24:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 0
16:30:24:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 1
16:30:24:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 2
16:30:24:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 3
16:30:24:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 4
16:30:24:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 5
16:30:24:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 6
16:30:24:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 7
16:30:24:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 8
16:30:24:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 9
16:30:24:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 10
16:30:24:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 11
16:30:24:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 12
16:30:24:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 13
16:30:24:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 14
16:30:24:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 15
16:30:24:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
16:30:24:elinks:INFO: Disabling clock on downlink 0
16:30:24:elinks:INFO: Disabling clock on downlink 1
16:30:24:elinks:INFO: Disabling clock on downlink 2
16:30:24:elinks:INFO: Disabling clock on downlink 3
16:30:24:elinks:INFO: Disabling clock on downlink 4
16:30:24:setup_element:INFO: Checking SOS, encoding_mode: SOS
16:30:24:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
16:30:24:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 16
16:30:24:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 17
16:30:24:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 18
16:30:24:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 19
16:30:24:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 20
16:30:24:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 21
16:30:24:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 22
16:30:24:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 23
16:30:24:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24
16:30:24:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25
16:30:24:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26
16:30:24:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27
16:30:24:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28
16:30:24:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29
16:30:24:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30
16:30:24:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31
16:30:24:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
16:30:24:elinks:INFO: Disabling clock on downlink 0
16:30:24:elinks:INFO: Disabling clock on downlink 1
16:30:24:elinks:INFO: Disabling clock on downlink 2
16:30:24:elinks:INFO: Disabling clock on downlink 3
16:30:24:elinks:INFO: Disabling clock on downlink 4
16:30:24:setup_element:INFO: Checking SOS, encoding_mode: SOS
16:30:24:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
16:30:25:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
16:30:25:elinks:INFO: Disabling clock on downlink 0
16:30:25:elinks:INFO: Disabling clock on downlink 1
16:30:25:elinks:INFO: Disabling clock on downlink 2
16:30:25:elinks:INFO: Disabling clock on downlink 3
16:30:25:elinks:INFO: Disabling clock on downlink 4
16:30:25:setup_element:INFO: Checking SOS, encoding_mode: SOS
16:30:25:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
16:30:25:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
16:30:25:setup_element:INFO: Scanning clock phase
16:30:25:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
16:30:25:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
16:30:25:setup_element:INFO: Clock phase scan results for group 0, downlink 1
16:30:25:setup_element:INFO: Eye window for uplink 0 : _________________________________________________________________________XXXXXXX
Clock Delay: 36
16:30:25:setup_element:INFO: Eye window for uplink 1 : _________________________________________________________________________XXXXXXX
Clock Delay: 36
16:30:25:setup_element:INFO: Eye window for uplink 2 : ________________________________________________________________________XXXXXXXX
Clock Delay: 35
16:30:25:setup_element:INFO: Eye window for uplink 3 : ________________________________________________________________________XXXXXXXX
Clock Delay: 35
16:30:25:setup_element:INFO: Eye window for uplink 4 : _______________________________________________________________________XXXXXXX__
Clock Delay: 34
16:30:25:setup_element:INFO: Eye window for uplink 5 : _______________________________________________________________________XXXXXXX__
Clock Delay: 34
16:30:25:setup_element:INFO: Eye window for uplink 6 : ________________________________________________________________________XXXXXXX_
Clock Delay: 35
16:30:25:setup_element:INFO: Eye window for uplink 7 : ________________________________________________________________________XXXXXXX_
Clock Delay: 35
16:30:25:setup_element:INFO: Eye window for uplink 8 : ______________________________________________________________________XXXXXXX___
Clock Delay: 33
16:30:25:setup_element:INFO: Eye window for uplink 9 : ______________________________________________________________________XXXXXXX___
Clock Delay: 33
16:30:25:setup_element:INFO: Eye window for uplink 10: ______________________________________________________________________XXXXXXX___
Clock Delay: 33
16:30:25:setup_element:INFO: Eye window for uplink 11: ______________________________________________________________________XXXXXXX___
Clock Delay: 33
16:30:25:setup_element:INFO: Eye window for uplink 12: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
16:30:25:setup_element:INFO: Eye window for uplink 13: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
16:30:25:setup_element:INFO: Eye window for uplink 14: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
16:30:25:setup_element:INFO: Eye window for uplink 15: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
16:30:25:setup_element:INFO: Setting the clock phase to 34 for group 0, downlink 1
16:30:25:setup_element:INFO: Scanning clock phase
16:30:25:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
16:30:25:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
16:30:26:setup_element:INFO: Clock phase scan results for group 0, downlink 2
16:30:26:setup_element:INFO: Eye window for uplink 16: ________________________________________________________________________XXXXXXX_
Clock Delay: 35
16:30:26:setup_element:INFO: Eye window for uplink 17: ________________________________________________________________________XXXXXXX_
Clock Delay: 35
16:30:26:setup_element:INFO: Eye window for uplink 18: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
16:30:26:setup_element:INFO: Eye window for uplink 19: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
16:30:26:setup_element:INFO: Eye window for uplink 20: ______________________________________________________________________XXXXXXX___
Clock Delay: 33
16:30:26:setup_element:INFO: Eye window for uplink 21: ______________________________________________________________________XXXXXXX___
Clock Delay: 33
16:30:26:setup_element:INFO: Eye window for uplink 22: ______________________________________________________________________XXXXXXX___
Clock Delay: 33
16:30:26:setup_element:INFO: Eye window for uplink 23: ______________________________________________________________________XXXXXXX___
Clock Delay: 33
16:30:26:setup_element:INFO: Eye window for uplink 24: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
16:30:26:setup_element:INFO: Eye window for uplink 25: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
16:30:26:setup_element:INFO: Eye window for uplink 26: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
16:30:26:setup_element:INFO: Eye window for uplink 27: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
16:30:26:setup_element:INFO: Eye window for uplink 28: _______________________________________________________________________XXXXXX___
Clock Delay: 33
16:30:26:setup_element:INFO: Eye window for uplink 29: _______________________________________________________________________XXXXXX___
Clock Delay: 33
16:30:26:setup_element:INFO: Eye window for uplink 30: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
16:30:26:setup_element:INFO: Eye window for uplink 31: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
16:30:26:setup_element:INFO: Setting the clock phase to 34 for group 0, downlink 2
16:30:26:setup_element:INFO: Scanning data phases
16:30:26:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
16:30:26:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
16:30:31:setup_element:INFO: Data phase scan results for group 0, downlink 1
16:30:32:setup_element:INFO: Eye window for uplink 0 : ________XXXXXX__________________________
Data delay found: 30
16:30:32:setup_element:INFO: Eye window for uplink 1 : ____XXXXXX______________________________
Data delay found: 26
16:30:32:setup_element:INFO: Eye window for uplink 2 : ____XXXXX_______________________________
Data delay found: 26
16:30:32:setup_element:INFO: Eye window for uplink 3 : _XXXXXX_________________________________
Data delay found: 23
16:30:32:setup_element:INFO: Eye window for uplink 4 : XXXX___________________________________X
Data delay found: 21
16:30:32:setup_element:INFO: Eye window for uplink 5 : X__________________________________XXXXX
Data delay found: 17
16:30:32:setup_element:INFO: Eye window for uplink 6 : ____________________________________XXXX
Data delay found: 17
16:30:32:setup_element:INFO: Eye window for uplink 7 : _______________________________XXXXX____
Data delay found: 13
16:30:32:setup_element:INFO: Eye window for uplink 8 : _____________________XXXXX______________
Data delay found: 3
16:30:32:setup_element:INFO: Eye window for uplink 9 : _________________________XXXXX__________
Data delay found: 7
16:30:32:setup_element:INFO: Eye window for uplink 10: ______________________XXXXXXX___________
Data delay found: 5
16:30:32:setup_element:INFO: Eye window for uplink 11: __________________________XXXXXX________
Data delay found: 8
16:30:32:setup_element:INFO: Eye window for uplink 12: _______________________XXXXX____________
Data delay found: 5
16:30:32:setup_element:INFO: Eye window for uplink 13: __________________________XXXXX_________
Data delay found: 8
16:30:32:setup_element:INFO: Eye window for uplink 14: _________________________XXXX___________
Data delay found: 6
16:30:32:setup_element:INFO: Eye window for uplink 15: ___________________________XXXXX________
Data delay found: 9
16:30:32:setup_element:INFO: Setting the data phase to 30 for uplink 0
16:30:32:setup_element:INFO: Setting the data phase to 26 for uplink 1
16:30:32:setup_element:INFO: Setting the data phase to 26 for uplink 2
16:30:32:setup_element:INFO: Setting the data phase to 23 for uplink 3
16:30:32:setup_element:INFO: Setting the data phase to 21 for uplink 4
16:30:32:setup_element:INFO: Setting the data phase to 17 for uplink 5
16:30:32:setup_element:INFO: Setting the data phase to 17 for uplink 6
16:30:32:setup_element:INFO: Setting the data phase to 13 for uplink 7
16:30:32:setup_element:INFO: Setting the data phase to 3 for uplink 8
16:30:32:setup_element:INFO: Setting the data phase to 7 for uplink 9
16:30:32:setup_element:INFO: Setting the data phase to 5 for uplink 10
16:30:32:setup_element:INFO: Setting the data phase to 8 for uplink 11
16:30:32:setup_element:INFO: Setting the data phase to 5 for uplink 12
16:30:32:setup_element:INFO: Setting the data phase to 8 for uplink 13
16:30:32:setup_element:INFO: Setting the data phase to 6 for uplink 14
16:30:32:setup_element:INFO: Setting the data phase to 9 for uplink 15
16:30:32:setup_element:INFO: Scanning data phases
16:30:32:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
16:30:32:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
16:30:37:setup_element:INFO: Data phase scan results for group 0, downlink 2
16:30:37:setup_element:INFO: Eye window for uplink 16: X__________________________________XXXXX
Data delay found: 17
16:30:37:setup_element:INFO: Eye window for uplink 17: _______________________________XXXXXX___
Data delay found: 13
16:30:37:setup_element:INFO: Eye window for uplink 18: _______________________________XXXXXX___
Data delay found: 13
16:30:37:setup_element:INFO: Eye window for uplink 19: _____________________________XXXXX______
Data delay found: 11
16:30:37:setup_element:INFO: Eye window for uplink 20: _______________________________XXXXX____
Data delay found: 13
16:30:37:setup_element:INFO: Eye window for uplink 21: ______________________________XXXXX_____
Data delay found: 12
16:30:37:setup_element:INFO: Eye window for uplink 22: _______________________________XXXXX____
Data delay found: 13
16:30:37:setup_element:INFO: Eye window for uplink 23: _____________________________XXXXX______
Data delay found: 11
16:30:37:setup_element:INFO: Eye window for uplink 24: __XXXXX________XXXXXXXXXXXXXXXXXXXXXXXXX
Data delay found: 10
16:30:37:setup_element:INFO: Eye window for uplink 25: ____XXXXXX_____XXXXXXXXXXXXXXXXXXXXXXXXX
Data delay found: 12
16:30:37:setup_element:INFO: Eye window for uplink 26: ___XXXXX________________________________
Data delay found: 25
16:30:37:setup_element:INFO: Eye window for uplink 27: ______XXXXX_____________________________
Data delay found: 28
16:30:37:setup_element:INFO: Eye window for uplink 28: _________XXXXX__________________________
Data delay found: 31
16:30:37:setup_element:INFO: Eye window for uplink 29: ___________XXXXX________________________
Data delay found: 33
16:30:37:setup_element:INFO: Eye window for uplink 30: ____________XXXXXX______________________
Data delay found: 34
16:30:37:setup_element:INFO: Eye window for uplink 31: ___________XXXXX________________________
Data delay found: 33
16:30:37:setup_element:INFO: Setting the data phase to 17 for uplink 16
16:30:37:setup_element:INFO: Setting the data phase to 13 for uplink 17
16:30:37:setup_element:INFO: Setting the data phase to 13 for uplink 18
16:30:37:setup_element:INFO: Setting the data phase to 11 for uplink 19
16:30:37:setup_element:INFO: Setting the data phase to 13 for uplink 20
16:30:37:setup_element:INFO: Setting the data phase to 12 for uplink 21
16:30:37:setup_element:INFO: Setting the data phase to 13 for uplink 22
16:30:37:setup_element:INFO: Setting the data phase to 11 for uplink 23
16:30:37:setup_element:INFO: Setting the data phase to 10 for uplink 24
16:30:37:setup_element:INFO: Setting the data phase to 12 for uplink 25
16:30:37:setup_element:INFO: Setting the data phase to 25 for uplink 26
16:30:37:setup_element:INFO: Setting the data phase to 28 for uplink 27
16:30:37:setup_element:INFO: Setting the data phase to 31 for uplink 28
16:30:37:setup_element:INFO: Setting the data phase to 33 for uplink 29
16:30:37:setup_element:INFO: Setting the data phase to 34 for uplink 30
16:30:37:setup_element:INFO: Setting the data phase to 33 for uplink 31
16:30:37:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 1
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 34
Window Length: 70
Eye Windows:
Uplink 0: _________________________________________________________________________XXXXXXX
Uplink 1: _________________________________________________________________________XXXXXXX
Uplink 2: ________________________________________________________________________XXXXXXXX
Uplink 3: ________________________________________________________________________XXXXXXXX
Uplink 4: _______________________________________________________________________XXXXXXX__
Uplink 5: _______________________________________________________________________XXXXXXX__
Uplink 6: ________________________________________________________________________XXXXXXX_
Uplink 7: ________________________________________________________________________XXXXXXX_
Uplink 8: ______________________________________________________________________XXXXXXX___
Uplink 9: ______________________________________________________________________XXXXXXX___
Uplink 10: ______________________________________________________________________XXXXXXX___
Uplink 11: ______________________________________________________________________XXXXXXX___
Uplink 12: ______________________________________________________________________XXXXXXXX__
Uplink 13: ______________________________________________________________________XXXXXXXX__
Uplink 14: _______________________________________________________________________XXXXXXX__
Uplink 15: _______________________________________________________________________XXXXXXX__
Data phase characteristics:
Uplink 0:
Optimal Phase: 30
Window Length: 34
Eye Window: ________XXXXXX__________________________
Uplink 1:
Optimal Phase: 26
Window Length: 34
Eye Window: ____XXXXXX______________________________
Uplink 2:
Optimal Phase: 26
Window Length: 35
Eye Window: ____XXXXX_______________________________
Uplink 3:
Optimal Phase: 23
Window Length: 34
Eye Window: _XXXXXX_________________________________
Uplink 4:
Optimal Phase: 21
Window Length: 35
Eye Window: XXXX___________________________________X
Uplink 5:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXXX
Uplink 6:
Optimal Phase: 17
Window Length: 36
Eye Window: ____________________________________XXXX
Uplink 7:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 8:
Optimal Phase: 3
Window Length: 35
Eye Window: _____________________XXXXX______________
Uplink 9:
Optimal Phase: 7
Window Length: 35
Eye Window: _________________________XXXXX__________
Uplink 10:
Optimal Phase: 5
Window Length: 33
Eye Window: ______________________XXXXXXX___________
Uplink 11:
Optimal Phase: 8
Window Length: 34
Eye Window: __________________________XXXXXX________
Uplink 12:
Optimal Phase: 5
Window Length: 35
Eye Window: _______________________XXXXX____________
Uplink 13:
Optimal Phase: 8
Window Length: 35
Eye Window: __________________________XXXXX_________
Uplink 14:
Optimal Phase: 6
Window Length: 36
Eye Window: _________________________XXXX___________
Uplink 15:
Optimal Phase: 9
Window Length: 35
Eye Window: ___________________________XXXXX________
,
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 34
Window Length: 71
Eye Windows:
Uplink 16: ________________________________________________________________________XXXXXXX_
Uplink 17: ________________________________________________________________________XXXXXXX_
Uplink 18: ______________________________________________________________________XXXXXXXX__
Uplink 19: ______________________________________________________________________XXXXXXXX__
Uplink 20: ______________________________________________________________________XXXXXXX___
Uplink 21: ______________________________________________________________________XXXXXXX___
Uplink 22: ______________________________________________________________________XXXXXXX___
Uplink 23: ______________________________________________________________________XXXXXXX___
Uplink 24: ______________________________________________________________________XXXXXXXX__
Uplink 25: ______________________________________________________________________XXXXXXXX__
Uplink 26: ______________________________________________________________________XXXXXXXX__
Uplink 27: ______________________________________________________________________XXXXXXXX__
Uplink 28: _______________________________________________________________________XXXXXX___
Uplink 29: _______________________________________________________________________XXXXXX___
Uplink 30: _______________________________________________________________________XXXXXXXX_
Uplink 31: _______________________________________________________________________XXXXXXXX_
Data phase characteristics:
Uplink 16:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXXX
Uplink 17:
Optimal Phase: 13
Window Length: 34
Eye Window: _______________________________XXXXXX___
Uplink 18:
Optimal Phase: 13
Window Length: 34
Eye Window: _______________________________XXXXXX___
Uplink 19:
Optimal Phase: 11
Window Length: 35
Eye Window: _____________________________XXXXX______
Uplink 20:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 21:
Optimal Phase: 12
Window Length: 35
Eye Window: ______________________________XXXXX_____
Uplink 22:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 23:
Optimal Phase: 11
Window Length: 35
Eye Window: _____________________________XXXXX______
Uplink 24:
Optimal Phase: 10
Window Length: 8
Eye Window: __XXXXX________XXXXXXXXXXXXXXXXXXXXXXXXX
Uplink 25:
Optimal Phase: 12
Window Length: 5
Eye Window: ____XXXXXX_____XXXXXXXXXXXXXXXXXXXXXXXXX
Uplink 26:
Optimal Phase: 25
Window Length: 35
Eye Window: ___XXXXX________________________________
Uplink 27:
Optimal Phase: 28
Window Length: 35
Eye Window: ______XXXXX_____________________________
Uplink 28:
Optimal Phase: 31
Window Length: 35
Eye Window: _________XXXXX__________________________
Uplink 29:
Optimal Phase: 33
Window Length: 35
Eye Window: ___________XXXXX________________________
Uplink 30:
Optimal Phase: 34
Window Length: 34
Eye Window: ____________XXXXXX______________________
Uplink 31:
Optimal Phase: 33
Window Length: 35
Eye Window: ___________XXXXX________________________
]
16:30:37:setup_element:INFO: Beginning SMX ASICs map scan
16:30:37:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
16:30:37:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
16:30:37:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
16:30:37:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
16:30:37:uplink:INFO: Setting uplinks mask [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
16:30:37:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 1
16:30:38:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 0
16:30:38:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 8
16:30:38:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 9
16:30:38:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 3
16:30:38:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 2
16:30:38:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 10
16:30:38:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 11
16:30:38:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 5
16:30:38:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 4
16:30:38:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 12
16:30:38:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 13
16:30:39:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 7
16:30:39:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 6
16:30:39:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 14
16:30:39:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 15
16:30:40:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 1
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 1), (1, 0)
ASIC address 0x1: (ASIC uplink, uplink): (0, 8), (1, 9)
ASIC address 0x2: (ASIC uplink, uplink): (0, 3), (1, 2)
ASIC address 0x3: (ASIC uplink, uplink): (0, 10), (1, 11)
ASIC address 0x4: (ASIC uplink, uplink): (0, 5), (1, 4)
ASIC address 0x5: (ASIC uplink, uplink): (0, 12), (1, 13)
ASIC address 0x6: (ASIC uplink, uplink): (0, 7), (1, 6)
ASIC address 0x7: (ASIC uplink, uplink): (0, 14), (1, 15)
Clock Phase Characteristic:
Optimal Phase: 34
Window Length: 70
Eye Windows:
Uplink 0: _________________________________________________________________________XXXXXXX
Uplink 1: _________________________________________________________________________XXXXXXX
Uplink 2: ________________________________________________________________________XXXXXXXX
Uplink 3: ________________________________________________________________________XXXXXXXX
Uplink 4: _______________________________________________________________________XXXXXXX__
Uplink 5: _______________________________________________________________________XXXXXXX__
Uplink 6: ________________________________________________________________________XXXXXXX_
Uplink 7: ________________________________________________________________________XXXXXXX_
Uplink 8: ______________________________________________________________________XXXXXXX___
Uplink 9: ______________________________________________________________________XXXXXXX___
Uplink 10: ______________________________________________________________________XXXXXXX___
Uplink 11: ______________________________________________________________________XXXXXXX___
Uplink 12: ______________________________________________________________________XXXXXXXX__
Uplink 13: ______________________________________________________________________XXXXXXXX__
Uplink 14: _______________________________________________________________________XXXXXXX__
Uplink 15: _______________________________________________________________________XXXXXXX__
Data phase characteristics:
Uplink 0:
Optimal Phase: 30
Window Length: 34
Eye Window: ________XXXXXX__________________________
Uplink 1:
Optimal Phase: 26
Window Length: 34
Eye Window: ____XXXXXX______________________________
Uplink 2:
Optimal Phase: 26
Window Length: 35
Eye Window: ____XXXXX_______________________________
Uplink 3:
Optimal Phase: 23
Window Length: 34
Eye Window: _XXXXXX_________________________________
Uplink 4:
Optimal Phase: 21
Window Length: 35
Eye Window: XXXX___________________________________X
Uplink 5:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXXX
Uplink 6:
Optimal Phase: 17
Window Length: 36
Eye Window: ____________________________________XXXX
Uplink 7:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 8:
Optimal Phase: 3
Window Length: 35
Eye Window: _____________________XXXXX______________
Uplink 9:
Optimal Phase: 7
Window Length: 35
Eye Window: _________________________XXXXX__________
Uplink 10:
Optimal Phase: 5
Window Length: 33
Eye Window: ______________________XXXXXXX___________
Uplink 11:
Optimal Phase: 8
Window Length: 34
Eye Window: __________________________XXXXXX________
Uplink 12:
Optimal Phase: 5
Window Length: 35
Eye Window: _______________________XXXXX____________
Uplink 13:
Optimal Phase: 8
Window Length: 35
Eye Window: __________________________XXXXX_________
Uplink 14:
Optimal Phase: 6
Window Length: 36
Eye Window: _________________________XXXX___________
Uplink 15:
Optimal Phase: 9
Window Length: 35
Eye Window: ___________________________XXXXX________
16:30:40:setup_element:INFO: Beginning SMX ASICs map scan
16:30:40:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
16:30:40:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
16:30:40:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
16:30:40:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
16:30:40:uplink:INFO: Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
16:30:40:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 23
16:30:40:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 22
16:30:41:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 30
16:30:41:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 31
16:30:41:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 21
16:30:41:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 20
16:30:41:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28
16:30:41:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 29
16:30:41:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 19
16:30:41:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 18
16:30:41:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26
16:30:41:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 27
16:30:41:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 17
16:30:42:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 16
16:30:42:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 24
16:30:42:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 25
16:30:43:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 23), (1, 22)
ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
ASIC address 0x2: (ASIC uplink, uplink): (0, 21), (1, 20)
ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
ASIC address 0x4: (ASIC uplink, uplink): (0, 19), (1, 18)
ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
ASIC address 0x6: (ASIC uplink, uplink): (0, 17), (1, 16)
ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
Clock Phase Characteristic:
Optimal Phase: 34
Window Length: 71
Eye Windows:
Uplink 16: ________________________________________________________________________XXXXXXX_
Uplink 17: ________________________________________________________________________XXXXXXX_
Uplink 18: ______________________________________________________________________XXXXXXXX__
Uplink 19: ______________________________________________________________________XXXXXXXX__
Uplink 20: ______________________________________________________________________XXXXXXX___
Uplink 21: ______________________________________________________________________XXXXXXX___
Uplink 22: ______________________________________________________________________XXXXXXX___
Uplink 23: ______________________________________________________________________XXXXXXX___
Uplink 24: ______________________________________________________________________XXXXXXXX__
Uplink 25: ______________________________________________________________________XXXXXXXX__
Uplink 26: ______________________________________________________________________XXXXXXXX__
Uplink 27: ______________________________________________________________________XXXXXXXX__
Uplink 28: _______________________________________________________________________XXXXXX___
Uplink 29: _______________________________________________________________________XXXXXX___
Uplink 30: _______________________________________________________________________XXXXXXXX_
Uplink 31: _______________________________________________________________________XXXXXXXX_
Data phase characteristics:
Uplink 16:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXXX
Uplink 17:
Optimal Phase: 13
Window Length: 34
Eye Window: _______________________________XXXXXX___
Uplink 18:
Optimal Phase: 13
Window Length: 34
Eye Window: _______________________________XXXXXX___
Uplink 19:
Optimal Phase: 11
Window Length: 35
Eye Window: _____________________________XXXXX______
Uplink 20:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 21:
Optimal Phase: 12
Window Length: 35
Eye Window: ______________________________XXXXX_____
Uplink 22:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 23:
Optimal Phase: 11
Window Length: 35
Eye Window: _____________________________XXXXX______
Uplink 24:
Optimal Phase: 10
Window Length: 8
Eye Window: __XXXXX________XXXXXXXXXXXXXXXXXXXXXXXXX
Uplink 25:
Optimal Phase: 12
Window Length: 5
Eye Window: ____XXXXXX_____XXXXXXXXXXXXXXXXXXXXXXXXX
Uplink 26:
Optimal Phase: 25
Window Length: 35
Eye Window: ___XXXXX________________________________
Uplink 27:
Optimal Phase: 28
Window Length: 35
Eye Window: ______XXXXX_____________________________
Uplink 28:
Optimal Phase: 31
Window Length: 35
Eye Window: _________XXXXX__________________________
Uplink 29:
Optimal Phase: 33
Window Length: 35
Eye Window: ___________XXXXX________________________
Uplink 30:
Optimal Phase: 34
Window Length: 34
Eye Window: ____________XXXXXX______________________
Uplink 31:
Optimal Phase: 33
Window Length: 35
Eye Window: ___________XXXXX________________________
16:30:43:setup_element:INFO: Performing Elink synchronization
16:30:43:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
16:30:43:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
16:30:43:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
16:30:43:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
16:30:43:setup_element:INFO: Performing Elink synchronization
16:30:43:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
16:30:43:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
16:30:43:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
16:30:43:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
16:30:43:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 1
16:30:43:uplink:INFO: Enabling uplinks [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
16:30:43:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2
16:30:43:uplink:INFO: Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
16:30:44:ST3_emu:INFO: Number of chips: 16
addr | upli | dwnli | grp | uplinks | uplinks_map
0 | [0] | 1 | 0 | [1] | [(0, 1), (1, 0)]
1 | [0] | 1 | 0 | [8] | [(0, 8), (1, 9)]
2 | [0] | 1 | 0 | [3] | [(0, 3), (1, 2)]
3 | [0] | 1 | 0 | [10] | [(0, 10), (1, 11)]
4 | [0] | 1 | 0 | [5] | [(0, 5), (1, 4)]
5 | [0] | 1 | 0 | [12] | [(0, 12), (1, 13)]
6 | [0] | 1 | 0 | [7] | [(0, 7), (1, 6)]
7 | [0] | 1 | 0 | [14] | [(0, 14), (1, 15)]
0 | [0] | 2 | 0 | [23] | [(0, 23), (1, 22)]
1 | [0] | 2 | 0 | [30] | [(0, 30), (1, 31)]
2 | [0] | 2 | 0 | [21] | [(0, 21), (1, 20)]
3 | [0] | 2 | 0 | [28] | [(0, 28), (1, 29)]
4 | [0] | 2 | 0 | [19] | [(0, 19), (1, 18)]
5 | [0] | 2 | 0 | [26] | [(0, 26), (1, 27)]
6 | [0] | 2 | 0 | [17] | [(0, 17), (1, 16)]
7 | [0] | 2 | 0 | [24] | [(0, 24), (1, 25)]
16:30:45:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:30:45:febtest:INFO: 0-0 | XA-000-08-002-000-001-022-04 | 60.0 | 1147.8
16:30:46:febtest:INFO: 0-1 | XA-000-08-002-000-001-018-04 | 53.6 | 1183.3
16:30:46:febtest:INFO: 0-2 | XA-000-08-002-000-001-025-04 | 63.2 | 1141.9
16:30:46:febtest:INFO: 0-3 | XA-000-08-002-000-001-023-04 | 53.6 | 1183.3
16:30:46:febtest:INFO: 0-4 | XA-000-08-002-000-001-037-13 | 60.0 | 1147.8
16:30:47:febtest:INFO: 0-5 | XA-000-08-002-000-001-020-04 | 66.4 | 1135.9
16:30:47:febtest:INFO: 0-6 | XA-000-08-002-000-001-034-13 | 60.0 | 1165.6
16:30:47:febtest:INFO: 0-7 | XA-000-08-002-000-001-036-13 | 44.1 | 1224.5
16:30:47:febtest:INFO: 0-0 | XA-000-08-002-000-001-021-04 | 56.8 | 1159.7
16:30:48:febtest:INFO: 0-1 | XA-000-08-002-000-002-021-10 | 60.0 | 1153.7
16:30:48:febtest:INFO: 0-2 | XA-000-08-002-000-001-024-04 | 66.4 | 1130.0
16:30:48:febtest:INFO: 0-3 | XA-000-08-002-000-002-019-10 | 56.8 | 1171.5
16:30:48:febtest:INFO: 0-4 | XA-000-08-002-000-001-019-04 | 50.4 | 1183.3
16:30:49:febtest:INFO: 0-5 | XA-000-08-002-000-001-017-04 | 60.0 | 1165.6
16:30:49:febtest:INFO: 0-6 | XA-000-08-002-000-001-015-03 | 53.6 | 1177.4
16:30:49:febtest:INFO: 0-7 | XA-000-08-002-000-001-016-04 | 76.0 | 1100.2
16:30:49:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:30:53:ST3_smx:INFO: chip: 0-0 56.797143 C 1159.654860 mV
16:30:53:ST3_smx:INFO: Electrons
16:30:53:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:30:54:ST3_smx:INFO: ----> Checking Analog response
16:30:54:ST3_smx:INFO: ----> Checking broken channels
16:30:55:ST3_smx:INFO: Total # broken ch: 2
16:30:55:ST3_smx:INFO: List FAST: [28, 118]
16:30:55:ST3_smx:INFO: List SLOW: []
16:30:55:ST3_smx:INFO: Holes
16:30:55:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:30:57:ST3_smx:INFO: ----> Checking Analog response
16:30:57:ST3_smx:INFO: ----> Checking broken channels
16:30:57:ST3_smx:INFO: Total # broken ch: 2
16:30:57:ST3_smx:INFO: List FAST: [28, 118]
16:30:57:ST3_smx:INFO: List SLOW: []
16:30:57:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:30:57:febtest:INFO: 0-0 | XA-000-08-002-000-001-022-04 | 56.8 | 1159.7
16:30:58:febtest:INFO: 0-1 | XA-000-08-002-000-001-018-04 | 53.6 | 1183.3
16:30:58:febtest:INFO: 0-2 | XA-000-08-002-000-001-025-04 | 63.2 | 1141.9
16:30:58:febtest:INFO: 0-3 | XA-000-08-002-000-001-023-04 | 53.6 | 1177.4
16:30:58:febtest:INFO: 0-4 | XA-000-08-002-000-001-037-13 | 60.0 | 1147.8
16:30:59:febtest:INFO: 0-5 | XA-000-08-002-000-001-020-04 | 66.4 | 1135.9
16:30:59:febtest:INFO: 0-6 | XA-000-08-002-000-001-034-13 | 60.0 | 1165.6
16:30:59:febtest:INFO: 0-7 | XA-000-08-002-000-001-036-13 | 44.1 | 1224.5
16:30:59:febtest:INFO: 0-0 | XA-000-08-002-000-001-021-04 | 56.8 | 1159.7
16:31:00:febtest:INFO: 0-1 | XA-000-08-002-000-002-021-10 | 60.0 | 1153.7
16:31:00:febtest:INFO: 0-2 | XA-000-08-002-000-001-024-04 | 66.4 | 1130.0
16:31:00:febtest:INFO: 0-3 | XA-000-08-002-000-002-019-10 | 56.8 | 1171.5
16:31:00:febtest:INFO: 0-4 | XA-000-08-002-000-001-019-04 | 50.4 | 1183.3
16:31:01:febtest:INFO: 0-5 | XA-000-08-002-000-001-017-04 | 60.0 | 1165.6
16:31:01:febtest:INFO: 0-6 | XA-000-08-002-000-001-015-03 | 53.6 | 1171.5
16:31:01:febtest:INFO: 0-7 | XA-000-08-002-000-001-016-04 | 76.0 | 1100.2
16:31:01:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:31:05:ST3_smx:INFO: chip: 0-1 56.797143 C 1171.483840 mV
16:31:05:ST3_smx:INFO: Electrons
16:31:05:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:31:07:ST3_smx:INFO: ----> Checking Analog response
16:31:07:ST3_smx:INFO: ----> Checking broken channels
16:31:07:ST3_smx:INFO: Total # broken ch: 3
16:31:07:ST3_smx:INFO: List FAST: [0, 21, 95]
16:31:07:ST3_smx:INFO: List SLOW: []
16:31:07:ST3_smx:INFO: Holes
16:31:07:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:31:09:ST3_smx:INFO: ----> Checking Analog response
16:31:09:ST3_smx:INFO: ----> Checking broken channels
16:31:09:ST3_smx:INFO: Total # broken ch: 3
16:31:09:ST3_smx:INFO: List FAST: [0, 21, 95]
16:31:09:ST3_smx:INFO: List SLOW: []
16:31:09:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:31:09:febtest:INFO: 0-0 | XA-000-08-002-000-001-022-04 | 56.8 | 1159.7
16:31:10:febtest:INFO: 0-1 | XA-000-08-002-000-001-018-04 | 60.0 | 1165.6
16:31:10:febtest:INFO: 0-2 | XA-000-08-002-000-001-025-04 | 63.2 | 1141.9
16:31:10:febtest:INFO: 0-3 | XA-000-08-002-000-001-023-04 | 53.6 | 1183.3
16:31:10:febtest:INFO: 0-4 | XA-000-08-002-000-001-037-13 | 60.0 | 1147.8
16:31:11:febtest:INFO: 0-5 | XA-000-08-002-000-001-020-04 | 66.4 | 1141.9
16:31:11:febtest:INFO: 0-6 | XA-000-08-002-000-001-034-13 | 60.0 | 1165.6
16:31:11:febtest:INFO: 0-7 | XA-000-08-002-000-001-036-13 | 44.1 | 1224.5
16:31:11:febtest:INFO: 0-0 | XA-000-08-002-000-001-021-04 | 56.8 | 1159.7
16:31:12:febtest:INFO: 0-1 | XA-000-08-002-000-002-021-10 | 63.2 | 1153.7
16:31:12:febtest:INFO: 0-2 | XA-000-08-002-000-001-024-04 | 66.4 | 1130.0
16:31:12:febtest:INFO: 0-3 | XA-000-08-002-000-002-019-10 | 56.8 | 1171.5
16:31:12:febtest:INFO: 0-4 | XA-000-08-002-000-001-019-04 | 53.6 | 1183.3
16:31:13:febtest:INFO: 0-5 | XA-000-08-002-000-001-017-04 | 60.0 | 1165.6
16:31:13:febtest:INFO: 0-6 | XA-000-08-002-000-001-015-03 | 53.6 | 1177.4
16:31:13:febtest:INFO: 0-7 | XA-000-08-002-000-001-016-04 | 76.0 | 1100.2
16:31:13:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:31:17:ST3_smx:INFO: chip: 0-2 66.365920 C 1135.937260 mV
16:31:17:ST3_smx:INFO: Electrons
16:31:17:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:31:19:ST3_smx:INFO: ----> Checking Analog response
16:31:19:ST3_smx:INFO: ----> Checking broken channels
16:31:19:ST3_smx:INFO: Total # broken ch: 4
16:31:19:ST3_smx:INFO: List FAST: [10, 61, 117, 118]
16:31:19:ST3_smx:INFO: List SLOW: []
16:31:19:ST3_smx:INFO: Holes
16:31:19:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:31:21:ST3_smx:INFO: ----> Checking Analog response
16:31:21:ST3_smx:INFO: ----> Checking broken channels
16:31:21:ST3_smx:INFO: Total # broken ch: 4
16:31:21:ST3_smx:INFO: List FAST: [10, 61, 117, 118]
16:31:21:ST3_smx:INFO: List SLOW: []
16:31:21:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:31:22:febtest:INFO: 0-0 | XA-000-08-002-000-001-022-04 | 56.8 | 1159.7
16:31:22:febtest:INFO: 0-1 | XA-000-08-002-000-001-018-04 | 60.0 | 1165.6
16:31:22:febtest:INFO: 0-2 | XA-000-08-002-000-001-025-04 | 69.6 | 1130.0
16:31:22:febtest:INFO: 0-3 | XA-000-08-002-000-001-023-04 | 53.6 | 1183.3
16:31:23:febtest:INFO: 0-4 | XA-000-08-002-000-001-037-13 | 63.2 | 1147.8
16:31:23:febtest:INFO: 0-5 | XA-000-08-002-000-001-020-04 | 66.4 | 1141.9
16:31:23:febtest:INFO: 0-6 | XA-000-08-002-000-001-034-13 | 60.0 | 1165.6
16:31:23:febtest:INFO: 0-7 | XA-000-08-002-000-001-036-13 | 47.3 | 1224.5
16:31:24:febtest:INFO: 0-0 | XA-000-08-002-000-001-021-04 | 56.8 | 1159.7
16:31:24:febtest:INFO: 0-1 | XA-000-08-002-000-002-021-10 | 63.2 | 1153.7
16:31:24:febtest:INFO: 0-2 | XA-000-08-002-000-001-024-04 | 66.4 | 1130.0
16:31:24:febtest:INFO: 0-3 | XA-000-08-002-000-002-019-10 | 56.8 | 1171.5
16:31:24:febtest:INFO: 0-4 | XA-000-08-002-000-001-019-04 | 53.6 | 1183.3
16:31:25:febtest:INFO: 0-5 | XA-000-08-002-000-001-017-04 | 60.0 | 1165.6
16:31:25:febtest:INFO: 0-6 | XA-000-08-002-000-001-015-03 | 56.8 | 1177.4
16:31:25:febtest:INFO: 0-7 | XA-000-08-002-000-001-016-04 | 76.0 | 1100.2
16:31:25:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:31:29:ST3_smx:INFO: chip: 0-3 63.173842 C 1153.732915 mV
16:31:29:ST3_smx:INFO: Electrons
16:31:29:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:31:31:ST3_smx:INFO: ----> Checking Analog response
16:31:31:ST3_smx:INFO: ----> Checking broken channels
16:31:31:ST3_smx:INFO: Total # broken ch: 5
16:31:31:ST3_smx:INFO: List FAST: [19, 47, 67, 97, 121]
16:31:31:ST3_smx:INFO: List SLOW: []
16:31:31:ST3_smx:INFO: Holes
16:31:31:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:31:33:ST3_smx:INFO: ----> Checking Analog response
16:31:33:ST3_smx:INFO: ----> Checking broken channels
16:31:33:ST3_smx:INFO: Total # broken ch: 5
16:31:33:ST3_smx:INFO: List FAST: [19, 47, 67, 97, 121]
16:31:33:ST3_smx:INFO: List SLOW: []
16:31:33:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:31:34:febtest:INFO: 0-0 | XA-000-08-002-000-001-022-04 | 60.0 | 1159.7
16:31:34:febtest:INFO: 0-1 | XA-000-08-002-000-001-018-04 | 60.0 | 1171.5
16:31:34:febtest:INFO: 0-2 | XA-000-08-002-000-001-025-04 | 69.6 | 1130.0
16:31:34:febtest:INFO: 0-3 | XA-000-08-002-000-001-023-04 | 63.2 | 1153.7
16:31:34:febtest:INFO: 0-4 | XA-000-08-002-000-001-037-13 | 63.2 | 1147.8
16:31:35:febtest:INFO: 0-5 | XA-000-08-002-000-001-020-04 | 69.6 | 1141.9
16:31:35:febtest:INFO: 0-6 | XA-000-08-002-000-001-034-13 | 60.0 | 1165.6
16:31:35:febtest:INFO: 0-7 | XA-000-08-002-000-001-036-13 | 47.3 | 1224.5
16:31:35:febtest:INFO: 0-0 | XA-000-08-002-000-001-021-04 | 56.8 | 1159.7
16:31:36:febtest:INFO: 0-1 | XA-000-08-002-000-002-021-10 | 63.2 | 1153.7
16:31:36:febtest:INFO: 0-2 | XA-000-08-002-000-001-024-04 | 66.4 | 1130.0
16:31:36:febtest:INFO: 0-3 | XA-000-08-002-000-002-019-10 | 56.8 | 1171.5
16:31:36:febtest:INFO: 0-4 | XA-000-08-002-000-001-019-04 | 53.6 | 1183.3
16:31:37:febtest:INFO: 0-5 | XA-000-08-002-000-001-017-04 | 60.0 | 1165.6
16:31:37:febtest:INFO: 0-6 | XA-000-08-002-000-001-015-03 | 53.6 | 1177.4
16:31:37:febtest:INFO: 0-7 | XA-000-08-002-000-001-016-04 | 76.0 | 1100.2
16:31:37:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:31:41:ST3_smx:INFO: chip: 0-4 66.365920 C 1129.995435 mV
16:31:41:ST3_smx:INFO: Electrons
16:31:41:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:31:43:ST3_smx:INFO: ----> Checking Analog response
16:31:43:ST3_smx:INFO: ----> Checking broken channels
16:31:43:ST3_smx:INFO: Total # broken ch: 5
16:31:43:ST3_smx:INFO: List FAST: [41, 45, 80, 84, 127]
16:31:43:ST3_smx:INFO: List SLOW: []
16:31:43:ST3_smx:INFO: Holes
16:31:43:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:31:45:ST3_smx:INFO: ----> Checking Analog response
16:31:45:ST3_smx:INFO: ----> Checking broken channels
16:31:45:ST3_smx:INFO: Total # broken ch: 5
16:31:45:ST3_smx:INFO: List FAST: [41, 45, 80, 84, 127]
16:31:45:ST3_smx:INFO: List SLOW: []
16:31:45:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:31:45:febtest:INFO: 0-0 | XA-000-08-002-000-001-022-04 | 60.0 | 1159.7
16:31:46:febtest:INFO: 0-1 | XA-000-08-002-000-001-018-04 | 60.0 | 1171.5
16:31:46:febtest:INFO: 0-2 | XA-000-08-002-000-001-025-04 | 69.6 | 1130.0
16:31:46:febtest:INFO: 0-3 | XA-000-08-002-000-001-023-04 | 66.4 | 1153.7
16:31:46:febtest:INFO: 0-4 | XA-000-08-002-000-001-037-13 | 69.6 | 1124.0
16:31:47:febtest:INFO: 0-5 | XA-000-08-002-000-001-020-04 | 69.6 | 1141.9
16:31:47:febtest:INFO: 0-6 | XA-000-08-002-000-001-034-13 | 60.0 | 1165.6
16:31:47:febtest:INFO: 0-7 | XA-000-08-002-000-001-036-13 | 47.3 | 1224.5
16:31:47:febtest:INFO: 0-0 | XA-000-08-002-000-001-021-04 | 56.8 | 1159.7
16:31:48:febtest:INFO: 0-1 | XA-000-08-002-000-002-021-10 | 63.2 | 1153.7
16:31:48:febtest:INFO: 0-2 | XA-000-08-002-000-001-024-04 | 66.4 | 1130.0
16:31:48:febtest:INFO: 0-3 | XA-000-08-002-000-002-019-10 | 56.8 | 1171.5
16:31:48:febtest:INFO: 0-4 | XA-000-08-002-000-001-019-04 | 53.6 | 1183.3
16:31:49:febtest:INFO: 0-5 | XA-000-08-002-000-001-017-04 | 60.0 | 1165.6
16:31:49:febtest:INFO: 0-6 | XA-000-08-002-000-001-015-03 | 56.8 | 1171.5
16:31:49:febtest:INFO: 0-7 | XA-000-08-002-000-001-016-04 | 76.0 | 1100.2
16:31:49:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:31:53:ST3_smx:INFO: chip: 0-5 66.365920 C 1147.806000 mV
16:31:53:ST3_smx:INFO: Electrons
16:31:53:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:31:55:ST3_smx:INFO: ----> Checking Analog response
16:31:55:ST3_smx:INFO: ----> Checking broken channels
16:31:55:ST3_smx:INFO: Total # broken ch: 3
16:31:55:ST3_smx:INFO: List FAST: [5, 39, 83]
16:31:55:ST3_smx:INFO: List SLOW: []
16:31:55:ST3_smx:INFO: Holes
16:31:55:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:31:57:ST3_smx:INFO: ----> Checking Analog response
16:31:57:ST3_smx:INFO: ----> Checking broken channels
16:31:57:ST3_smx:INFO: Total # broken ch: 3
16:31:57:ST3_smx:INFO: List FAST: [5, 39, 83]
16:31:57:ST3_smx:INFO: List SLOW: []
16:31:57:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:31:57:febtest:INFO: 0-0 | XA-000-08-002-000-001-022-04 | 60.0 | 1159.7
16:31:58:febtest:INFO: 0-1 | XA-000-08-002-000-001-018-04 | 60.0 | 1171.5
16:31:58:febtest:INFO: 0-2 | XA-000-08-002-000-001-025-04 | 69.6 | 1130.0
16:31:58:febtest:INFO: 0-3 | XA-000-08-002-000-001-023-04 | 66.4 | 1153.7
16:31:58:febtest:INFO: 0-4 | XA-000-08-002-000-001-037-13 | 69.6 | 1124.0
16:31:59:febtest:INFO: 0-5 | XA-000-08-002-000-001-020-04 | 69.6 | 1141.9
16:31:59:febtest:INFO: 0-6 | XA-000-08-002-000-001-034-13 | 60.0 | 1165.6
16:31:59:febtest:INFO: 0-7 | XA-000-08-002-000-001-036-13 | 47.3 | 1224.5
16:31:59:febtest:INFO: 0-0 | XA-000-08-002-000-001-021-04 | 60.0 | 1159.7
16:31:59:febtest:INFO: 0-1 | XA-000-08-002-000-002-021-10 | 63.2 | 1153.7
16:32:00:febtest:INFO: 0-2 | XA-000-08-002-000-001-024-04 | 66.4 | 1130.0
16:32:00:febtest:INFO: 0-3 | XA-000-08-002-000-002-019-10 | 56.8 | 1171.5
16:32:00:febtest:INFO: 0-4 | XA-000-08-002-000-001-019-04 | 53.6 | 1183.3
16:32:00:febtest:INFO: 0-5 | XA-000-08-002-000-001-017-04 | 60.0 | 1165.6
16:32:01:febtest:INFO: 0-6 | XA-000-08-002-000-001-015-03 | 56.8 | 1177.4
16:32:01:febtest:INFO: 0-7 | XA-000-08-002-000-001-016-04 | 76.0 | 1100.2
16:32:01:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:32:05:ST3_smx:INFO: chip: 0-6 69.560482 C 1135.937260 mV
16:32:05:ST3_smx:INFO: Electrons
16:32:05:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:32:07:ST3_smx:INFO: ----> Checking Analog response
16:32:08:ST3_smx:INFO: ----> Checking broken channels
16:32:08:ST3_smx:INFO: Total # broken ch: 1
16:32:08:ST3_smx:INFO: List FAST: [66]
16:32:08:ST3_smx:INFO: List SLOW: []
16:32:08:ST3_smx:INFO: Holes
16:32:08:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:32:10:ST3_smx:INFO: ----> Checking Analog response
16:32:10:ST3_smx:INFO: ----> Checking broken channels
16:32:10:ST3_smx:INFO: Total # broken ch: 1
16:32:10:ST3_smx:INFO: List FAST: [66]
16:32:10:ST3_smx:INFO: List SLOW: []
16:32:10:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:32:10:febtest:INFO: 0-0 | XA-000-08-002-000-001-022-04 | 60.0 | 1159.7
16:32:11:febtest:INFO: 0-1 | XA-000-08-002-000-001-018-04 | 60.0 | 1171.5
16:32:11:febtest:INFO: 0-2 | XA-000-08-002-000-001-025-04 | 69.6 | 1130.0
16:32:11:febtest:INFO: 0-3 | XA-000-08-002-000-001-023-04 | 66.4 | 1153.7
16:32:11:febtest:INFO: 0-4 | XA-000-08-002-000-001-037-13 | 69.6 | 1124.0
16:32:12:febtest:INFO: 0-5 | XA-000-08-002-000-001-020-04 | 69.6 | 1147.8
16:32:12:febtest:INFO: 0-6 | XA-000-08-002-000-001-034-13 | 72.8 | 1130.0
16:32:12:febtest:INFO: 0-7 | XA-000-08-002-000-001-036-13 | 47.3 | 1224.5
16:32:12:febtest:INFO: 0-0 | XA-000-08-002-000-001-021-04 | 56.8 | 1159.7
16:32:13:febtest:INFO: 0-1 | XA-000-08-002-000-002-021-10 | 63.2 | 1153.7
16:32:13:febtest:INFO: 0-2 | XA-000-08-002-000-001-024-04 | 69.6 | 1130.0
16:32:13:febtest:INFO: 0-3 | XA-000-08-002-000-002-019-10 | 56.8 | 1171.5
16:32:14:febtest:INFO: 0-4 | XA-000-08-002-000-001-019-04 | 53.6 | 1183.3
16:32:14:febtest:INFO: 0-5 | XA-000-08-002-000-001-017-04 | 60.0 | 1165.6
16:32:14:febtest:INFO: 0-6 | XA-000-08-002-000-001-015-03 | 56.8 | 1177.4
16:32:14:febtest:INFO: 0-7 | XA-000-08-002-000-001-016-04 | 76.0 | 1100.2
16:32:15:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:32:19:ST3_smx:INFO: chip: 0-7 63.173842 C 1171.483840 mV
16:32:19:ST3_smx:INFO: Electrons
16:32:19:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:32:21:ST3_smx:INFO: ----> Checking Analog response
16:32:21:ST3_smx:INFO: ----> Checking broken channels
16:32:21:ST3_smx:INFO: Total # broken ch: 3
16:32:21:ST3_smx:INFO: List FAST: [19, 65, 121]
16:32:21:ST3_smx:INFO: List SLOW: []
16:32:21:ST3_smx:INFO: Holes
16:32:21:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:32:23:ST3_smx:INFO: ----> Checking Analog response
16:32:23:ST3_smx:INFO: ----> Checking broken channels
16:32:23:ST3_smx:INFO: Total # broken ch: 3
16:32:23:ST3_smx:INFO: List FAST: [19, 65, 121]
16:32:23:ST3_smx:INFO: List SLOW: []
16:32:23:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:32:23:febtest:INFO: 0-0 | XA-000-08-002-000-001-022-04 | 60.0 | 1159.7
16:32:24:febtest:INFO: 0-1 | XA-000-08-002-000-001-018-04 | 60.0 | 1171.5
16:32:24:febtest:INFO: 0-2 | XA-000-08-002-000-001-025-04 | 69.6 | 1130.0
16:32:24:febtest:INFO: 0-3 | XA-000-08-002-000-001-023-04 | 66.4 | 1153.7
16:32:24:febtest:INFO: 0-4 | XA-000-08-002-000-001-037-13 | 69.6 | 1124.0
16:32:24:febtest:INFO: 0-5 | XA-000-08-002-000-001-020-04 | 69.6 | 1147.8
16:32:25:febtest:INFO: 0-6 | XA-000-08-002-000-001-034-13 | 69.6 | 1130.0
16:32:25:febtest:INFO: 0-7 | XA-000-08-002-000-001-036-13 | 63.2 | 1165.6
16:32:25:febtest:INFO: 0-0 | XA-000-08-002-000-001-021-04 | 56.8 | 1159.7
16:32:25:febtest:INFO: 0-1 | XA-000-08-002-000-002-021-10 | 63.2 | 1153.7
16:32:26:febtest:INFO: 0-2 | XA-000-08-002-000-001-024-04 | 69.6 | 1130.0
16:32:26:febtest:INFO: 0-3 | XA-000-08-002-000-002-019-10 | 56.8 | 1171.5
16:32:26:febtest:INFO: 0-4 | XA-000-08-002-000-001-019-04 | 53.6 | 1183.3
16:32:26:febtest:INFO: 0-5 | XA-000-08-002-000-001-017-04 | 63.2 | 1165.6
16:32:26:febtest:INFO: 0-6 | XA-000-08-002-000-001-015-03 | 56.8 | 1177.4
16:32:27:febtest:INFO: 0-7 | XA-000-08-002-000-001-016-04 | 76.0 | 1100.2
16:32:27:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:32:30:ST3_smx:INFO: chip: 0-0 63.173842 C 1147.806000 mV
16:32:30:ST3_smx:INFO: Electrons
16:32:30:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:32:32:ST3_smx:INFO: ----> Checking Analog response
16:32:32:ST3_smx:INFO: ----> Checking broken channels
16:32:33:ST3_smx:INFO: Total # broken ch: 6
16:32:33:ST3_smx:INFO: List FAST: [16, 38, 45, 73, 108, 120]
16:32:33:ST3_smx:INFO: List SLOW: []
16:32:33:ST3_smx:INFO: Holes
16:32:33:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:32:35:ST3_smx:INFO: ----> Checking Analog response
16:32:35:ST3_smx:INFO: ----> Checking broken channels
16:32:35:ST3_smx:INFO: Total # broken ch: 6
16:32:35:ST3_smx:INFO: List FAST: [16, 38, 45, 73, 108, 120]
16:32:35:ST3_smx:INFO: List SLOW: []
16:32:35:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:32:35:febtest:INFO: 0-0 | XA-000-08-002-000-001-022-04 | 60.0 | 1159.7
16:32:36:febtest:INFO: 0-1 | XA-000-08-002-000-001-018-04 | 60.0 | 1171.5
16:32:36:febtest:INFO: 0-2 | XA-000-08-002-000-001-025-04 | 69.6 | 1130.0
16:32:36:febtest:INFO: 0-3 | XA-000-08-002-000-001-023-04 | 66.4 | 1153.7
16:32:36:febtest:INFO: 0-4 | XA-000-08-002-000-001-037-13 | 69.6 | 1124.0
16:32:37:febtest:INFO: 0-5 | XA-000-08-002-000-001-020-04 | 69.6 | 1147.8
16:32:37:febtest:INFO: 0-6 | XA-000-08-002-000-001-034-13 | 72.8 | 1130.0
16:32:37:febtest:INFO: 0-7 | XA-000-08-002-000-001-036-13 | 63.2 | 1165.6
16:32:37:febtest:INFO: 0-0 | XA-000-08-002-000-001-021-04 | 63.2 | 1141.9
16:32:37:febtest:INFO: 0-1 | XA-000-08-002-000-002-021-10 | 63.2 | 1153.7
16:32:38:febtest:INFO: 0-2 | XA-000-08-002-000-001-024-04 | 69.6 | 1130.0
16:32:38:febtest:INFO: 0-3 | XA-000-08-002-000-002-019-10 | 56.8 | 1171.5
16:32:38:febtest:INFO: 0-4 | XA-000-08-002-000-001-019-04 | 56.8 | 1183.3
16:32:38:febtest:INFO: 0-5 | XA-000-08-002-000-001-017-04 | 63.2 | 1165.6
16:32:38:febtest:INFO: 0-6 | XA-000-08-002-000-001-015-03 | 56.8 | 1177.4
16:32:39:febtest:INFO: 0-7 | XA-000-08-002-000-001-016-04 | 79.2 | 1100.2
16:32:39:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:32:43:ST3_smx:INFO: chip: 0-1 66.365920 C 1153.732915 mV
16:32:43:ST3_smx:INFO: Electrons
16:32:43:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:32:45:ST3_smx:INFO: ----> Checking Analog response
16:32:45:ST3_smx:INFO: ----> Checking broken channels
16:32:45:ST3_smx:INFO: Total # broken ch: 3
16:32:45:ST3_smx:INFO: List FAST: [46, 52, 123]
16:32:45:ST3_smx:INFO: List SLOW: []
16:32:45:ST3_smx:INFO: Holes
16:32:45:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:32:47:ST3_smx:INFO: ----> Checking Analog response
16:32:47:ST3_smx:INFO: ----> Checking broken channels
16:32:47:ST3_smx:INFO: Total # broken ch: 3
16:32:47:ST3_smx:INFO: List FAST: [46, 52, 123]
16:32:47:ST3_smx:INFO: List SLOW: []
16:32:47:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:32:48:febtest:INFO: 0-0 | XA-000-08-002-000-001-022-04 | 60.0 | 1159.7
16:32:48:febtest:INFO: 0-1 | XA-000-08-002-000-001-018-04 | 60.0 | 1171.5
16:32:48:febtest:INFO: 0-2 | XA-000-08-002-000-001-025-04 | 69.6 | 1130.0
16:32:48:febtest:INFO: 0-3 | XA-000-08-002-000-001-023-04 | 66.4 | 1153.7
16:32:48:febtest:INFO: 0-4 | XA-000-08-002-000-001-037-13 | 69.6 | 1124.0
16:32:49:febtest:INFO: 0-5 | XA-000-08-002-000-001-020-04 | 69.6 | 1147.8
16:32:49:febtest:INFO: 0-6 | XA-000-08-002-000-001-034-13 | 72.8 | 1130.0
16:32:49:febtest:INFO: 0-7 | XA-000-08-002-000-001-036-13 | 63.2 | 1165.6
16:32:49:febtest:INFO: 0-0 | XA-000-08-002-000-001-021-04 | 63.2 | 1141.9
16:32:49:febtest:INFO: 0-1 | XA-000-08-002-000-002-021-10 | 66.4 | 1147.8
16:32:50:febtest:INFO: 0-2 | XA-000-08-002-000-001-024-04 | 69.6 | 1130.0
16:32:50:febtest:INFO: 0-3 | XA-000-08-002-000-002-019-10 | 60.0 | 1171.5
16:32:50:febtest:INFO: 0-4 | XA-000-08-002-000-001-019-04 | 53.6 | 1183.3
16:32:50:febtest:INFO: 0-5 | XA-000-08-002-000-001-017-04 | 63.2 | 1165.6
16:32:50:febtest:INFO: 0-6 | XA-000-08-002-000-001-015-03 | 56.8 | 1177.4
16:32:51:febtest:INFO: 0-7 | XA-000-08-002-000-001-016-04 | 79.2 | 1100.2
16:32:51:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:32:55:ST3_smx:INFO: chip: 0-2 66.365920 C 1141.874115 mV
16:32:55:ST3_smx:INFO: Electrons
16:32:55:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:32:57:ST3_smx:INFO: ----> Checking Analog response
16:32:57:ST3_smx:INFO: ----> Checking broken channels
16:32:57:ST3_smx:INFO: Total # broken ch: 2
16:32:57:ST3_smx:INFO: List FAST: [18, 98]
16:32:57:ST3_smx:INFO: List SLOW: []
16:32:57:ST3_smx:INFO: Holes
16:32:57:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:32:59:ST3_smx:INFO: ----> Checking Analog response
16:32:59:ST3_smx:INFO: ----> Checking broken channels
16:32:59:ST3_smx:INFO: Total # broken ch: 2
16:32:59:ST3_smx:INFO: List FAST: [18, 98]
16:32:59:ST3_smx:INFO: List SLOW: []
16:32:59:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:32:59:febtest:INFO: 0-0 | XA-000-08-002-000-001-022-04 | 60.0 | 1159.7
16:33:00:febtest:INFO: 0-1 | XA-000-08-002-000-001-018-04 | 60.0 | 1171.5
16:33:00:febtest:INFO: 0-2 | XA-000-08-002-000-001-025-04 | 69.6 | 1130.0
16:33:00:febtest:INFO: 0-3 | XA-000-08-002-000-001-023-04 | 66.4 | 1153.7
16:33:00:febtest:INFO: 0-4 | XA-000-08-002-000-001-037-13 | 69.6 | 1124.0
16:33:01:febtest:INFO: 0-5 | XA-000-08-002-000-001-020-04 | 69.6 | 1147.8
16:33:01:febtest:INFO: 0-6 | XA-000-08-002-000-001-034-13 | 72.8 | 1130.0
16:33:01:febtest:INFO: 0-7 | XA-000-08-002-000-001-036-13 | 63.2 | 1165.6
16:33:01:febtest:INFO: 0-0 | XA-000-08-002-000-001-021-04 | 63.2 | 1141.9
16:33:02:febtest:INFO: 0-1 | XA-000-08-002-000-002-021-10 | 66.4 | 1147.8
16:33:02:febtest:INFO: 0-2 | XA-000-08-002-000-001-024-04 | 66.4 | 1141.9
16:33:02:febtest:INFO: 0-3 | XA-000-08-002-000-002-019-10 | 60.0 | 1171.5
16:33:02:febtest:INFO: 0-4 | XA-000-08-002-000-001-019-04 | 56.8 | 1183.3
16:33:02:febtest:INFO: 0-5 | XA-000-08-002-000-001-017-04 | 63.2 | 1165.6
16:33:03:febtest:INFO: 0-6 | XA-000-08-002-000-001-015-03 | 56.8 | 1177.4
16:33:03:febtest:INFO: 0-7 | XA-000-08-002-000-001-016-04 | 79.2 | 1100.2
16:33:03:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:33:07:ST3_smx:INFO: chip: 0-3 66.365920 C 1147.806000 mV
16:33:07:ST3_smx:INFO: Electrons
16:33:07:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:33:09:ST3_smx:INFO: ----> Checking Analog response
16:33:09:ST3_smx:INFO: ----> Checking broken channels
16:33:09:ST3_smx:INFO: Total # broken ch: 1
16:33:09:ST3_smx:INFO: List FAST: [61]
16:33:09:ST3_smx:INFO: List SLOW: []
16:33:09:ST3_smx:INFO: Holes
16:33:09:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:33:12:ST3_smx:INFO: ----> Checking Analog response
16:33:12:ST3_smx:INFO: ----> Checking broken channels
16:33:12:ST3_smx:INFO: Total # broken ch: 1
16:33:12:ST3_smx:INFO: List FAST: [61]
16:33:12:ST3_smx:INFO: List SLOW: []
16:33:12:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:33:12:febtest:INFO: 0-0 | XA-000-08-002-000-001-022-04 | 60.0 | 1159.7
16:33:13:febtest:INFO: 0-1 | XA-000-08-002-000-001-018-04 | 60.0 | 1171.5
16:33:13:febtest:INFO: 0-2 | XA-000-08-002-000-001-025-04 | 69.6 | 1130.0
16:33:13:febtest:INFO: 0-3 | XA-000-08-002-000-001-023-04 | 66.4 | 1153.7
16:33:13:febtest:INFO: 0-4 | XA-000-08-002-000-001-037-13 | 69.6 | 1124.0
16:33:13:febtest:INFO: 0-5 | XA-000-08-002-000-001-020-04 | 69.6 | 1141.9
16:33:14:febtest:INFO: 0-6 | XA-000-08-002-000-001-034-13 | 72.8 | 1130.0
16:33:14:febtest:INFO: 0-7 | XA-000-08-002-000-001-036-13 | 63.2 | 1165.6
16:33:14:febtest:INFO: 0-0 | XA-000-08-002-000-001-021-04 | 66.4 | 1141.9
16:33:14:febtest:INFO: 0-1 | XA-000-08-002-000-002-021-10 | 66.4 | 1153.7
16:33:14:febtest:INFO: 0-2 | XA-000-08-002-000-001-024-04 | 66.4 | 1141.9
16:33:15:febtest:INFO: 0-3 | XA-000-08-002-000-002-019-10 | 66.4 | 1147.8
16:33:15:febtest:INFO: 0-4 | XA-000-08-002-000-001-019-04 | 53.6 | 1183.3
16:33:15:febtest:INFO: 0-5 | XA-000-08-002-000-001-017-04 | 63.2 | 1165.6
16:33:15:febtest:INFO: 0-6 | XA-000-08-002-000-001-015-03 | 56.8 | 1177.4
16:33:16:febtest:INFO: 0-7 | XA-000-08-002-000-001-016-04 | 79.2 | 1100.2
16:33:16:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:33:20:ST3_smx:INFO: chip: 0-4 53.612520 C 1189.190035 mV
16:33:20:ST3_smx:INFO: Electrons
16:33:20:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:33:22:ST3_smx:INFO: ----> Checking Analog response
16:33:22:ST3_smx:INFO: ----> Checking broken channels
16:33:22:ST3_smx:INFO: Total # broken ch: 3
16:33:22:ST3_smx:INFO: List FAST: [53, 94, 111]
16:33:22:ST3_smx:INFO: List SLOW: []
16:33:22:ST3_smx:INFO: Holes
16:33:22:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:33:25:ST3_smx:INFO: ----> Checking Analog response
16:33:25:ST3_smx:INFO: ----> Checking broken channels
16:33:25:ST3_smx:INFO: Total # broken ch: 3
16:33:25:ST3_smx:INFO: List FAST: [53, 94, 111]
16:33:25:ST3_smx:INFO: List SLOW: []
16:33:25:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:33:25:febtest:INFO: 0-0 | XA-000-08-002-000-001-022-04 | 60.0 | 1159.7
16:33:25:febtest:INFO: 0-1 | XA-000-08-002-000-001-018-04 | 60.0 | 1171.5
16:33:26:febtest:INFO: 0-2 | XA-000-08-002-000-001-025-04 | 69.6 | 1130.0
16:33:26:febtest:INFO: 0-3 | XA-000-08-002-000-001-023-04 | 66.4 | 1153.7
16:33:26:febtest:INFO: 0-4 | XA-000-08-002-000-001-037-13 | 72.8 | 1124.0
16:33:26:febtest:INFO: 0-5 | XA-000-08-002-000-001-020-04 | 69.6 | 1147.8
16:33:27:febtest:INFO: 0-6 | XA-000-08-002-000-001-034-13 | 72.8 | 1130.0
16:33:27:febtest:INFO: 0-7 | XA-000-08-002-000-001-036-13 | 66.4 | 1165.6
16:33:27:febtest:INFO: 0-0 | XA-000-08-002-000-001-021-04 | 66.4 | 1141.9
16:33:27:febtest:INFO: 0-1 | XA-000-08-002-000-002-021-10 | 66.4 | 1147.8
16:33:28:febtest:INFO: 0-2 | XA-000-08-002-000-001-024-04 | 66.4 | 1141.9
16:33:28:febtest:INFO: 0-3 | XA-000-08-002-000-002-019-10 | 66.4 | 1147.8
16:33:28:febtest:INFO: 0-4 | XA-000-08-002-000-001-019-04 | 56.8 | 1183.3
16:33:28:febtest:INFO: 0-5 | XA-000-08-002-000-001-017-04 | 63.2 | 1165.6
16:33:29:febtest:INFO: 0-6 | XA-000-08-002-000-001-015-03 | 56.8 | 1177.4
16:33:29:febtest:INFO: 0-7 | XA-000-08-002-000-001-016-04 | 79.2 | 1100.2
16:33:29:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:33:33:ST3_smx:INFO: chip: 0-5 63.173842 C 1159.654860 mV
16:33:33:ST3_smx:INFO: Electrons
16:33:33:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:33:35:ST3_smx:INFO: ----> Checking Analog response
16:33:35:ST3_smx:INFO: ----> Checking broken channels
16:33:35:ST3_smx:INFO: Total # broken ch: 1
16:33:35:ST3_smx:INFO: List FAST: [93]
16:33:35:ST3_smx:INFO: List SLOW: []
16:33:35:ST3_smx:INFO: Holes
16:33:35:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:33:37:ST3_smx:INFO: ----> Checking Analog response
16:33:37:ST3_smx:INFO: ----> Checking broken channels
16:33:38:ST3_smx:INFO: Total # broken ch: 1
16:33:38:ST3_smx:INFO: List FAST: [93]
16:33:38:ST3_smx:INFO: List SLOW: []
16:33:38:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:33:38:febtest:INFO: 0-0 | XA-000-08-002-000-001-022-04 | 60.0 | 1159.7
16:33:38:febtest:INFO: 0-1 | XA-000-08-002-000-001-018-04 | 60.0 | 1171.5
16:33:38:febtest:INFO: 0-2 | XA-000-08-002-000-001-025-04 | 69.6 | 1130.0
16:33:39:febtest:INFO: 0-3 | XA-000-08-002-000-001-023-04 | 66.4 | 1153.7
16:33:39:febtest:INFO: 0-4 | XA-000-08-002-000-001-037-13 | 69.6 | 1124.0
16:33:39:febtest:INFO: 0-5 | XA-000-08-002-000-001-020-04 | 69.6 | 1141.9
16:33:39:febtest:INFO: 0-6 | XA-000-08-002-000-001-034-13 | 72.8 | 1130.0
16:33:40:febtest:INFO: 0-7 | XA-000-08-002-000-001-036-13 | 66.4 | 1165.6
16:33:40:febtest:INFO: 0-0 | XA-000-08-002-000-001-021-04 | 66.4 | 1141.9
16:33:40:febtest:INFO: 0-1 | XA-000-08-002-000-002-021-10 | 66.4 | 1153.7
16:33:40:febtest:INFO: 0-2 | XA-000-08-002-000-001-024-04 | 66.4 | 1141.9
16:33:41:febtest:INFO: 0-3 | XA-000-08-002-000-002-019-10 | 66.4 | 1147.8
16:33:41:febtest:INFO: 0-4 | XA-000-08-002-000-001-019-04 | 56.8 | 1183.3
16:33:41:febtest:INFO: 0-5 | XA-000-08-002-000-001-017-04 | 63.2 | 1159.7
16:33:41:febtest:INFO: 0-6 | XA-000-08-002-000-001-015-03 | 56.8 | 1177.4
16:33:42:febtest:INFO: 0-7 | XA-000-08-002-000-001-016-04 | 79.2 | 1100.2
16:33:42:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:33:45:ST3_smx:INFO: chip: 0-6 66.365920 C 1135.937260 mV
16:33:45:ST3_smx:INFO: Electrons
16:33:45:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:33:47:ST3_smx:INFO: ----> Checking Analog response
16:33:47:ST3_smx:INFO: ----> Checking broken channels
16:33:48:ST3_smx:INFO: Total # broken ch: 5
16:33:48:ST3_smx:INFO: List FAST: [30, 37, 47, 72, 106]
16:33:48:ST3_smx:INFO: List SLOW: []
16:33:48:ST3_smx:INFO: Holes
16:33:48:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:33:49:ST3_smx:INFO: ----> Checking Analog response
16:33:49:ST3_smx:INFO: ----> Checking broken channels
16:33:50:ST3_smx:INFO: Total # broken ch: 5
16:33:50:ST3_smx:INFO: List FAST: [30, 37, 47, 72, 106]
16:33:50:ST3_smx:INFO: List SLOW: []
16:33:50:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:33:50:febtest:INFO: 0-0 | XA-000-08-002-000-001-022-04 | 60.0 | 1159.7
16:33:50:febtest:INFO: 0-1 | XA-000-08-002-000-001-018-04 | 60.0 | 1171.5
16:33:51:febtest:INFO: 0-2 | XA-000-08-002-000-001-025-04 | 69.6 | 1130.0
16:33:51:febtest:INFO: 0-3 | XA-000-08-002-000-001-023-04 | 66.4 | 1153.7
16:33:51:febtest:INFO: 0-4 | XA-000-08-002-000-001-037-13 | 69.6 | 1124.0
16:33:51:febtest:INFO: 0-5 | XA-000-08-002-000-001-020-04 | 69.6 | 1147.8
16:33:52:febtest:INFO: 0-6 | XA-000-08-002-000-001-034-13 | 72.8 | 1130.0
16:33:52:febtest:INFO: 0-7 | XA-000-08-002-000-001-036-13 | 63.2 | 1171.5
16:33:52:febtest:INFO: 0-0 | XA-000-08-002-000-001-021-04 | 66.4 | 1141.9
16:33:52:febtest:INFO: 0-1 | XA-000-08-002-000-002-021-10 | 66.4 | 1147.8
16:33:53:febtest:INFO: 0-2 | XA-000-08-002-000-001-024-04 | 66.4 | 1141.9
16:33:53:febtest:INFO: 0-3 | XA-000-08-002-000-002-019-10 | 66.4 | 1147.8
16:33:53:febtest:INFO: 0-4 | XA-000-08-002-000-001-019-04 | 56.8 | 1183.3
16:33:53:febtest:INFO: 0-5 | XA-000-08-002-000-001-017-04 | 66.4 | 1159.7
16:33:54:febtest:INFO: 0-6 | XA-000-08-002-000-001-015-03 | 69.6 | 1130.0
16:33:54:febtest:INFO: 0-7 | XA-000-08-002-000-001-016-04 | 79.2 | 1100.2
16:33:54:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:33:58:ST3_smx:INFO: chip: 0-7 75.957063 C 1112.140140 mV
16:33:58:ST3_smx:INFO: Electrons
16:33:58:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:34:00:ST3_smx:INFO: ----> Checking Analog response
16:34:00:ST3_smx:INFO: ----> Checking broken channels
16:34:00:ST3_smx:INFO: Total # broken ch: 3
16:34:00:ST3_smx:INFO: List FAST: [22, 104, 125]
16:34:00:ST3_smx:INFO: List SLOW: []
16:34:00:ST3_smx:INFO: Holes
16:34:00:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:34:02:ST3_smx:INFO: ----> Checking Analog response
16:34:02:ST3_smx:INFO: ----> Checking broken channels
16:34:02:ST3_smx:INFO: Total # broken ch: 3
16:34:02:ST3_smx:INFO: List FAST: [22, 104, 125]
16:34:02:ST3_smx:INFO: List SLOW: []
16:34:02:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:34:03:febtest:INFO: 0-0 | XA-000-08-002-000-001-022-04 | 60.0 | 1159.7
16:34:03:febtest:INFO: 0-1 | XA-000-08-002-000-001-018-04 | 63.2 | 1171.5
16:34:03:febtest:INFO: 0-2 | XA-000-08-002-000-001-025-04 | 69.6 | 1130.0
16:34:03:febtest:INFO: 0-3 | XA-000-08-002-000-001-023-04 | 66.4 | 1153.7
16:34:03:febtest:INFO: 0-4 | XA-000-08-002-000-001-037-13 | 69.6 | 1124.0
16:34:04:febtest:INFO: 0-5 | XA-000-08-002-000-001-020-04 | 69.6 | 1147.8
16:34:04:febtest:INFO: 0-6 | XA-000-08-002-000-001-034-13 | 72.8 | 1130.0
16:34:04:febtest:INFO: 0-7 | XA-000-08-002-000-001-036-13 | 63.2 | 1165.6
16:34:04:febtest:INFO: 0-0 | XA-000-08-002-000-001-021-04 | 66.4 | 1141.9
16:34:05:febtest:INFO: 0-1 | XA-000-08-002-000-002-021-10 | 66.4 | 1147.8
16:34:05:febtest:INFO: 0-2 | XA-000-08-002-000-001-024-04 | 66.4 | 1141.9
16:34:05:febtest:INFO: 0-3 | XA-000-08-002-000-002-019-10 | 66.4 | 1147.8
16:34:05:febtest:INFO: 0-4 | XA-000-08-002-000-001-019-04 | 56.8 | 1183.3
16:34:06:febtest:INFO: 0-5 | XA-000-08-002-000-001-017-04 | 66.4 | 1159.7
16:34:06:febtest:INFO: 0-6 | XA-000-08-002-000-001-015-03 | 69.6 | 1135.9
16:34:06:febtest:INFO: 0-7 | XA-000-08-002-000-001-016-04 | 76.0 | 1106.2
############################################################
# S U M M A R Y #
############################################################
{'TEST_NAME': 'FEB-ASIC', 'TEST_DATE': '2023_11_20-16_30_22', 'OPERATOR': 'Alois Alzheimer', 'PROJECT': 'Production', 'SITE': 'GSI', 'SETUP': 'GSI_TEST_SETUP_1', 'ASIC_ID': 'XA-000-08-002-000-001-016-04', 'FUSED_ID': 6359364699116540164, 'HW_ADDR': 7, 'UPLINK': 24, 'VERS_NO': '2.2', 'CABLE_SET_ID': '', 'IC_TEMP': '0', 'VDDM': '0', 'AUX': '0', 'CSABIAS': '0', 'VDDM_INT': '0', 'ADC_Chi2': 0.0, 'ADC_NDF': 0, 'ADC_P0': 0.0, 'ADC_P1': 0.006824, 'ADC_P2': -2.485e-06, 'ADC_P0err': 0.001, 'ADC_P1err': 0.001, 'ADC_P2err': 1e-05, 'ADC_VREF_P': 58, 'ADC_VREF_N': 30, 'ADC_VREF_T': 128, 'ADC_VREF_TR': 122, 'THR2_GLB': 30, 'LOOP__PLS': 100, 'CALIB_PLS': 250, 'SnsLoop': 5, 'IFED': 31, 'CSA_BIAS': 15, 'CSA_Chi2': 0.0, 'CSA_NDF': 0, 'CSA_P0': 0.0, 'CSA_P1': 0.0, 'CSA_P2': 0.0, 'CSA_P0err': 0.0, 'CSA_P1err': 0.0, 'CSA_P2err': 0.0, 'CONF_FAIL_REG': 0, 'N_BROKEN_DISC': 3, 'N_BROKEN_FAST': '[22, 104, 125]', 'N_BROKEN_SLOW': '[]', 'P_BROKEN_DISC': 3, 'P_BROKEN_FAST': '[22, 104, 125]', 'P_BROKEN_SLOW': '[]', 'ASIC_QA_category': '', 'N_BROKEN_CABLE': 0, 'LIST_OF_BROKEN_CABLES': 0, 'ADDR_0': '', 'ADDR_1': '', 'ADDR_2': '', 'ADDR_3': '', 'ADDR_4': '', 'ADDR_5': '', 'ADDR_6': '', 'ADDR_7': '', 'SENSOR_ID': '', 'MODULE_NAME': '', 'MODULE_LADDER': '', 'MODULE_MODULE': '', 'MODULE_SIZE': '', 'MODULE_GRADE': '', 'MODULE_TYPE': '', 'VI_bInit': ['2.445', '3.8470', '1.842', '4.8970', '7.000', '1.5690', '7.000', '1.5690'], 'VI_aInit': ['0', '0', '0', '0', '0', '0'], 'VI_atEnd': ['0', '0', '0', '0', '0', '0'], 'AMP_CAL': 125, 'PlsLoop': 3, 'N_ANA_PRESENT': 'Analog response OK', 'N_DISC_FAIL_CH': 0, 'N_ANA_FAIL_CH': '0', 'P_ANA_PRESENT': 'Analog response OK', 'P_DISC_FAIL_CH': 0, 'P_ANA_FAIL_CH': '0'}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-ASIC
TEST_DATE : 2023_11_20-16_30_22
OPERATOR : Alois Alzheimer
SITE : GSI
SETUP : GSI_TEST_SETUP_1
Set-ID :
---------------------------------------
MODULE_NAME
---------------------------------------
VI_before_Init : ['2.445', '3.8470', '1.842', '4.8970', '7.000', '1.5690', '7.000', '1.5690']
VI_after__Init : ['2.450', '4.1220', '1.850', '0.6520', '7.000', '1.5630', '7.000', '1.5630']
VI_at__the_End : ['2.450', '4.1220', '1.850', '0.6520', '7.000', '1.5630', '7.000', '1.5630']
16:34:27:ST3_Shared:INFO: /home/cbm/public_html/Production_LogDir//FEB/FEB_2029/TestDate_2023_11_20-16_30_22/