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FEB_2035 01.11.23 13:00:15
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12:50:29:febtest:INFO: FEB 8-2 B @ GSI
12:50:36:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
12:50:36:ST3_Shared:INFO: -------------------------FEB-Sensor-------------------------
12:50:36:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
12:50:37:febtest:INFO: Tsting FEB with SN 2027
12:50:38:smx_tester:INFO: Scanning setup
12:50:38:elinks:INFO: Disabling clock on downlink 0
12:50:38:elinks:INFO: Disabling clock on downlink 1
12:50:38:elinks:INFO: Disabling clock on downlink 2
12:50:38:elinks:INFO: Disabling clock on downlink 3
12:50:38:elinks:INFO: Disabling clock on downlink 4
12:50:38:setup_element:INFO: Checking SOS, encoding_mode: SOS
12:50:38:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
12:50:38:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
12:50:38:elinks:INFO: Disabling clock on downlink 0
12:50:38:elinks:INFO: Disabling clock on downlink 1
12:50:38:elinks:INFO: Disabling clock on downlink 2
12:50:38:elinks:INFO: Disabling clock on downlink 3
12:50:38:elinks:INFO: Disabling clock on downlink 4
12:50:38:setup_element:INFO: Checking SOS, encoding_mode: SOS
12:50:38:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
12:50:38:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
12:50:38:elinks:INFO: Disabling clock on downlink 0
12:50:38:elinks:INFO: Disabling clock on downlink 1
12:50:38:elinks:INFO: Disabling clock on downlink 2
12:50:38:elinks:INFO: Disabling clock on downlink 3
12:50:38:elinks:INFO: Disabling clock on downlink 4
12:50:38:setup_element:INFO: Checking SOS, encoding_mode: SOS
12:50:38:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
12:50:38:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 16
12:50:38:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 17
12:50:38:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 18
12:50:38:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 19
12:50:38:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 20
12:50:38:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 21
12:50:38:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 22
12:50:38:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 23
12:50:38:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24
12:50:38:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25
12:50:38:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26
12:50:38:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27
12:50:38:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28
12:50:38:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29
12:50:38:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30
12:50:38:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31
12:50:38:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
12:50:38:elinks:INFO: Disabling clock on downlink 0
12:50:38:elinks:INFO: Disabling clock on downlink 1
12:50:38:elinks:INFO: Disabling clock on downlink 2
12:50:38:elinks:INFO: Disabling clock on downlink 3
12:50:38:elinks:INFO: Disabling clock on downlink 4
12:50:38:setup_element:INFO: Checking SOS, encoding_mode: SOS
12:50:38:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
12:50:38:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
12:50:38:elinks:INFO: Disabling clock on downlink 0
12:50:38:elinks:INFO: Disabling clock on downlink 1
12:50:38:elinks:INFO: Disabling clock on downlink 2
12:50:38:elinks:INFO: Disabling clock on downlink 3
12:50:38:elinks:INFO: Disabling clock on downlink 4
12:50:38:setup_element:INFO: Checking SOS, encoding_mode: SOS
12:50:38:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
12:50:39:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
12:50:39:setup_element:INFO: Scanning clock phase
12:50:39:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
12:50:39:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
12:50:39:setup_element:INFO: Clock phase scan results for group 0, downlink 2
12:50:39:setup_element:INFO: Eye window for uplink 16: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
12:50:39:setup_element:INFO: Eye window for uplink 17: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
12:50:39:setup_element:INFO: Eye window for uplink 18: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
12:50:39:setup_element:INFO: Eye window for uplink 19: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
12:50:39:setup_element:INFO: Eye window for uplink 20: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
12:50:39:setup_element:INFO: Eye window for uplink 21: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
12:50:39:setup_element:INFO: Eye window for uplink 22: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
12:50:39:setup_element:INFO: Eye window for uplink 23: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
12:50:39:setup_element:INFO: Eye window for uplink 24: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
12:50:39:setup_element:INFO: Eye window for uplink 25: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
12:50:39:setup_element:INFO: Eye window for uplink 26: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
12:50:39:setup_element:INFO: Eye window for uplink 27: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
12:50:39:setup_element:INFO: Eye window for uplink 28: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
12:50:39:setup_element:INFO: Eye window for uplink 29: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
12:50:39:setup_element:INFO: Eye window for uplink 30: ________________________________________________________________________XXXXXXX_
Clock Delay: 35
12:50:39:setup_element:INFO: Eye window for uplink 31: ________________________________________________________________________XXXXXXX_
Clock Delay: 35
12:50:39:setup_element:INFO: Setting the clock phase to 33 for group 0, downlink 2
12:50:39:setup_element:INFO: Scanning data phases
12:50:39:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
12:50:39:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
12:50:45:setup_element:INFO: Data phase scan results for group 0, downlink 2
12:50:45:setup_element:INFO: Eye window for uplink 16: X___________________________________XXXX
Data delay found: 18
12:50:45:setup_element:INFO: Eye window for uplink 17: ________________________________XXXX____
Data delay found: 13
12:50:45:setup_element:INFO: Eye window for uplink 18: XX_________________________________XXXXX
Data delay found: 18
12:50:45:setup_element:INFO: Eye window for uplink 19: _________________________________XXXXX__
Data delay found: 15
12:50:45:setup_element:INFO: Eye window for uplink 20: XX__________________________________XXXX
Data delay found: 18
12:50:45:setup_element:INFO: Eye window for uplink 21: X__________________________________XXXXX
Data delay found: 17
12:50:45:setup_element:INFO: Eye window for uplink 22: X__________________________________XXXXX
Data delay found: 17
12:50:45:setup_element:INFO: Eye window for uplink 23: _________________________________XXXXX__
Data delay found: 15
12:50:45:setup_element:INFO: Eye window for uplink 24: _____XXXXXX_____________________________
Data delay found: 27
12:50:45:setup_element:INFO: Eye window for uplink 25: ________XXXXX___________________________
Data delay found: 30
12:50:45:setup_element:INFO: Eye window for uplink 26: ____XXXXX_______________________________
Data delay found: 26
12:50:45:setup_element:INFO: Eye window for uplink 27: _______XXXXX____________________________
Data delay found: 29
12:50:45:setup_element:INFO: Eye window for uplink 28: _________XXXXX__________________________
Data delay found: 31
12:50:45:setup_element:INFO: Eye window for uplink 29: ___________XXXXX________________________
Data delay found: 33
12:50:45:setup_element:INFO: Eye window for uplink 30: _____________XXXXXXX____________________
Data delay found: 36
12:50:45:setup_element:INFO: Eye window for uplink 31: ____________XXXXX_______________________
Data delay found: 34
12:50:45:setup_element:INFO: Setting the data phase to 18 for uplink 16
12:50:45:setup_element:INFO: Setting the data phase to 13 for uplink 17
12:50:45:setup_element:INFO: Setting the data phase to 18 for uplink 18
12:50:45:setup_element:INFO: Setting the data phase to 15 for uplink 19
12:50:45:setup_element:INFO: Setting the data phase to 18 for uplink 20
12:50:45:setup_element:INFO: Setting the data phase to 17 for uplink 21
12:50:45:setup_element:INFO: Setting the data phase to 17 for uplink 22
12:50:45:setup_element:INFO: Setting the data phase to 15 for uplink 23
12:50:45:setup_element:INFO: Setting the data phase to 27 for uplink 24
12:50:45:setup_element:INFO: Setting the data phase to 30 for uplink 25
12:50:45:setup_element:INFO: Setting the data phase to 26 for uplink 26
12:50:45:setup_element:INFO: Setting the data phase to 29 for uplink 27
12:50:45:setup_element:INFO: Setting the data phase to 31 for uplink 28
12:50:45:setup_element:INFO: Setting the data phase to 33 for uplink 29
12:50:45:setup_element:INFO: Setting the data phase to 36 for uplink 30
12:50:45:setup_element:INFO: Setting the data phase to 34 for uplink 31
12:50:45:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 33
Window Length: 70
Eye Windows:
Uplink 16: _______________________________________________________________________XXXXXXX__
Uplink 17: _______________________________________________________________________XXXXXXX__
Uplink 18: _______________________________________________________________________XXXXXXXX_
Uplink 19: _______________________________________________________________________XXXXXXXX_
Uplink 20: _______________________________________________________________________XXXXXXXX_
Uplink 21: _______________________________________________________________________XXXXXXXX_
Uplink 22: ______________________________________________________________________XXXXXXXX__
Uplink 23: ______________________________________________________________________XXXXXXXX__
Uplink 24: _______________________________________________________________________XXXXXXXX_
Uplink 25: _______________________________________________________________________XXXXXXXX_
Uplink 26: _____________________________________________________________________XXXXXXXX___
Uplink 27: _____________________________________________________________________XXXXXXXX___
Uplink 28: ______________________________________________________________________XXXXXXXX__
Uplink 29: ______________________________________________________________________XXXXXXXX__
Uplink 30: ________________________________________________________________________XXXXXXX_
Uplink 31: ________________________________________________________________________XXXXXXX_
Data phase characteristics:
Uplink 16:
Optimal Phase: 18
Window Length: 35
Eye Window: X___________________________________XXXX
Uplink 17:
Optimal Phase: 13
Window Length: 36
Eye Window: ________________________________XXXX____
Uplink 18:
Optimal Phase: 18
Window Length: 33
Eye Window: XX_________________________________XXXXX
Uplink 19:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
Uplink 20:
Optimal Phase: 18
Window Length: 34
Eye Window: XX__________________________________XXXX
Uplink 21:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXXX
Uplink 22:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXXX
Uplink 23:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
Uplink 24:
Optimal Phase: 27
Window Length: 34
Eye Window: _____XXXXXX_____________________________
Uplink 25:
Optimal Phase: 30
Window Length: 35
Eye Window: ________XXXXX___________________________
Uplink 26:
Optimal Phase: 26
Window Length: 35
Eye Window: ____XXXXX_______________________________
Uplink 27:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 28:
Optimal Phase: 31
Window Length: 35
Eye Window: _________XXXXX__________________________
Uplink 29:
Optimal Phase: 33
Window Length: 35
Eye Window: ___________XXXXX________________________
Uplink 30:
Optimal Phase: 36
Window Length: 33
Eye Window: _____________XXXXXXX____________________
Uplink 31:
Optimal Phase: 34
Window Length: 35
Eye Window: ____________XXXXX_______________________
]
12:50:45:setup_element:INFO: Beginning SMX ASICs map scan
12:50:45:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
12:50:45:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
12:50:45:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
12:50:45:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
12:50:45:uplink:INFO: Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
12:50:45:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 23
12:50:45:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 22
12:50:45:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 30
12:50:45:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 31
12:50:45:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 21
12:50:45:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 20
12:50:45:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28
12:50:45:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 29
12:50:45:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 19
12:50:45:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 18
12:50:46:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26
12:50:46:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 27
12:50:46:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 17
12:50:46:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 16
12:50:46:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 24
12:50:46:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 25
12:50:47:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 23), (1, 22)
ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
ASIC address 0x2: (ASIC uplink, uplink): (0, 21), (1, 20)
ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
ASIC address 0x4: (ASIC uplink, uplink): (0, 19), (1, 18)
ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
ASIC address 0x6: (ASIC uplink, uplink): (0, 17), (1, 16)
ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
Clock Phase Characteristic:
Optimal Phase: 33
Window Length: 70
Eye Windows:
Uplink 16: _______________________________________________________________________XXXXXXX__
Uplink 17: _______________________________________________________________________XXXXXXX__
Uplink 18: _______________________________________________________________________XXXXXXXX_
Uplink 19: _______________________________________________________________________XXXXXXXX_
Uplink 20: _______________________________________________________________________XXXXXXXX_
Uplink 21: _______________________________________________________________________XXXXXXXX_
Uplink 22: ______________________________________________________________________XXXXXXXX__
Uplink 23: ______________________________________________________________________XXXXXXXX__
Uplink 24: _______________________________________________________________________XXXXXXXX_
Uplink 25: _______________________________________________________________________XXXXXXXX_
Uplink 26: _____________________________________________________________________XXXXXXXX___
Uplink 27: _____________________________________________________________________XXXXXXXX___
Uplink 28: ______________________________________________________________________XXXXXXXX__
Uplink 29: ______________________________________________________________________XXXXXXXX__
Uplink 30: ________________________________________________________________________XXXXXXX_
Uplink 31: ________________________________________________________________________XXXXXXX_
Data phase characteristics:
Uplink 16:
Optimal Phase: 18
Window Length: 35
Eye Window: X___________________________________XXXX
Uplink 17:
Optimal Phase: 13
Window Length: 36
Eye Window: ________________________________XXXX____
Uplink 18:
Optimal Phase: 18
Window Length: 33
Eye Window: XX_________________________________XXXXX
Uplink 19:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
Uplink 20:
Optimal Phase: 18
Window Length: 34
Eye Window: XX__________________________________XXXX
Uplink 21:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXXX
Uplink 22:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXXX
Uplink 23:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
Uplink 24:
Optimal Phase: 27
Window Length: 34
Eye Window: _____XXXXXX_____________________________
Uplink 25:
Optimal Phase: 30
Window Length: 35
Eye Window: ________XXXXX___________________________
Uplink 26:
Optimal Phase: 26
Window Length: 35
Eye Window: ____XXXXX_______________________________
Uplink 27:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 28:
Optimal Phase: 31
Window Length: 35
Eye Window: _________XXXXX__________________________
Uplink 29:
Optimal Phase: 33
Window Length: 35
Eye Window: ___________XXXXX________________________
Uplink 30:
Optimal Phase: 36
Window Length: 33
Eye Window: _____________XXXXXXX____________________
Uplink 31:
Optimal Phase: 34
Window Length: 35
Eye Window: ____________XXXXX_______________________
12:50:47:setup_element:INFO: Performing Elink synchronization
12:50:47:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
12:50:47:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
12:50:47:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
12:50:47:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
12:50:47:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2
12:50:47:uplink:INFO: Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
12:50:48:ST3_emu:INFO: Number of chips: 8
12:50:48:ST3_emu:INFO: Chip address: 0x0
12:50:48:ST3_emu:INFO: Chip address: 0x1
12:50:48:ST3_emu:INFO: Chip address: 0x2
12:50:48:ST3_emu:INFO: Chip address: 0x3
12:50:48:ST3_emu:INFO: Chip address: 0x4
12:50:48:ST3_emu:INFO: Chip address: 0x5
12:50:48:ST3_emu:INFO: Chip address: 0x6
12:50:48:ST3_emu:INFO: Chip address: 0x7
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_h_0 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_h_0 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_h_0 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_h_0 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_h_0 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_h_0 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_e_0 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_e_0 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_e_0 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_e_0 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_e_0 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_e_0 (Potential memory leak).
TCanvas::Constructor:0: RuntimeWarning: Deleting canvas with same name: cDist_0
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_h_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_h_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_h_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_h_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_h_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_h_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_e_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_e_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_e_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_e_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_e_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_e_1 (Potential memory leak).
TCanvas::Constructor:0: RuntimeWarning: Deleting canvas with same name: cDist_1
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_h_2 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_h_2 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_h_2 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_h_2 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_h_2 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_h_2 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_e_2 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_e_2 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_e_2 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_e_2 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_e_2 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_e_2 (Potential memory leak).
TCanvas::Constructor:0: RuntimeWarning: Deleting canvas with same name: cDist_2
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_h_3 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_h_3 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_h_3 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_h_3 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_h_3 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_h_3 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_e_3 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_e_3 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_e_3 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_e_3 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_e_3 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_e_3 (Potential memory leak).
TCanvas::Constructor:0: RuntimeWarning: Deleting canvas with same name: cDist_3
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_h_4 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_h_4 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_h_4 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_h_4 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_h_4 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_h_4 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_e_4 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_e_4 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_e_4 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_e_4 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_e_4 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_e_4 (Potential memory leak).
TCanvas::Constructor:0: RuntimeWarning: Deleting canvas with same name: cDist_4
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_h_5 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_h_5 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_h_5 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_h_5 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_h_5 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_h_5 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_e_5 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_e_5 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_e_5 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_e_5 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_e_5 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_e_5 (Potential memory leak).
TCanvas::Constructor:0: RuntimeWarning: Deleting canvas with same name: cDist_5
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_h_6 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_h_6 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_h_6 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_h_6 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_h_6 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_h_6 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_e_6 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_e_6 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_e_6 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_e_6 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_e_6 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_e_6 (Potential memory leak).
TCanvas::Constructor:0: RuntimeWarning: Deleting canvas with same name: cDist_6
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_h_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_h_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_h_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_h_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_h_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_h_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_e_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_e_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_e_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_e_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_e_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_e_7 (Potential memory leak).
TCanvas::Constructor:0: RuntimeWarning: Deleting canvas with same name: cDist_7
12:50:48:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
12:50:49:febtest:INFO: 0-0 | XA-000-08-002-000-001-221-11 | 37.7 | 1171.5
12:50:49:febtest:INFO: 0-1 | XA-000-08-001-064-050-160-13 | 34.6 | 1195.1
12:50:49:febtest:INFO: 0-2 | XA-000-08-002-000-001-045-13 | 40.9 | 1171.5
12:50:49:febtest:INFO: 0-3 | XA-000-08-001-064-051-128-14 | 44.1 | 1153.7
12:50:50:febtest:INFO: 0-4 | XA-000-08-001-064-051-080-06 | 31.4 | 1195.1
12:50:50:febtest:INFO: 0-5 | XA-000-08-001-064-051-136-14 | 34.6 | 1189.2
12:50:50:febtest:INFO: 0-6 | XA-000-08-001-064-051-088-06 | 31.4 | 1189.2
12:50:50:febtest:INFO: 0-7 | XA-000-08-001-064-051-184-07 | 40.9 | 1171.5
12:50:50:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
12:50:54:ST3_smx:INFO: chip: 0-0 40.898880 C 1159.654860 mV
12:50:54:ST3_smx:INFO: # loops 0
12:50:56:ST3_smx:INFO: # loops 1
12:50:57:ST3_smx:INFO: # loops 2
12:50:59:ST3_smx:INFO: # loops 3
12:51:01:ST3_smx:INFO: # loops 4
12:51:02:ST3_smx:INFO: Total # of broken channels: 0
12:51:02:ST3_smx:INFO: List of broken channels: []
12:51:02:ST3_smx:INFO: Total # of broken channels: 0
12:51:02:ST3_smx:INFO: List of broken channels: []
12:51:03:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
12:51:07:ST3_smx:INFO: chip: 0-1 37.726682 C 1171.483840 mV
12:51:07:ST3_smx:INFO: # loops 0
12:51:08:ST3_smx:INFO: # loops 1
12:51:10:ST3_smx:INFO: # loops 2
12:51:12:ST3_smx:INFO: # loops 3
12:51:13:ST3_smx:INFO: # loops 4
12:51:15:ST3_smx:INFO: Total # of broken channels: 0
12:51:15:ST3_smx:INFO: List of broken channels: []
12:51:15:ST3_smx:INFO: Total # of broken channels: 0
12:51:15:ST3_smx:INFO: List of broken channels: []
12:51:16:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
12:51:19:ST3_smx:INFO: chip: 0-2 50.430383 C 1124.048640 mV
12:51:20:ST3_smx:INFO: # loops 0
12:51:21:ST3_smx:INFO: # loops 1
12:51:23:ST3_smx:INFO: # loops 2
12:51:25:ST3_smx:INFO: # loops 3
12:51:26:ST3_smx:INFO: # loops 4
12:51:28:ST3_smx:INFO: Total # of broken channels: 0
12:51:28:ST3_smx:INFO: List of broken channels: []
12:51:28:ST3_smx:INFO: Total # of broken channels: 0
12:51:28:ST3_smx:INFO: List of broken channels: []
12:51:29:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
12:51:32:ST3_smx:INFO: chip: 0-3 44.073563 C 1141.874115 mV
12:51:32:ST3_smx:INFO: # loops 0
12:51:34:ST3_smx:INFO: # loops 1
12:51:36:ST3_smx:INFO: # loops 2
12:51:37:ST3_smx:INFO: # loops 3
12:51:39:ST3_smx:INFO: # loops 4
12:51:41:ST3_smx:INFO: Total # of broken channels: 0
12:51:41:ST3_smx:INFO: List of broken channels: []
12:51:41:ST3_smx:INFO: Total # of broken channels: 0
12:51:41:ST3_smx:INFO: List of broken channels: []
12:51:41:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
12:51:45:ST3_smx:INFO: chip: 0-4 44.073563 C 1153.732915 mV
12:51:45:ST3_smx:INFO: # loops 0
12:51:47:ST3_smx:INFO: # loops 1
12:51:49:ST3_smx:INFO: # loops 2
12:51:51:ST3_smx:INFO: # loops 3
12:51:52:ST3_smx:INFO: # loops 4
12:51:54:ST3_smx:INFO: Total # of broken channels: 0
12:51:54:ST3_smx:INFO: List of broken channels: []
12:51:54:ST3_smx:INFO: Total # of broken channels: 0
12:51:54:ST3_smx:INFO: List of broken channels: []
12:51:55:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
12:51:58:ST3_smx:INFO: chip: 0-5 40.898880 C 1159.654860 mV
12:51:58:ST3_smx:INFO: # loops 0
12:52:00:ST3_smx:INFO: # loops 1
12:52:02:ST3_smx:INFO: # loops 2
12:52:04:ST3_smx:INFO: # loops 3
12:52:05:ST3_smx:INFO: # loops 4
12:52:07:ST3_smx:INFO: Total # of broken channels: 0
12:52:07:ST3_smx:INFO: List of broken channels: []
12:52:07:ST3_smx:INFO: Total # of broken channels: 0
12:52:07:ST3_smx:INFO: List of broken channels: []
12:52:08:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
12:52:11:ST3_smx:INFO: chip: 0-6 44.073563 C 1147.806000 mV
12:52:11:ST3_smx:INFO: # loops 0
12:52:13:ST3_smx:INFO: # loops 1
12:52:15:ST3_smx:INFO: # loops 2
12:52:17:ST3_smx:INFO: # loops 3
12:52:18:ST3_smx:INFO: # loops 4
12:52:20:ST3_smx:INFO: Total # of broken channels: 1
12:52:20:ST3_smx:INFO: List of broken channels: [1]
12:52:20:ST3_smx:INFO: Total # of broken channels: 1
12:52:20:ST3_smx:INFO: List of broken channels: [1]
12:52:20:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
12:52:24:ST3_smx:INFO: chip: 0-7 40.898880 C 1159.654860 mV
12:52:24:ST3_smx:INFO: # loops 0
12:52:26:ST3_smx:INFO: # loops 1
12:52:27:ST3_smx:INFO: # loops 2
12:52:29:ST3_smx:INFO: # loops 3
12:52:31:ST3_smx:INFO: # loops 4
12:52:32:ST3_smx:INFO: Total # of broken channels: 0
12:52:32:ST3_smx:INFO: List of broken channels: []
12:52:32:ST3_smx:INFO: Total # of broken channels: 1
12:52:32:ST3_smx:INFO: List of broken channels: [75]
12:52:33:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
12:52:33:febtest:INFO: 0-0 | XA-000-08-002-000-001-221-11 | 44.1 | 1147.8
12:52:33:febtest:INFO: 0-1 | XA-000-08-001-064-050-160-13 | 44.1 | 1159.7
12:52:34:febtest:INFO: 0-2 | XA-000-08-002-000-001-045-13 | 56.8 | 1118.1
12:52:34:febtest:INFO: 0-3 | XA-000-08-001-064-051-128-14 | 47.3 | 1135.9
12:52:34:febtest:INFO: 0-4 | XA-000-08-001-064-051-080-06 | 47.3 | 1141.9
12:52:34:febtest:INFO: 0-5 | XA-000-08-001-064-051-136-14 | 40.9 | 1159.7
12:52:34:febtest:INFO: 0-6 | XA-000-08-001-064-051-088-06 | 47.3 | 1147.8
12:52:35:febtest:INFO: 0-7 | XA-000-08-001-064-051-184-07 | 40.9 | 1153.7
12:52:45:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
12:52:45:ST3_Shared:INFO: -------------------------FEB-Sensor-------------------------
12:52:45:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
12:52:45:febtest:INFO: Tsting FEB with SN 2027
12:52:47:smx_tester:INFO: Scanning setup
12:52:47:elinks:INFO: Disabling clock on downlink 0
12:52:47:elinks:INFO: Disabling clock on downlink 1
12:52:47:elinks:INFO: Disabling clock on downlink 2
12:52:47:elinks:INFO: Disabling clock on downlink 3
12:52:47:elinks:INFO: Disabling clock on downlink 4
12:52:47:setup_element:INFO: Checking SOS, encoding_mode: SOS
12:52:47:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
12:52:47:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
12:52:47:elinks:INFO: Disabling clock on downlink 0
12:52:47:elinks:INFO: Disabling clock on downlink 1
12:52:47:elinks:INFO: Disabling clock on downlink 2
12:52:47:elinks:INFO: Disabling clock on downlink 3
12:52:47:elinks:INFO: Disabling clock on downlink 4
12:52:47:setup_element:INFO: Checking SOS, encoding_mode: SOS
12:52:47:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
12:52:47:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
12:52:47:elinks:INFO: Disabling clock on downlink 0
12:52:47:elinks:INFO: Disabling clock on downlink 1
12:52:47:elinks:INFO: Disabling clock on downlink 2
12:52:47:elinks:INFO: Disabling clock on downlink 3
12:52:47:elinks:INFO: Disabling clock on downlink 4
12:52:47:setup_element:INFO: Checking SOS, encoding_mode: SOS
12:52:47:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
12:52:47:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 16
12:52:47:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 17
12:52:47:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 18
12:52:47:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 19
12:52:47:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 20
12:52:47:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 21
12:52:47:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 22
12:52:47:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 23
12:52:47:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24
12:52:47:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25
12:52:47:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26
12:52:47:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27
12:52:47:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28
12:52:47:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29
12:52:47:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30
12:52:47:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31
12:52:47:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
12:52:47:elinks:INFO: Disabling clock on downlink 0
12:52:47:elinks:INFO: Disabling clock on downlink 1
12:52:47:elinks:INFO: Disabling clock on downlink 2
12:52:47:elinks:INFO: Disabling clock on downlink 3
12:52:47:elinks:INFO: Disabling clock on downlink 4
12:52:47:setup_element:INFO: Checking SOS, encoding_mode: SOS
12:52:47:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
12:52:47:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
12:52:47:elinks:INFO: Disabling clock on downlink 0
12:52:47:elinks:INFO: Disabling clock on downlink 1
12:52:47:elinks:INFO: Disabling clock on downlink 2
12:52:47:elinks:INFO: Disabling clock on downlink 3
12:52:47:elinks:INFO: Disabling clock on downlink 4
12:52:47:setup_element:INFO: Checking SOS, encoding_mode: SOS
12:52:47:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
12:52:47:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
12:52:47:setup_element:INFO: Scanning clock phase
12:52:47:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
12:52:47:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
12:52:48:setup_element:INFO: Clock phase scan results for group 0, downlink 2
12:52:48:setup_element:INFO: Eye window for uplink 16: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
12:52:48:setup_element:INFO: Eye window for uplink 17: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
12:52:48:setup_element:INFO: Eye window for uplink 18: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
12:52:48:setup_element:INFO: Eye window for uplink 19: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
12:52:48:setup_element:INFO: Eye window for uplink 20: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
12:52:48:setup_element:INFO: Eye window for uplink 21: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
12:52:48:setup_element:INFO: Eye window for uplink 22: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
12:52:48:setup_element:INFO: Eye window for uplink 23: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
12:52:48:setup_element:INFO: Eye window for uplink 24: ______________________________________________________________________XXXXXXXXX_
Clock Delay: 34
12:52:48:setup_element:INFO: Eye window for uplink 25: ______________________________________________________________________XXXXXXXXX_
Clock Delay: 34
12:52:48:setup_element:INFO: Eye window for uplink 26: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
12:52:48:setup_element:INFO: Eye window for uplink 27: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
12:52:48:setup_element:INFO: Eye window for uplink 28: _____________________________________________________________________XXXXXXXXX__
Clock Delay: 33
12:52:48:setup_element:INFO: Eye window for uplink 29: _____________________________________________________________________XXXXXXXXX__
Clock Delay: 33
12:52:48:setup_element:INFO: Eye window for uplink 30: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
12:52:48:setup_element:INFO: Eye window for uplink 31: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
12:52:48:setup_element:INFO: Setting the clock phase to 33 for group 0, downlink 2
12:52:48:setup_element:INFO: Scanning data phases
12:52:48:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
12:52:48:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
12:52:53:setup_element:INFO: Data phase scan results for group 0, downlink 2
12:52:53:setup_element:INFO: Eye window for uplink 16: ___________________________________XXXX_
Data delay found: 16
12:52:53:setup_element:INFO: Eye window for uplink 17: _______________________________XXXXX____
Data delay found: 13
12:52:53:setup_element:INFO: Eye window for uplink 18: X__________________________________XXXXX
Data delay found: 17
12:52:53:setup_element:INFO: Eye window for uplink 19: ________________________________XXXXX___
Data delay found: 14
12:52:53:setup_element:INFO: Eye window for uplink 20: X___________________________________XXXX
Data delay found: 18
12:52:53:setup_element:INFO: Eye window for uplink 21: __________________________________XXXXXX
Data delay found: 16
12:52:53:setup_element:INFO: Eye window for uplink 22: ___________________________________XXXX_
Data delay found: 16
12:52:53:setup_element:INFO: Eye window for uplink 23: _________________________________XXXX___
Data delay found: 14
12:52:53:setup_element:INFO: Eye window for uplink 24: ____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Data delay found: 1
12:52:53:setup_element:INFO: Eye window for uplink 25: ______XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Data delay found: 2
12:52:53:setup_element:INFO: Eye window for uplink 26: ___XXXXXX_______________________________
Data delay found: 25
12:52:53:setup_element:INFO: Eye window for uplink 27: _______XXXXXX___________________________
Data delay found: 29
12:52:53:setup_element:INFO: Eye window for uplink 28: _________XXXXXX_________________________
Data delay found: 31
12:52:53:setup_element:INFO: Eye window for uplink 29: ___________XXXXXX_______________________
Data delay found: 33
12:52:53:setup_element:INFO: Eye window for uplink 30: _____________XXXXXX_____________________
Data delay found: 35
12:52:53:setup_element:INFO: Eye window for uplink 31: ____________XXXXX_______________________
Data delay found: 34
12:52:53:setup_element:INFO: Setting the data phase to 16 for uplink 16
12:52:53:setup_element:INFO: Setting the data phase to 13 for uplink 17
12:52:53:setup_element:INFO: Setting the data phase to 17 for uplink 18
12:52:53:setup_element:INFO: Setting the data phase to 14 for uplink 19
12:52:53:setup_element:INFO: Setting the data phase to 18 for uplink 20
12:52:53:setup_element:INFO: Setting the data phase to 16 for uplink 21
12:52:53:setup_element:INFO: Setting the data phase to 16 for uplink 22
12:52:53:setup_element:INFO: Setting the data phase to 14 for uplink 23
12:52:53:setup_element:INFO: Setting the data phase to 1 for uplink 24
12:52:53:setup_element:INFO: Setting the data phase to 2 for uplink 25
12:52:53:setup_element:INFO: Setting the data phase to 25 for uplink 26
12:52:53:setup_element:INFO: Setting the data phase to 29 for uplink 27
12:52:53:setup_element:INFO: Setting the data phase to 31 for uplink 28
12:52:53:setup_element:INFO: Setting the data phase to 33 for uplink 29
12:52:53:setup_element:INFO: Setting the data phase to 35 for uplink 30
12:52:53:setup_element:INFO: Setting the data phase to 34 for uplink 31
12:52:53:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 33
Window Length: 70
Eye Windows:
Uplink 16: _______________________________________________________________________XXXXXXX__
Uplink 17: _______________________________________________________________________XXXXXXX__
Uplink 18: _______________________________________________________________________XXXXXXX__
Uplink 19: _______________________________________________________________________XXXXXXX__
Uplink 20: _______________________________________________________________________XXXXXXXX_
Uplink 21: _______________________________________________________________________XXXXXXXX_
Uplink 22: ______________________________________________________________________XXXXXXXX__
Uplink 23: ______________________________________________________________________XXXXXXXX__
Uplink 24: ______________________________________________________________________XXXXXXXXX_
Uplink 25: ______________________________________________________________________XXXXXXXXX_
Uplink 26: _____________________________________________________________________XXXXXXXX___
Uplink 27: _____________________________________________________________________XXXXXXXX___
Uplink 28: _____________________________________________________________________XXXXXXXXX__
Uplink 29: _____________________________________________________________________XXXXXXXXX__
Uplink 30: _______________________________________________________________________XXXXXXX__
Uplink 31: _______________________________________________________________________XXXXXXX__
Data phase characteristics:
Uplink 16:
Optimal Phase: 16
Window Length: 36
Eye Window: ___________________________________XXXX_
Uplink 17:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 18:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXXX
Uplink 19:
Optimal Phase: 14
Window Length: 35
Eye Window: ________________________________XXXXX___
Uplink 20:
Optimal Phase: 18
Window Length: 35
Eye Window: X___________________________________XXXX
Uplink 21:
Optimal Phase: 16
Window Length: 34
Eye Window: __________________________________XXXXXX
Uplink 22:
Optimal Phase: 16
Window Length: 36
Eye Window: ___________________________________XXXX_
Uplink 23:
Optimal Phase: 14
Window Length: 36
Eye Window: _________________________________XXXX___
Uplink 24:
Optimal Phase: 1
Window Length: 4
Eye Window: ____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Uplink 25:
Optimal Phase: 2
Window Length: 6
Eye Window: ______XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Uplink 26:
Optimal Phase: 25
Window Length: 34
Eye Window: ___XXXXXX_______________________________
Uplink 27:
Optimal Phase: 29
Window Length: 34
Eye Window: _______XXXXXX___________________________
Uplink 28:
Optimal Phase: 31
Window Length: 34
Eye Window: _________XXXXXX_________________________
Uplink 29:
Optimal Phase: 33
Window Length: 34
Eye Window: ___________XXXXXX_______________________
Uplink 30:
Optimal Phase: 35
Window Length: 34
Eye Window: _____________XXXXXX_____________________
Uplink 31:
Optimal Phase: 34
Window Length: 35
Eye Window: ____________XXXXX_______________________
]
12:52:53:setup_element:INFO: Beginning SMX ASICs map scan
12:52:53:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
12:52:53:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
12:52:53:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
12:52:53:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
12:52:53:uplink:INFO: Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
12:52:53:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 23
12:52:53:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 22
12:52:53:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 30
12:52:53:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 31
12:52:53:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 21
12:52:53:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 20
12:52:53:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28
12:52:54:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 29
12:52:54:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 19
12:52:54:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 18
12:52:54:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26
12:52:54:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 27
12:52:54:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 17
12:52:54:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 16
12:52:54:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 24
12:52:54:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 25
12:52:56:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 23), (1, 22)
ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
ASIC address 0x2: (ASIC uplink, uplink): (0, 21), (1, 20)
ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
ASIC address 0x4: (ASIC uplink, uplink): (0, 19), (1, 18)
ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
ASIC address 0x6: (ASIC uplink, uplink): (0, 17), (1, 16)
ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
Clock Phase Characteristic:
Optimal Phase: 33
Window Length: 70
Eye Windows:
Uplink 16: _______________________________________________________________________XXXXXXX__
Uplink 17: _______________________________________________________________________XXXXXXX__
Uplink 18: _______________________________________________________________________XXXXXXX__
Uplink 19: _______________________________________________________________________XXXXXXX__
Uplink 20: _______________________________________________________________________XXXXXXXX_
Uplink 21: _______________________________________________________________________XXXXXXXX_
Uplink 22: ______________________________________________________________________XXXXXXXX__
Uplink 23: ______________________________________________________________________XXXXXXXX__
Uplink 24: ______________________________________________________________________XXXXXXXXX_
Uplink 25: ______________________________________________________________________XXXXXXXXX_
Uplink 26: _____________________________________________________________________XXXXXXXX___
Uplink 27: _____________________________________________________________________XXXXXXXX___
Uplink 28: _____________________________________________________________________XXXXXXXXX__
Uplink 29: _____________________________________________________________________XXXXXXXXX__
Uplink 30: _______________________________________________________________________XXXXXXX__
Uplink 31: _______________________________________________________________________XXXXXXX__
Data phase characteristics:
Uplink 16:
Optimal Phase: 16
Window Length: 36
Eye Window: ___________________________________XXXX_
Uplink 17:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 18:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXXX
Uplink 19:
Optimal Phase: 14
Window Length: 35
Eye Window: ________________________________XXXXX___
Uplink 20:
Optimal Phase: 18
Window Length: 35
Eye Window: X___________________________________XXXX
Uplink 21:
Optimal Phase: 16
Window Length: 34
Eye Window: __________________________________XXXXXX
Uplink 22:
Optimal Phase: 16
Window Length: 36
Eye Window: ___________________________________XXXX_
Uplink 23:
Optimal Phase: 14
Window Length: 36
Eye Window: _________________________________XXXX___
Uplink 24:
Optimal Phase: 1
Window Length: 4
Eye Window: ____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Uplink 25:
Optimal Phase: 2
Window Length: 6
Eye Window: ______XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Uplink 26:
Optimal Phase: 25
Window Length: 34
Eye Window: ___XXXXXX_______________________________
Uplink 27:
Optimal Phase: 29
Window Length: 34
Eye Window: _______XXXXXX___________________________
Uplink 28:
Optimal Phase: 31
Window Length: 34
Eye Window: _________XXXXXX_________________________
Uplink 29:
Optimal Phase: 33
Window Length: 34
Eye Window: ___________XXXXXX_______________________
Uplink 30:
Optimal Phase: 35
Window Length: 34
Eye Window: _____________XXXXXX_____________________
Uplink 31:
Optimal Phase: 34
Window Length: 35
Eye Window: ____________XXXXX_______________________
12:52:56:setup_element:INFO: Performing Elink synchronization
12:52:56:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
12:52:56:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
12:52:56:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
12:52:56:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
12:52:56:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2
12:52:56:uplink:INFO: Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
12:52:56:ST3_emu:INFO: Number of chips: 8
12:52:56:ST3_emu:INFO: Chip address: 0x0
12:52:56:ST3_emu:INFO: Chip address: 0x1
12:52:56:ST3_emu:INFO: Chip address: 0x2
12:52:56:ST3_emu:INFO: Chip address: 0x3
12:52:56:ST3_emu:INFO: Chip address: 0x4
12:52:56:ST3_emu:INFO: Chip address: 0x5
12:52:56:ST3_emu:INFO: Chip address: 0x6
12:52:56:ST3_emu:INFO: Chip address: 0x7
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_h_0 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_h_0 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_h_0 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_h_0 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_h_0 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_h_0 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_e_0 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_e_0 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_e_0 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_e_0 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_e_0 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_e_0 (Potential memory leak).
TCanvas::Constructor:0: RuntimeWarning: Deleting canvas with same name: cDist_0
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_h_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_h_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_h_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_h_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_h_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_h_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_e_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_e_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_e_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_e_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_e_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_e_1 (Potential memory leak).
TCanvas::Constructor:0: RuntimeWarning: Deleting canvas with same name: cDist_1
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_h_2 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_h_2 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_h_2 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_h_2 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_h_2 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_h_2 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_e_2 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_e_2 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_e_2 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_e_2 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_e_2 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_e_2 (Potential memory leak).
TCanvas::Constructor:0: RuntimeWarning: Deleting canvas with same name: cDist_2
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_h_3 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_h_3 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_h_3 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_h_3 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_h_3 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_h_3 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_e_3 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_e_3 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_e_3 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_e_3 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_e_3 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_e_3 (Potential memory leak).
TCanvas::Constructor:0: RuntimeWarning: Deleting canvas with same name: cDist_3
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_h_4 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_h_4 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_h_4 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_h_4 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_h_4 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_h_4 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_e_4 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_e_4 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_e_4 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_e_4 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_e_4 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_e_4 (Potential memory leak).
TCanvas::Constructor:0: RuntimeWarning: Deleting canvas with same name: cDist_4
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_h_5 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_h_5 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_h_5 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_h_5 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_h_5 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_h_5 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_e_5 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_e_5 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_e_5 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_e_5 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_e_5 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_e_5 (Potential memory leak).
TCanvas::Constructor:0: RuntimeWarning: Deleting canvas with same name: cDist_5
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_h_6 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_h_6 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_h_6 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_h_6 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_h_6 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_h_6 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_e_6 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_e_6 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_e_6 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_e_6 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_e_6 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_e_6 (Potential memory leak).
TCanvas::Constructor:0: RuntimeWarning: Deleting canvas with same name: cDist_6
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_h_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_h_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_h_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_h_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_h_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_h_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_e_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_e_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_e_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_e_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_e_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_e_7 (Potential memory leak).
TCanvas::Constructor:0: RuntimeWarning: Deleting canvas with same name: cDist_7
12:52:57:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
12:52:57:febtest:INFO: 0-0 | XA-000-08-002-000-001-221-11 | 40.9 | 1171.5
12:52:57:febtest:INFO: 0-1 | XA-000-08-001-064-050-160-13 | 37.7 | 1201.0
12:52:57:febtest:INFO: 0-2 | XA-000-08-002-000-001-045-13 | 44.1 | 1171.5
12:52:57:febtest:INFO: 0-3 | XA-000-08-001-064-051-128-14 | 50.4 | 1153.7
12:52:58:febtest:INFO: 0-4 | XA-000-08-001-064-051-080-06 | 37.7 | 1195.1
12:52:58:febtest:INFO: 0-5 | XA-000-08-001-064-051-136-14 | 37.7 | 1183.3
12:52:58:febtest:INFO: 0-6 | XA-000-08-001-064-051-088-06 | 34.6 | 1195.1
12:52:58:febtest:INFO: 0-7 | XA-000-08-001-064-051-184-07 | 44.1 | 1165.6
12:52:58:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
12:53:02:ST3_smx:INFO: chip: 0-0 44.073563 C 1159.654860 mV
12:53:02:ST3_smx:INFO: # loops 0
12:53:04:ST3_smx:INFO: # loops 1
12:53:05:ST3_smx:INFO: # loops 2
12:53:07:ST3_smx:INFO: # loops 3
12:53:09:ST3_smx:INFO: # loops 4
12:53:10:ST3_smx:INFO: Total # of broken channels: 0
12:53:10:ST3_smx:INFO: List of broken channels: []
12:53:10:ST3_smx:INFO: Total # of broken channels: 0
12:53:10:ST3_smx:INFO: List of broken channels: []
12:53:11:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
12:53:15:ST3_smx:INFO: chip: 0-1 40.898880 C 1165.571835 mV
12:53:15:ST3_smx:INFO: # loops 0
12:53:16:ST3_smx:INFO: # loops 1
12:53:18:ST3_smx:INFO: # loops 2
12:53:20:ST3_smx:INFO: # loops 3
12:53:22:ST3_smx:INFO: # loops 4
12:53:23:ST3_smx:INFO: Total # of broken channels: 0
12:53:23:ST3_smx:INFO: List of broken channels: []
12:53:23:ST3_smx:INFO: Total # of broken channels: 0
12:53:23:ST3_smx:INFO: List of broken channels: []
12:53:24:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
12:53:28:ST3_smx:INFO: chip: 0-2 53.612520 C 1124.048640 mV
12:53:28:ST3_smx:INFO: # loops 0
12:53:30:ST3_smx:INFO: # loops 1
12:53:31:ST3_smx:INFO: # loops 2
12:53:33:ST3_smx:INFO: # loops 3
12:53:35:ST3_smx:INFO: # loops 4
12:53:36:ST3_smx:INFO: Total # of broken channels: 0
12:53:36:ST3_smx:INFO: List of broken channels: []
12:53:36:ST3_smx:INFO: Total # of broken channels: 0
12:53:36:ST3_smx:INFO: List of broken channels: []
12:53:37:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
12:53:41:ST3_smx:INFO: chip: 0-3 50.430383 C 1141.874115 mV
12:53:41:ST3_smx:INFO: # loops 0
12:53:42:ST3_smx:INFO: # loops 1
12:53:44:ST3_smx:INFO: # loops 2
12:53:46:ST3_smx:INFO: # loops 3
12:53:47:ST3_smx:INFO: # loops 4
12:53:49:ST3_smx:INFO: Total # of broken channels: 0
12:53:49:ST3_smx:INFO: List of broken channels: []
12:53:49:ST3_smx:INFO: Total # of broken channels: 0
12:53:49:ST3_smx:INFO: List of broken channels: []
12:53:50:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
12:53:53:ST3_smx:INFO: chip: 0-4 47.250730 C 1153.732915 mV
12:53:54:ST3_smx:INFO: # loops 0
12:53:55:ST3_smx:INFO: # loops 1
12:53:57:ST3_smx:INFO: # loops 2
12:53:58:ST3_smx:INFO: # loops 3
12:54:00:ST3_smx:INFO: # loops 4
12:54:02:ST3_smx:INFO: Total # of broken channels: 0
12:54:02:ST3_smx:INFO: List of broken channels: []
12:54:02:ST3_smx:INFO: Total # of broken channels: 0
12:54:02:ST3_smx:INFO: List of broken channels: []
12:54:02:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
12:54:06:ST3_smx:INFO: chip: 0-5 40.898880 C 1159.654860 mV
12:54:06:ST3_smx:INFO: # loops 0
12:54:08:ST3_smx:INFO: # loops 1
12:54:09:ST3_smx:INFO: # loops 2
12:54:11:ST3_smx:INFO: # loops 3
12:54:13:ST3_smx:INFO: # loops 4
12:54:14:ST3_smx:INFO: Total # of broken channels: 0
12:54:14:ST3_smx:INFO: List of broken channels: []
12:54:14:ST3_smx:INFO: Total # of broken channels: 0
12:54:14:ST3_smx:INFO: List of broken channels: []
12:54:15:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
12:54:19:ST3_smx:INFO: chip: 0-6 44.073563 C 1147.806000 mV
12:54:19:ST3_smx:INFO: # loops 0
12:54:21:ST3_smx:INFO: # loops 1
12:54:22:ST3_smx:INFO: # loops 2
12:54:24:ST3_smx:INFO: # loops 3
12:54:26:ST3_smx:INFO: # loops 4
12:54:27:ST3_smx:INFO: Total # of broken channels: 0
12:54:27:ST3_smx:INFO: List of broken channels: []
12:54:27:ST3_smx:INFO: Total # of broken channels: 1
12:54:27:ST3_smx:INFO: List of broken channels: [1]
12:54:28:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
12:54:32:ST3_smx:INFO: chip: 0-7 44.073563 C 1153.732915 mV
12:54:32:ST3_smx:INFO: # loops 0
12:54:33:ST3_smx:INFO: # loops 1
12:54:35:ST3_smx:INFO: # loops 2
12:54:36:ST3_smx:INFO: # loops 3
12:54:38:ST3_smx:INFO: # loops 4
12:54:40:ST3_smx:INFO: Total # of broken channels: 0
12:54:40:ST3_smx:INFO: List of broken channels: []
12:54:40:ST3_smx:INFO: Total # of broken channels: 1
12:54:40:ST3_smx:INFO: List of broken channels: [75]
12:54:41:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
12:54:41:febtest:INFO: 0-0 | XA-000-08-002-000-001-221-11 | 47.3 | 1153.7
12:54:41:febtest:INFO: 0-1 | XA-000-08-001-064-050-160-13 | 47.3 | 1159.7
12:54:41:febtest:INFO: 0-2 | XA-000-08-002-000-001-045-13 | 56.8 | 1118.1
12:54:41:febtest:INFO: 0-3 | XA-000-08-001-064-051-128-14 | 50.4 | 1135.9
12:54:42:febtest:INFO: 0-4 | XA-000-08-001-064-051-080-06 | 50.4 | 1147.8
12:54:42:febtest:INFO: 0-5 | XA-000-08-001-064-051-136-14 | 44.1 | 1153.7
12:54:42:febtest:INFO: 0-6 | XA-000-08-001-064-051-088-06 | 47.3 | 1147.8
12:54:42:febtest:INFO: 0-7 | XA-000-08-001-064-051-184-07 | 44.1 | 1153.7
12:54:54:ST3_Shared:INFO: /home/cbm/public_html/Production_LogDir//FEB/FEB_2027/TestDate_2023_11_01-12_52_45/
12:59:12:ST3_Shared:INFO: Listo of operators:Alois Alzheimer
12:59:12:ST3_Shared:INFO: Listo of operators:Robert V.;
12:59:23:febtest:INFO: FEB 8-2 B @ GSI
12:59:29:smx_tester:INFO: Setting Elink clock mode to 160 MHz
13:00:15:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
13:00:15:ST3_Shared:INFO: --------------------------FEB-ASIC--------------------------
13:00:15:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
13:00:16:febtest:INFO: Tsting FEB with SN 2035
13:00:17:smx_tester:INFO: Scanning setup
13:00:17:elinks:INFO: Disabling clock on downlink 0
13:00:17:elinks:INFO: Disabling clock on downlink 1
13:00:17:elinks:INFO: Disabling clock on downlink 2
13:00:17:elinks:INFO: Disabling clock on downlink 3
13:00:17:elinks:INFO: Disabling clock on downlink 4
13:00:17:setup_element:INFO: Checking SOS, encoding_mode: SOS
13:00:17:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
13:00:17:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
13:00:17:elinks:INFO: Disabling clock on downlink 0
13:00:17:elinks:INFO: Disabling clock on downlink 1
13:00:17:elinks:INFO: Disabling clock on downlink 2
13:00:17:elinks:INFO: Disabling clock on downlink 3
13:00:17:elinks:INFO: Disabling clock on downlink 4
13:00:17:setup_element:INFO: Checking SOS, encoding_mode: SOS
13:00:17:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
13:00:17:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
13:00:17:elinks:INFO: Disabling clock on downlink 0
13:00:17:elinks:INFO: Disabling clock on downlink 1
13:00:17:elinks:INFO: Disabling clock on downlink 2
13:00:17:elinks:INFO: Disabling clock on downlink 3
13:00:17:elinks:INFO: Disabling clock on downlink 4
13:00:17:setup_element:INFO: Checking SOS, encoding_mode: SOS
13:00:17:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
13:00:18:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 16
13:00:18:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 17
13:00:18:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 18
13:00:18:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 19
13:00:18:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 20
13:00:18:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 21
13:00:18:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 22
13:00:18:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 23
13:00:18:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24
13:00:18:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25
13:00:18:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26
13:00:18:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27
13:00:18:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28
13:00:18:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29
13:00:18:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30
13:00:18:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31
13:00:18:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
13:00:18:elinks:INFO: Disabling clock on downlink 0
13:00:18:elinks:INFO: Disabling clock on downlink 1
13:00:18:elinks:INFO: Disabling clock on downlink 2
13:00:18:elinks:INFO: Disabling clock on downlink 3
13:00:18:elinks:INFO: Disabling clock on downlink 4
13:00:18:setup_element:INFO: Checking SOS, encoding_mode: SOS
13:00:18:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
13:00:18:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
13:00:18:elinks:INFO: Disabling clock on downlink 0
13:00:18:elinks:INFO: Disabling clock on downlink 1
13:00:18:elinks:INFO: Disabling clock on downlink 2
13:00:18:elinks:INFO: Disabling clock on downlink 3
13:00:18:elinks:INFO: Disabling clock on downlink 4
13:00:18:setup_element:INFO: Checking SOS, encoding_mode: SOS
13:00:18:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
13:00:18:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
13:00:18:setup_element:INFO: Scanning clock phase
13:00:18:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
13:00:18:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
13:00:18:setup_element:INFO: Clock phase scan results for group 0, downlink 2
13:00:18:setup_element:INFO: Eye window for uplink 16: ________________________________________________________________________XXXXXXXX
Clock Delay: 35
13:00:18:setup_element:INFO: Eye window for uplink 17: ________________________________________________________________________XXXXXXXX
Clock Delay: 35
13:00:19:setup_element:INFO: Eye window for uplink 18: ________________________________________________________________________XXXXXXX_
Clock Delay: 35
13:00:19:setup_element:INFO: Eye window for uplink 19: ________________________________________________________________________XXXXXXX_
Clock Delay: 35
13:00:19:setup_element:INFO: Eye window for uplink 20: ______________________________________________________________________XXXXXXXXX_
Clock Delay: 34
13:00:19:setup_element:INFO: Eye window for uplink 21: ______________________________________________________________________XXXXXXXXX_
Clock Delay: 34
13:00:19:setup_element:INFO: Eye window for uplink 22: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
13:00:19:setup_element:INFO: Eye window for uplink 23: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
13:00:19:setup_element:INFO: Eye window for uplink 24: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
13:00:19:setup_element:INFO: Eye window for uplink 25: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
13:00:19:setup_element:INFO: Eye window for uplink 26: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
13:00:19:setup_element:INFO: Eye window for uplink 27: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
13:00:19:setup_element:INFO: Eye window for uplink 28: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
13:00:19:setup_element:INFO: Eye window for uplink 29: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
13:00:19:setup_element:INFO: Eye window for uplink 30: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
13:00:19:setup_element:INFO: Eye window for uplink 31: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
13:00:19:setup_element:INFO: Setting the clock phase to 34 for group 0, downlink 2
13:00:19:setup_element:INFO: Scanning data phases
13:00:19:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
13:00:19:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
13:00:24:setup_element:INFO: Data phase scan results for group 0, downlink 2
13:00:24:setup_element:INFO: Eye window for uplink 16: XXXX____________________________________
Data delay found: 21
13:00:24:setup_element:INFO: Eye window for uplink 17: ___________________________________XXXXX
Data delay found: 17
13:00:24:setup_element:INFO: Eye window for uplink 18: XXX__________________________________XXX
Data delay found: 19
13:00:24:setup_element:INFO: Eye window for uplink 19: X__________________________________XXXX_
Data delay found: 17
13:00:24:setup_element:INFO: Eye window for uplink 20: __________________________________XXXXX_
Data delay found: 16
13:00:24:setup_element:INFO: Eye window for uplink 21: _________________________________XXXXXX_
Data delay found: 15
13:00:24:setup_element:INFO: Eye window for uplink 22: X____________________________XXXXXXXXXXX
Data delay found: 14
13:00:24:setup_element:INFO: Eye window for uplink 23: _____________________________XXXXXXXXXXX
Data delay found: 14
13:00:24:setup_element:INFO: Eye window for uplink 24: ______XXXXXX____________________________
Data delay found: 28
13:00:24:setup_element:INFO: Eye window for uplink 25: ________XXXXXX__________________________
Data delay found: 30
13:00:24:setup_element:INFO: Eye window for uplink 26: ______XXXX______________________________
Data delay found: 27
13:00:24:setup_element:INFO: Eye window for uplink 27: _________XXXXX__________________________
Data delay found: 31
13:00:24:setup_element:INFO: Eye window for uplink 28: ___________XXXXX________________________
Data delay found: 33
13:00:24:setup_element:INFO: Eye window for uplink 29: _____________XXXX_______________________
Data delay found: 34
13:00:24:setup_element:INFO: Eye window for uplink 30: ______________XXXXXX____________________
Data delay found: 36
13:00:24:setup_element:INFO: Eye window for uplink 31: _____________XXXXX______________________
Data delay found: 35
13:00:24:setup_element:INFO: Setting the data phase to 21 for uplink 16
13:00:24:setup_element:INFO: Setting the data phase to 17 for uplink 17
13:00:24:setup_element:INFO: Setting the data phase to 19 for uplink 18
13:00:24:setup_element:INFO: Setting the data phase to 17 for uplink 19
13:00:24:setup_element:INFO: Setting the data phase to 16 for uplink 20
13:00:24:setup_element:INFO: Setting the data phase to 15 for uplink 21
13:00:24:setup_element:INFO: Setting the data phase to 14 for uplink 22
13:00:24:setup_element:INFO: Setting the data phase to 14 for uplink 23
13:00:24:setup_element:INFO: Setting the data phase to 28 for uplink 24
13:00:24:setup_element:INFO: Setting the data phase to 30 for uplink 25
13:00:24:setup_element:INFO: Setting the data phase to 27 for uplink 26
13:00:24:setup_element:INFO: Setting the data phase to 31 for uplink 27
13:00:24:setup_element:INFO: Setting the data phase to 33 for uplink 28
13:00:24:setup_element:INFO: Setting the data phase to 34 for uplink 29
13:00:24:setup_element:INFO: Setting the data phase to 36 for uplink 30
13:00:24:setup_element:INFO: Setting the data phase to 35 for uplink 31
13:00:24:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 34
Window Length: 70
Eye Windows:
Uplink 16: ________________________________________________________________________XXXXXXXX
Uplink 17: ________________________________________________________________________XXXXXXXX
Uplink 18: ________________________________________________________________________XXXXXXX_
Uplink 19: ________________________________________________________________________XXXXXXX_
Uplink 20: ______________________________________________________________________XXXXXXXXX_
Uplink 21: ______________________________________________________________________XXXXXXXXX_
Uplink 22: _______________________________________________________________________XXXXXXXX_
Uplink 23: _______________________________________________________________________XXXXXXXX_
Uplink 24: _______________________________________________________________________XXXXXXXX_
Uplink 25: _______________________________________________________________________XXXXXXXX_
Uplink 26: ______________________________________________________________________XXXXXXXX__
Uplink 27: ______________________________________________________________________XXXXXXXX__
Uplink 28: _______________________________________________________________________XXXXXXXX_
Uplink 29: _______________________________________________________________________XXXXXXXX_
Uplink 30: _______________________________________________________________________XXXXXXXX_
Uplink 31: _______________________________________________________________________XXXXXXXX_
Data phase characteristics:
Uplink 16:
Optimal Phase: 21
Window Length: 36
Eye Window: XXXX____________________________________
Uplink 17:
Optimal Phase: 17
Window Length: 35
Eye Window: ___________________________________XXXXX
Uplink 18:
Optimal Phase: 19
Window Length: 34
Eye Window: XXX__________________________________XXX
Uplink 19:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXX_
Uplink 20:
Optimal Phase: 16
Window Length: 35
Eye Window: __________________________________XXXXX_
Uplink 21:
Optimal Phase: 15
Window Length: 34
Eye Window: _________________________________XXXXXX_
Uplink 22:
Optimal Phase: 14
Window Length: 28
Eye Window: X____________________________XXXXXXXXXXX
Uplink 23:
Optimal Phase: 14
Window Length: 29
Eye Window: _____________________________XXXXXXXXXXX
Uplink 24:
Optimal Phase: 28
Window Length: 34
Eye Window: ______XXXXXX____________________________
Uplink 25:
Optimal Phase: 30
Window Length: 34
Eye Window: ________XXXXXX__________________________
Uplink 26:
Optimal Phase: 27
Window Length: 36
Eye Window: ______XXXX______________________________
Uplink 27:
Optimal Phase: 31
Window Length: 35
Eye Window: _________XXXXX__________________________
Uplink 28:
Optimal Phase: 33
Window Length: 35
Eye Window: ___________XXXXX________________________
Uplink 29:
Optimal Phase: 34
Window Length: 36
Eye Window: _____________XXXX_______________________
Uplink 30:
Optimal Phase: 36
Window Length: 34
Eye Window: ______________XXXXXX____________________
Uplink 31:
Optimal Phase: 35
Window Length: 35
Eye Window: _____________XXXXX______________________
]
13:00:24:setup_element:INFO: Beginning SMX ASICs map scan
13:00:24:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
13:00:24:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
13:00:24:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
13:00:24:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
13:00:24:uplink:INFO: Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
13:00:24:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 23
13:00:24:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 22
13:00:25:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 30
13:00:25:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 31
13:00:25:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 21
13:00:25:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 20
13:00:25:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28
13:00:25:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 29
13:00:25:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 19
13:00:25:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 18
13:00:25:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26
13:00:25:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 27
13:00:26:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 17
13:00:26:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 16
13:00:26:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 24
13:00:26:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 25
13:00:27:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 23), (1, 22)
ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
ASIC address 0x2: (ASIC uplink, uplink): (0, 21), (1, 20)
ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
ASIC address 0x4: (ASIC uplink, uplink): (0, 19), (1, 18)
ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
ASIC address 0x6: (ASIC uplink, uplink): (0, 17), (1, 16)
ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
Clock Phase Characteristic:
Optimal Phase: 34
Window Length: 70
Eye Windows:
Uplink 16: ________________________________________________________________________XXXXXXXX
Uplink 17: ________________________________________________________________________XXXXXXXX
Uplink 18: ________________________________________________________________________XXXXXXX_
Uplink 19: ________________________________________________________________________XXXXXXX_
Uplink 20: ______________________________________________________________________XXXXXXXXX_
Uplink 21: ______________________________________________________________________XXXXXXXXX_
Uplink 22: _______________________________________________________________________XXXXXXXX_
Uplink 23: _______________________________________________________________________XXXXXXXX_
Uplink 24: _______________________________________________________________________XXXXXXXX_
Uplink 25: _______________________________________________________________________XXXXXXXX_
Uplink 26: ______________________________________________________________________XXXXXXXX__
Uplink 27: ______________________________________________________________________XXXXXXXX__
Uplink 28: _______________________________________________________________________XXXXXXXX_
Uplink 29: _______________________________________________________________________XXXXXXXX_
Uplink 30: _______________________________________________________________________XXXXXXXX_
Uplink 31: _______________________________________________________________________XXXXXXXX_
Data phase characteristics:
Uplink 16:
Optimal Phase: 21
Window Length: 36
Eye Window: XXXX____________________________________
Uplink 17:
Optimal Phase: 17
Window Length: 35
Eye Window: ___________________________________XXXXX
Uplink 18:
Optimal Phase: 19
Window Length: 34
Eye Window: XXX__________________________________XXX
Uplink 19:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXX_
Uplink 20:
Optimal Phase: 16
Window Length: 35
Eye Window: __________________________________XXXXX_
Uplink 21:
Optimal Phase: 15
Window Length: 34
Eye Window: _________________________________XXXXXX_
Uplink 22:
Optimal Phase: 14
Window Length: 28
Eye Window: X____________________________XXXXXXXXXXX
Uplink 23:
Optimal Phase: 14
Window Length: 29
Eye Window: _____________________________XXXXXXXXXXX
Uplink 24:
Optimal Phase: 28
Window Length: 34
Eye Window: ______XXXXXX____________________________
Uplink 25:
Optimal Phase: 30
Window Length: 34
Eye Window: ________XXXXXX__________________________
Uplink 26:
Optimal Phase: 27
Window Length: 36
Eye Window: ______XXXX______________________________
Uplink 27:
Optimal Phase: 31
Window Length: 35
Eye Window: _________XXXXX__________________________
Uplink 28:
Optimal Phase: 33
Window Length: 35
Eye Window: ___________XXXXX________________________
Uplink 29:
Optimal Phase: 34
Window Length: 36
Eye Window: _____________XXXX_______________________
Uplink 30:
Optimal Phase: 36
Window Length: 34
Eye Window: ______________XXXXXX____________________
Uplink 31:
Optimal Phase: 35
Window Length: 35
Eye Window: _____________XXXXX______________________
13:00:27:setup_element:INFO: Performing Elink synchronization
13:00:27:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
13:00:27:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
13:00:27:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
13:00:27:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
13:00:27:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2
13:00:27:uplink:INFO: Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
13:00:27:ST3_emu:INFO: Number of chips: 8
13:00:27:ST3_emu:INFO: Chip address: 0x0
13:00:27:ST3_emu:INFO: Chip address: 0x1
13:00:27:ST3_emu:INFO: Chip address: 0x2
13:00:27:ST3_emu:INFO: Chip address: 0x3
13:00:27:ST3_emu:INFO: Chip address: 0x4
13:00:27:ST3_emu:INFO: Chip address: 0x5
13:00:27:ST3_emu:INFO: Chip address: 0x6
13:00:27:ST3_emu:INFO: Chip address: 0x7
13:00:28:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
13:00:28:febtest:INFO: 0-0 | XA-000-08-002-000-007-008-06 | 47.3 | 1153.7
13:00:28:febtest:INFO: 0-1 | XA-000-08-002-000-007-199-09 | 50.4 | 1153.7
13:00:29:febtest:INFO: 0-2 | XA-000-08-002-000-007-031-01 | 31.4 | 1218.6
13:00:29:febtest:INFO: 0-3 | XA-000-08-002-000-007-198-09 | 34.6 | 1206.9
13:00:29:febtest:INFO: 0-4 | XA-000-08-002-000-007-041-08 | 18.7 | 1259.6
13:00:29:febtest:INFO: 0-5 | XA-000-08-002-000-007-127-10 | 44.1 | 1177.4
13:00:30:febtest:INFO: 0-6 | XA-000-08-002-000-007-047-08 | 15.6 | 1277.1
13:00:30:febtest:INFO: 0-7 | XA-000-08-002-000-007-083-04 | 34.6 | 1201.0
13:00:30:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
13:00:34:ST3_smx:INFO: chip: 0-0 44.073563 C 1159.654860 mV
13:00:34:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
13:00:34:ST3_smx:INFO: Electrons
13:00:34:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
13:00:36:ST3_smx:INFO: ----> Checking Analog response
13:00:36:ST3_smx:INFO: ----> Checking broken channels
13:00:36:ST3_smx:INFO: Total # broken ch: 0
13:00:36:ST3_smx:INFO: List FAST: []
13:00:36:ST3_smx:INFO: List SLOW: []
13:00:36:ST3_smx:INFO: Holes
13:00:36:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
13:00:38:ST3_smx:INFO: ----> Checking Analog response
13:00:38:ST3_smx:INFO: ----> Checking broken channels
13:00:38:ST3_smx:INFO: Total # broken ch: 0
13:00:38:ST3_smx:INFO: List FAST: []
13:00:38:ST3_smx:INFO: List SLOW: []
13:00:38:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
13:00:38:febtest:INFO: 0-0 | XA-000-08-002-000-007-008-06 | 47.3 | 1153.7
13:00:38:febtest:INFO: 0-1 | XA-000-08-002-000-007-199-09 | 50.4 | 1153.7
13:00:39:febtest:INFO: 0-2 | XA-000-08-002-000-007-031-01 | 31.4 | 1218.6
13:00:39:febtest:INFO: 0-3 | XA-000-08-002-000-007-198-09 | 34.6 | 1206.9
13:00:39:febtest:INFO: 0-4 | XA-000-08-002-000-007-041-08 | 18.7 | 1253.7
13:00:39:febtest:INFO: 0-5 | XA-000-08-002-000-007-127-10 | 40.9 | 1177.4
13:00:40:febtest:INFO: 0-6 | XA-000-08-002-000-007-047-08 | 15.6 | 1277.1
13:00:40:febtest:INFO: 0-7 | XA-000-08-002-000-007-083-04 | 31.4 | 1201.0
13:00:40:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
13:00:44:ST3_smx:INFO: chip: 0-1 44.073563 C 1153.732915 mV
13:00:44:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
13:00:44:ST3_smx:INFO: Electrons
13:00:44:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
13:00:46:ST3_smx:INFO: ----> Checking Analog response
13:00:46:ST3_smx:INFO: ----> Checking broken channels
13:00:46:ST3_smx:INFO: Total # broken ch: 0
13:00:46:ST3_smx:INFO: List FAST: []
13:00:46:ST3_smx:INFO: List SLOW: []
13:00:46:ST3_smx:INFO: Holes
13:00:46:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
13:00:48:ST3_smx:INFO: ----> Checking Analog response
13:00:48:ST3_smx:INFO: ----> Checking broken channels
13:00:48:ST3_smx:INFO: Total # broken ch: 0
13:00:48:ST3_smx:INFO: List FAST: []
13:00:48:ST3_smx:INFO: List SLOW: []
13:00:48:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
13:00:48:febtest:INFO: 0-0 | XA-000-08-002-000-007-008-06 | 47.3 | 1153.7
13:00:49:febtest:INFO: 0-1 | XA-000-08-002-000-007-199-09 | 47.3 | 1153.7
13:00:49:febtest:INFO: 0-2 | XA-000-08-002-000-007-031-01 | 34.6 | 1218.6
13:00:49:febtest:INFO: 0-3 | XA-000-08-002-000-007-198-09 | 34.6 | 1201.0
13:00:49:febtest:INFO: 0-4 | XA-000-08-002-000-007-041-08 | 18.7 | 1253.7
13:00:50:febtest:INFO: 0-5 | XA-000-08-002-000-007-127-10 | 40.9 | 1177.4
13:00:50:febtest:INFO: 0-6 | XA-000-08-002-000-007-047-08 | 15.6 | 1277.1
13:00:50:febtest:INFO: 0-7 | XA-000-08-002-000-007-083-04 | 31.4 | 1195.1
13:00:50:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
13:00:54:ST3_smx:INFO: chip: 0-2 40.898880 C 1171.483840 mV
13:00:54:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
13:00:54:ST3_smx:INFO: Electrons
13:00:54:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
13:00:56:ST3_smx:INFO: ----> Checking Analog response
13:00:56:ST3_smx:INFO: ----> Checking broken channels
13:00:56:ST3_smx:INFO: Total # broken ch: 0
13:00:56:ST3_smx:INFO: List FAST: []
13:00:56:ST3_smx:INFO: List SLOW: []
13:00:56:ST3_smx:INFO: Holes
13:00:56:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
13:00:58:ST3_smx:INFO: ----> Checking Analog response
13:00:58:ST3_smx:INFO: ----> Checking broken channels
13:00:58:ST3_smx:INFO: Total # broken ch: 0
13:00:58:ST3_smx:INFO: List FAST: []
13:00:58:ST3_smx:INFO: List SLOW: []
13:00:58:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
13:00:58:febtest:INFO: 0-0 | XA-000-08-002-000-007-008-06 | 47.3 | 1153.7
13:00:59:febtest:INFO: 0-1 | XA-000-08-002-000-007-199-09 | 47.3 | 1153.7
13:00:59:febtest:INFO: 0-2 | XA-000-08-002-000-007-031-01 | 44.1 | 1165.6
13:00:59:febtest:INFO: 0-3 | XA-000-08-002-000-007-198-09 | 34.6 | 1201.0
13:00:59:febtest:INFO: 0-4 | XA-000-08-002-000-007-041-08 | 18.7 | 1253.7
13:01:00:febtest:INFO: 0-5 | XA-000-08-002-000-007-127-10 | 40.9 | 1177.4
13:01:00:febtest:INFO: 0-6 | XA-000-08-002-000-007-047-08 | 15.6 | 1277.1
13:01:00:febtest:INFO: 0-7 | XA-000-08-002-000-007-083-04 | 31.4 | 1201.0
13:01:00:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
13:01:04:ST3_smx:INFO: chip: 0-3 44.073563 C 1153.732915 mV
13:01:04:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
13:01:04:ST3_smx:INFO: Electrons
13:01:04:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
13:01:06:ST3_smx:INFO: ----> Checking Analog response
13:01:06:ST3_smx:INFO: ----> Checking broken channels
13:01:06:ST3_smx:INFO: Total # broken ch: 0
13:01:06:ST3_smx:INFO: List FAST: []
13:01:06:ST3_smx:INFO: List SLOW: []
13:01:06:ST3_smx:INFO: Holes
13:01:06:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
13:01:08:ST3_smx:INFO: ----> Checking Analog response
13:01:08:ST3_smx:INFO: ----> Checking broken channels
13:01:08:ST3_smx:INFO: Total # broken ch: 0
13:01:08:ST3_smx:INFO: List FAST: []
13:01:08:ST3_smx:INFO: List SLOW: []
13:01:08:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
13:01:08:febtest:INFO: 0-0 | XA-000-08-002-000-007-008-06 | 47.3 | 1153.7
13:01:09:febtest:INFO: 0-1 | XA-000-08-002-000-007-199-09 | 47.3 | 1153.7
13:01:09:febtest:INFO: 0-2 | XA-000-08-002-000-007-031-01 | 44.1 | 1171.5
13:01:09:febtest:INFO: 0-3 | XA-000-08-002-000-007-198-09 | 47.3 | 1153.7
13:01:09:febtest:INFO: 0-4 | XA-000-08-002-000-007-041-08 | 21.9 | 1253.7
13:01:10:febtest:INFO: 0-5 | XA-000-08-002-000-007-127-10 | 40.9 | 1171.5
13:01:10:febtest:INFO: 0-6 | XA-000-08-002-000-007-047-08 | 15.6 | 1277.1
13:01:10:febtest:INFO: 0-7 | XA-000-08-002-000-007-083-04 | 34.6 | 1195.1
13:01:10:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
13:01:14:ST3_smx:INFO: chip: 0-4 18.745682 C 1242.040240 mV
13:01:14:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
13:01:14:ST3_smx:INFO: Electrons
13:01:14:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
13:01:16:ST3_smx:INFO: ----> Checking Analog response
13:01:16:ST3_smx:INFO: ----> Checking broken channels
13:01:16:ST3_smx:INFO: Total # broken ch: 0
13:01:16:ST3_smx:INFO: List FAST: []
13:01:16:ST3_smx:INFO: List SLOW: []
13:01:16:ST3_smx:INFO: Holes
13:01:16:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
13:01:18:ST3_smx:INFO: ----> Checking Analog response
13:01:18:ST3_smx:INFO: ----> Checking broken channels
13:01:18:ST3_smx:INFO: Total # broken ch: 0
13:01:18:ST3_smx:INFO: List FAST: []
13:01:18:ST3_smx:INFO: List SLOW: []
13:01:18:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
13:01:19:febtest:INFO: 0-0 | XA-000-08-002-000-007-008-06 | 47.3 | 1153.7
13:01:19:febtest:INFO: 0-1 | XA-000-08-002-000-007-199-09 | 50.4 | 1153.7
13:01:19:febtest:INFO: 0-2 | XA-000-08-002-000-007-031-01 | 44.1 | 1165.6
13:01:19:febtest:INFO: 0-3 | XA-000-08-002-000-007-198-09 | 47.3 | 1153.7
13:01:20:febtest:INFO: 0-4 | XA-000-08-002-000-007-041-08 | 21.9 | 1242.0
13:01:20:febtest:INFO: 0-5 | XA-000-08-002-000-007-127-10 | 40.9 | 1171.5
13:01:20:febtest:INFO: 0-6 | XA-000-08-002-000-007-047-08 | 15.6 | 1271.2
13:01:20:febtest:INFO: 0-7 | XA-000-08-002-000-007-083-04 | 34.6 | 1195.1
13:01:21:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
13:01:24:ST3_smx:INFO: chip: 0-5 40.898880 C 1165.571835 mV
13:01:24:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
13:01:24:ST3_smx:INFO: Electrons
13:01:24:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
13:01:26:ST3_smx:INFO: ----> Checking Analog response
13:01:26:ST3_smx:INFO: ----> Checking broken channels
13:01:26:ST3_smx:INFO: Total # broken ch: 0
13:01:26:ST3_smx:INFO: List FAST: []
13:01:26:ST3_smx:INFO: List SLOW: []
13:01:26:ST3_smx:INFO: Holes
13:01:26:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
13:01:28:ST3_smx:INFO: ----> Checking Analog response
13:01:28:ST3_smx:INFO: ----> Checking broken channels
13:01:29:ST3_smx:INFO: Total # broken ch: 0
13:01:29:ST3_smx:INFO: List FAST: []
13:01:29:ST3_smx:INFO: List SLOW: []
13:01:29:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
13:01:29:febtest:INFO: 0-0 | XA-000-08-002-000-007-008-06 | 47.3 | 1153.7
13:01:29:febtest:INFO: 0-1 | XA-000-08-002-000-007-199-09 | 50.4 | 1147.8
13:01:29:febtest:INFO: 0-2 | XA-000-08-002-000-007-031-01 | 47.3 | 1165.6
13:01:29:febtest:INFO: 0-3 | XA-000-08-002-000-007-198-09 | 47.3 | 1153.7
13:01:30:febtest:INFO: 0-4 | XA-000-08-002-000-007-041-08 | 21.9 | 1236.2
13:01:30:febtest:INFO: 0-5 | XA-000-08-002-000-007-127-10 | 44.1 | 1165.6
13:01:30:febtest:INFO: 0-6 | XA-000-08-002-000-007-047-08 | 15.6 | 1277.1
13:01:30:febtest:INFO: 0-7 | XA-000-08-002-000-007-083-04 | 34.6 | 1195.1
13:01:31:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
13:01:34:ST3_smx:INFO: chip: 0-6 25.062742 C 1224.468235 mV
13:01:34:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
13:01:34:ST3_smx:INFO: Electrons
13:01:34:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
13:01:36:ST3_smx:INFO: ----> Checking Analog response
13:01:36:ST3_smx:INFO: ----> Checking broken channels
13:01:37:ST3_smx:INFO: Total # broken ch: 0
13:01:37:ST3_smx:INFO: List FAST: []
13:01:37:ST3_smx:INFO: List SLOW: []
13:01:37:ST3_smx:INFO: Holes
13:01:37:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
13:01:39:ST3_smx:INFO: ----> Checking Analog response
13:01:39:ST3_smx:INFO: ----> Checking broken channels
13:01:39:ST3_smx:INFO: Total # broken ch: 0
13:01:39:ST3_smx:INFO: List FAST: []
13:01:39:ST3_smx:INFO: List SLOW: []
13:01:39:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
13:01:39:febtest:INFO: 0-0 | XA-000-08-002-000-007-008-06 | 50.4 | 1147.8
13:01:39:febtest:INFO: 0-1 | XA-000-08-002-000-007-199-09 | 50.4 | 1147.8
13:01:40:febtest:INFO: 0-2 | XA-000-08-002-000-007-031-01 | 44.1 | 1165.6
13:01:40:febtest:INFO: 0-3 | XA-000-08-002-000-007-198-09 | 47.3 | 1153.7
13:01:40:febtest:INFO: 0-4 | XA-000-08-002-000-007-041-08 | 25.1 | 1236.2
13:01:40:febtest:INFO: 0-5 | XA-000-08-002-000-007-127-10 | 44.1 | 1165.6
13:01:41:febtest:INFO: 0-6 | XA-000-08-002-000-007-047-08 | 28.2 | 1224.5
13:01:41:febtest:INFO: 0-7 | XA-000-08-002-000-007-083-04 | 34.6 | 1195.1
13:01:41:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
13:01:45:ST3_smx:INFO: chip: 0-7 40.898880 C 1159.654860 mV
13:01:45:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
13:01:45:ST3_smx:INFO: Electrons
13:01:45:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
13:01:46:ST3_smx:INFO: ----> Checking Analog response
13:01:46:ST3_smx:INFO: ----> Checking broken channels
13:01:47:ST3_smx:INFO: Total # broken ch: 0
13:01:47:ST3_smx:INFO: List FAST: []
13:01:47:ST3_smx:INFO: List SLOW: []
13:01:47:ST3_smx:INFO: Holes
13:01:47:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
13:01:49:ST3_smx:INFO: ----> Checking Analog response
13:01:49:ST3_smx:INFO: ----> Checking broken channels
13:01:49:ST3_smx:INFO: Total # broken ch: 0
13:01:49:ST3_smx:INFO: List FAST: []
13:01:49:ST3_smx:INFO: List SLOW: []
13:01:49:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
13:01:49:febtest:INFO: 0-0 | XA-000-08-002-000-007-008-06 | 47.3 | 1147.8
13:01:49:febtest:INFO: 0-1 | XA-000-08-002-000-007-199-09 | 50.4 | 1147.8
13:01:50:febtest:INFO: 0-2 | XA-000-08-002-000-007-031-01 | 47.3 | 1165.6
13:01:50:febtest:INFO: 0-3 | XA-000-08-002-000-007-198-09 | 47.3 | 1147.8
13:01:50:febtest:INFO: 0-4 | XA-000-08-002-000-007-041-08 | 25.1 | 1236.2
13:01:50:febtest:INFO: 0-5 | XA-000-08-002-000-007-127-10 | 44.1 | 1165.6
13:01:51:febtest:INFO: 0-6 | XA-000-08-002-000-007-047-08 | 28.2 | 1224.5
13:01:51:febtest:INFO: 0-7 | XA-000-08-002-000-007-083-04 | 44.1 | 1159.7
############################################################
# S U M M A R Y #
############################################################
{'TEST_NAME': 'FEB-ASIC', 'TEST_DATE': '2023_11_01-13_00_15', 'OPERATOR': 'Robert V.; ', 'PROJECT': 'Production', 'SITE': 'GSI', 'SETUP': 'GSI_TEST_SETUP_1', 'ASIC_ID': 'XA-000-08-002-000-007-083-04', 'FUSED_ID': 6359364699116565812, 'HW_ADDR': 7, 'VERS_NO': '2.2', 'CABLE_SET_ID': '', 'IC_TEMP': '0', 'VDDM': '0', 'AUX': '0', 'CSABIAS': '0', 'VDDM_INT': '0', 'ADC_Chi2': 0.0, 'ADC_NDF': 0, 'ADC_P0': 0.0, 'ADC_P1': 0.006824, 'ADC_P2': -2.485e-06, 'ADC_P0err': 0.001, 'ADC_P1err': 0.001, 'ADC_P2err': 1e-05, 'ADC_VREF_P': 58, 'ADC_VREF_N': 30, 'ADC_VREF_T': 128, 'ADC_VREF_TR': 122, 'THR2_GLB': 30, 'LOOP__PLS': 100, 'CALIB_PLS': 250, 'SnsLoop': 5, 'IFED': 31, 'CSA_BIAS': 15, 'CSA_Chi2': 0.0, 'CSA_NDF': 0, 'CSA_P0': 0.0, 'CSA_P1': 0.0, 'CSA_P2': 0.0, 'CSA_P0err': 0.0, 'CSA_P1err': 0.0, 'CSA_P2err': 0.0, 'CONF_FAIL_REG': 0, 'N_BROKEN_DISC': 0, 'N_BROKEN_FAST': '[]', 'N_BROKEN_SLOW': '[]', 'P_BROKEN_DISC': 0, 'P_BROKEN_FAST': '[]', 'P_BROKEN_SLOW': '[]', 'ASIC_QA_category': '', 'N_BROKEN_CABLE': 0, 'LIST_OF_BROKEN_CABLES': 0, 'VI_bInit': ['2.447', '1.8930', '1.845', '2.5720', '7.001', '1.5540', '7.001', '1.5540'], 'VI_aInit': ['0', '0', '0', '0', '0', '0'], 'VI_atEnd': ['0', '0', '0', '0', '0', '0'], 'AMP_CAL': 125, 'PlsLoop': 3, 'N_ANA_PRESENT': 'Analog response OK', 'N_DISC_FAIL_CH': 0, 'N_ANA_FAIL_CH': '0', 'P_ANA_PRESENT': 'Analog response OK', 'P_DISC_FAIL_CH': 0, 'P_ANA_FAIL_CH': '0'}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
13:02:28:ST3_Shared:INFO: /home/cbm/public_html/Production_LogDir//FEB/FEB_2035/TestDate_2023_11_01-13_00_15/
Comment.txt
Test FEB B 2035 fuer KIT Referenzmessung