08:32:22:febtest:INFO:	FEB 8-2 selected
08:32:22:smx_tester:INFO:	Setting Elink clock mode to 160 MHz
08:32:26:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
08:32:26:ST3_Shared:INFO:	-------------------------FEB-Sensor-------------------------
08:32:26:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
08:33:03:ST3_ModuleSelector:INFO:	L4UL201031 M4UL2T2010312B2 42 A

08:33:03:ST3_ModuleSelector:INFO:	07402

08:33:03:febtest:INFO:	Testing FEB with SN 1064
08:33:04:smx_tester:INFO:	Scanning setup
08:33:04:elinks:INFO:	Disabling clock on downlink 0
08:33:04:elinks:INFO:	Disabling clock on downlink 1
08:33:04:elinks:INFO:	Disabling clock on downlink 2
08:33:04:elinks:INFO:	Disabling clock on downlink 3
08:33:04:elinks:INFO:	Disabling clock on downlink 4
08:33:04:setup_element:INFO:	Checking SOS, encoding_mode: SOS
08:33:04:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
08:33:05:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
08:33:05:elinks:INFO:	Disabling clock on downlink 0
08:33:05:elinks:INFO:	Disabling clock on downlink 1
08:33:05:elinks:INFO:	Disabling clock on downlink 2
08:33:05:elinks:INFO:	Disabling clock on downlink 3
08:33:05:elinks:INFO:	Disabling clock on downlink 4
08:33:05:setup_element:INFO:	Checking SOS, encoding_mode: SOS
08:33:05:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
08:33:05:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 0
08:33:05:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 1
08:33:05:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 2
08:33:05:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 3
08:33:05:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 4
08:33:05:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 5
08:33:05:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 6
08:33:05:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 7
08:33:05:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 8
08:33:05:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 9
08:33:05:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 10
08:33:05:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 11
08:33:05:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 12
08:33:05:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 13
08:33:05:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 14
08:33:05:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 15
08:33:05:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
08:33:05:elinks:INFO:	Disabling clock on downlink 0
08:33:05:elinks:INFO:	Disabling clock on downlink 1
08:33:05:elinks:INFO:	Disabling clock on downlink 2
08:33:05:elinks:INFO:	Disabling clock on downlink 3
08:33:05:elinks:INFO:	Disabling clock on downlink 4
08:33:05:setup_element:INFO:	Checking SOS, encoding_mode: SOS
08:33:05:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
08:33:05:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
08:33:05:elinks:INFO:	Disabling clock on downlink 0
08:33:05:elinks:INFO:	Disabling clock on downlink 1
08:33:05:elinks:INFO:	Disabling clock on downlink 2
08:33:05:elinks:INFO:	Disabling clock on downlink 3
08:33:05:elinks:INFO:	Disabling clock on downlink 4
08:33:05:setup_element:INFO:	Checking SOS, encoding_mode: SOS
08:33:05:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
08:33:05:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
08:33:05:elinks:INFO:	Disabling clock on downlink 0
08:33:05:elinks:INFO:	Disabling clock on downlink 1
08:33:05:elinks:INFO:	Disabling clock on downlink 2
08:33:05:elinks:INFO:	Disabling clock on downlink 3
08:33:05:elinks:INFO:	Disabling clock on downlink 4
08:33:05:setup_element:INFO:	Checking SOS, encoding_mode: SOS
08:33:05:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [4]
08:33:05:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
08:33:05:setup_element:INFO:	Scanning clock phase
08:33:05:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
08:33:05:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [1]
08:33:06:setup_element:INFO:	Clock phase scan results for group 0, downlink 1
08:33:06:setup_element:INFO:	Eye window for uplink 0 : _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
08:33:06:setup_element:INFO:	Eye window for uplink 1 : _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
08:33:06:setup_element:INFO:	Eye window for uplink 2 : ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
08:33:06:setup_element:INFO:	Eye window for uplink 3 : ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
08:33:06:setup_element:INFO:	Eye window for uplink 4 : _____________________________________________________________________XXXXXXX____
Clock Delay: 32
08:33:06:setup_element:INFO:	Eye window for uplink 5 : _____________________________________________________________________XXXXXXX____
Clock Delay: 32
08:33:06:setup_element:INFO:	Eye window for uplink 6 : ________________________________________________________________________XXXXXX__
Clock Delay: 34
08:33:06:setup_element:INFO:	Eye window for uplink 7 : ________________________________________________________________________XXXXXX__
Clock Delay: 34
08:33:06:setup_element:INFO:	Eye window for uplink 8 : ____________________________________________________________________XXXXXXXXX___
Clock Delay: 32
08:33:06:setup_element:INFO:	Eye window for uplink 9 : ____________________________________________________________________XXXXXXXXX___
Clock Delay: 32
08:33:06:setup_element:INFO:	Eye window for uplink 10: ________________________________________________________________________________
Clock Delay: 40
08:33:06:setup_element:INFO:	Eye window for uplink 11: ________________________________________________________________________________
Clock Delay: 40
08:33:06:setup_element:INFO:	Eye window for uplink 12: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
08:33:06:setup_element:INFO:	Eye window for uplink 13: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
08:33:06:setup_element:INFO:	Eye window for uplink 14: ________________________________________________________________________XXXXX___
Clock Delay: 34
08:33:06:setup_element:INFO:	Eye window for uplink 15: ________________________________________________________________________XXXXX___
Clock Delay: 34
08:33:06:setup_element:INFO:	Setting the clock phase to 33 for group 0, downlink 1
08:33:06:setup_element:INFO:	Scanning data phases
08:33:06:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
08:33:06:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [1]
08:33:11:setup_element:INFO:	Data phase scan results for group 0, downlink 1
08:33:11:setup_element:INFO:	Eye window for uplink 0 : __________XXXXXX________________________
Data delay found: 32
08:33:11:setup_element:INFO:	Eye window for uplink 1 : ______XXXXX_____________________________
Data delay found: 28
08:33:11:setup_element:INFO:	Eye window for uplink 2 : _____XXXXX______________________________
Data delay found: 27
08:33:11:setup_element:INFO:	Eye window for uplink 3 : __XXXXXX________________________________
Data delay found: 24
08:33:11:setup_element:INFO:	Eye window for uplink 4 : __XXXXX_________________________________
Data delay found: 24
08:33:11:setup_element:INFO:	Eye window for uplink 5 : XXX__________________________________XXX
Data delay found: 19
08:33:11:setup_element:INFO:	Eye window for uplink 6 : XXXX__________________________________XX
Data delay found: 20
08:33:11:setup_element:INFO:	Eye window for uplink 7 : X__________________________________XXXXX
Data delay found: 17
08:33:11:setup_element:INFO:	Eye window for uplink 8 : _________________________XXXXX__________
Data delay found: 7
08:33:11:setup_element:INFO:	Eye window for uplink 9 : ______________________________XXXXX_____
Data delay found: 12
08:33:11:setup_element:INFO:	Eye window for uplink 10: _________________________XXXXX__________
Data delay found: 7
08:33:11:setup_element:INFO:	Eye window for uplink 11: ____________________________XXXXX_______
Data delay found: 10
08:33:11:setup_element:INFO:	Eye window for uplink 12: __________________________XXXXX_________
Data delay found: 8
08:33:11:setup_element:INFO:	Eye window for uplink 13: _____________________________XXXXX______
Data delay found: 11
08:33:11:setup_element:INFO:	Eye window for uplink 14: _____________________________XXXX_______
Data delay found: 10
08:33:11:setup_element:INFO:	Eye window for uplink 15: ______________________________XXXXX_____
Data delay found: 12
08:33:11:setup_element:INFO:	Setting the data phase to 32 for uplink 0
08:33:11:setup_element:INFO:	Setting the data phase to 28 for uplink 1
08:33:11:setup_element:INFO:	Setting the data phase to 27 for uplink 2
08:33:11:setup_element:INFO:	Setting the data phase to 24 for uplink 3
08:33:11:setup_element:INFO:	Setting the data phase to 24 for uplink 4
08:33:11:setup_element:INFO:	Setting the data phase to 19 for uplink 5
08:33:11:setup_element:INFO:	Setting the data phase to 20 for uplink 6
08:33:11:setup_element:INFO:	Setting the data phase to 17 for uplink 7
08:33:11:setup_element:INFO:	Setting the data phase to 7 for uplink 8
08:33:11:setup_element:INFO:	Setting the data phase to 12 for uplink 9
08:33:11:setup_element:INFO:	Setting the data phase to 7 for uplink 10
08:33:11:setup_element:INFO:	Setting the data phase to 10 for uplink 11
08:33:11:setup_element:INFO:	Setting the data phase to 8 for uplink 12
08:33:11:setup_element:INFO:	Setting the data phase to 11 for uplink 13
08:33:11:setup_element:INFO:	Setting the data phase to 10 for uplink 14
08:33:11:setup_element:INFO:	Setting the data phase to 12 for uplink 15
08:33:11:ST3_emu:ERROR:	[
Setup Element:
  Group: 0
  Downlink: 1
  Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
  ASICs Map: None
  Clock Phase Characteristic:
    Optimal Phase: 33
    Window Length: 69
    Eye Windows:
      Uplink  0: _______________________________________________________________________XXXXXXXX_
      Uplink  1: _______________________________________________________________________XXXXXXXX_
      Uplink  2: ______________________________________________________________________XXXXXXXX__
      Uplink  3: ______________________________________________________________________XXXXXXXX__
      Uplink  4: _____________________________________________________________________XXXXXXX____
      Uplink  5: _____________________________________________________________________XXXXXXX____
      Uplink  6: ________________________________________________________________________XXXXXX__
      Uplink  7: ________________________________________________________________________XXXXXX__
      Uplink  8: ____________________________________________________________________XXXXXXXXX___
      Uplink  9: ____________________________________________________________________XXXXXXXXX___
      Uplink 10: ________________________________________________________________________________
      Uplink 11: ________________________________________________________________________________
      Uplink 12: _____________________________________________________________________XXXXXXXX___
      Uplink 13: _____________________________________________________________________XXXXXXXX___
      Uplink 14: ________________________________________________________________________XXXXX___
      Uplink 15: ________________________________________________________________________XXXXX___
  Data phase characteristics:
    Uplink 0:
      Optimal Phase: 32
      Window Length: 34
      Eye Window: __________XXXXXX________________________
    Uplink 1:
      Optimal Phase: 28
      Window Length: 35
      Eye Window: ______XXXXX_____________________________
    Uplink 2:
      Optimal Phase: 27
      Window Length: 35
      Eye Window: _____XXXXX______________________________
    Uplink 3:
      Optimal Phase: 24
      Window Length: 34
      Eye Window: __XXXXXX________________________________
    Uplink 4:
      Optimal Phase: 24
      Window Length: 35
      Eye Window: __XXXXX_________________________________
    Uplink 5:
      Optimal Phase: 19
      Window Length: 34
      Eye Window: XXX__________________________________XXX
    Uplink 6:
      Optimal Phase: 20
      Window Length: 34
      Eye Window: XXXX__________________________________XX
    Uplink 7:
      Optimal Phase: 17
      Window Length: 34
      Eye Window: X__________________________________XXXXX
    Uplink 8:
      Optimal Phase: 7
      Window Length: 35
      Eye Window: _________________________XXXXX__________
    Uplink 9:
      Optimal Phase: 12
      Window Length: 35
      Eye Window: ______________________________XXXXX_____
    Uplink 10:
      Optimal Phase: 7
      Window Length: 35
      Eye Window: _________________________XXXXX__________
    Uplink 11:
      Optimal Phase: 10
      Window Length: 35
      Eye Window: ____________________________XXXXX_______
    Uplink 12:
      Optimal Phase: 8
      Window Length: 35
      Eye Window: __________________________XXXXX_________
    Uplink 13:
      Optimal Phase: 11
      Window Length: 35
      Eye Window: _____________________________XXXXX______
    Uplink 14:
      Optimal Phase: 10
      Window Length: 36
      Eye Window: _____________________________XXXX_______
    Uplink 15:
      Optimal Phase: 12
      Window Length: 35
      Eye Window: ______________________________XXXXX_____
]
08:33:11:setup_element:INFO:	Beginning SMX ASICs map scan
08:33:12:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
08:33:12:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [1]
08:33:12:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [1]
08:33:12:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [1]
08:33:12:uplink:INFO:	Setting uplinks mask [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
08:33:12:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 0, uplink 1
08:33:12:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 1, uplink 0
08:33:12:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 0, uplink 8
08:33:12:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 1, uplink 9
08:33:12:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 0, uplink 3
08:33:12:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 1, uplink 2
08:33:12:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 0, uplink 10
08:33:12:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 1, uplink 11
08:33:12:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 0, uplink 5
08:33:12:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 1, uplink 4
08:33:13:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 0, uplink 12
08:33:13:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 1, uplink 13
08:33:13:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 0, uplink 7
08:33:13:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 1, uplink 6
08:33:13:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 0, uplink 14
08:33:13:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 1, uplink 15
08:33:14:ST3_emu:ERROR:	
Setup Element:
  Group: 0
  Downlink: 1
  Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
  ASICs Map:
    ASIC address 0x0: (ASIC uplink, uplink): (0, 1), (1, 0)
    ASIC address 0x1: (ASIC uplink, uplink): (0, 8), (1, 9)
    ASIC address 0x2: (ASIC uplink, uplink): (0, 3), (1, 2)
    ASIC address 0x3: (ASIC uplink, uplink): (0, 10), (1, 11)
    ASIC address 0x4: (ASIC uplink, uplink): (0, 5), (1, 4)
    ASIC address 0x5: (ASIC uplink, uplink): (0, 12), (1, 13)
    ASIC address 0x6: (ASIC uplink, uplink): (0, 7), (1, 6)
    ASIC address 0x7: (ASIC uplink, uplink): (0, 14), (1, 15)
  Clock Phase Characteristic:
    Optimal Phase: 33
    Window Length: 69
    Eye Windows:
      Uplink  0: _______________________________________________________________________XXXXXXXX_
      Uplink  1: _______________________________________________________________________XXXXXXXX_
      Uplink  2: ______________________________________________________________________XXXXXXXX__
      Uplink  3: ______________________________________________________________________XXXXXXXX__
      Uplink  4: _____________________________________________________________________XXXXXXX____
      Uplink  5: _____________________________________________________________________XXXXXXX____
      Uplink  6: ________________________________________________________________________XXXXXX__
      Uplink  7: ________________________________________________________________________XXXXXX__
      Uplink  8: ____________________________________________________________________XXXXXXXXX___
      Uplink  9: ____________________________________________________________________XXXXXXXXX___
      Uplink 10: ________________________________________________________________________________
      Uplink 11: ________________________________________________________________________________
      Uplink 12: _____________________________________________________________________XXXXXXXX___
      Uplink 13: _____________________________________________________________________XXXXXXXX___
      Uplink 14: ________________________________________________________________________XXXXX___
      Uplink 15: ________________________________________________________________________XXXXX___
  Data phase characteristics:
    Uplink 0:
      Optimal Phase: 32
      Window Length: 34
      Eye Window: __________XXXXXX________________________
    Uplink 1:
      Optimal Phase: 28
      Window Length: 35
      Eye Window: ______XXXXX_____________________________
    Uplink 2:
      Optimal Phase: 27
      Window Length: 35
      Eye Window: _____XXXXX______________________________
    Uplink 3:
      Optimal Phase: 24
      Window Length: 34
      Eye Window: __XXXXXX________________________________
    Uplink 4:
      Optimal Phase: 24
      Window Length: 35
      Eye Window: __XXXXX_________________________________
    Uplink 5:
      Optimal Phase: 19
      Window Length: 34
      Eye Window: XXX__________________________________XXX
    Uplink 6:
      Optimal Phase: 20
      Window Length: 34
      Eye Window: XXXX__________________________________XX
    Uplink 7:
      Optimal Phase: 17
      Window Length: 34
      Eye Window: X__________________________________XXXXX
    Uplink 8:
      Optimal Phase: 7
      Window Length: 35
      Eye Window: _________________________XXXXX__________
    Uplink 9:
      Optimal Phase: 12
      Window Length: 35
      Eye Window: ______________________________XXXXX_____
    Uplink 10:
      Optimal Phase: 7
      Window Length: 35
      Eye Window: _________________________XXXXX__________
    Uplink 11:
      Optimal Phase: 10
      Window Length: 35
      Eye Window: ____________________________XXXXX_______
    Uplink 12:
      Optimal Phase: 8
      Window Length: 35
      Eye Window: __________________________XXXXX_________
    Uplink 13:
      Optimal Phase: 11
      Window Length: 35
      Eye Window: _____________________________XXXXX______
    Uplink 14:
      Optimal Phase: 10
      Window Length: 36
      Eye Window: _____________________________XXXX_______
    Uplink 15:
      Optimal Phase: 12
      Window Length: 35
      Eye Window: ______________________________XXXXX_____

08:33:14:setup_element:INFO:	Performing Elink synchronization
08:33:14:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
08:33:14:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [1]
08:33:14:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [1]
08:33:14:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [1]
08:33:14:setup_element:INFO:	Writing SMX Elink masks for group 0, downlink 1
08:33:14:uplink:INFO:	Enabling uplinks [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
08:33:15:ST3_emu:INFO:	Number of chips: 8
addr  |  upli  |  dwnli  |  grp |  uplinks | uplinks_map
   0  |   [0]   |  1  |  0  |     [1]      |   [(0, 1), (1, 0)] 
   1  |   [0]   |  1  |  0  |     [8]      |   [(0, 8), (1, 9)] 
   2  |   [0]   |  1  |  0  |     [3]      |   [(0, 3), (1, 2)] 
   3  |   [0]   |  1  |  0  |     [10]     |  [(0, 10), (1, 11)]
   4  |   [0]   |  1  |  0  |     [5]      |   [(0, 5), (1, 4)] 
   5  |   [0]   |  1  |  0  |     [12]     |  [(0, 12), (1, 13)]
   6  |   [0]   |  1  |  0  |     [7]      |   [(0, 7), (1, 6)] 
   7  |   [0]   |  1  |  0  |     [14]     |  [(0, 14), (1, 15)]
08:33:15:febtest:INFO:	 Add. | ASIC-ID                      | T [C] | Vddm [mV]
08:33:16:febtest:INFO:	1-0 | XA-000-08-002-000-005-029-02 |  21.9 | 1242.0
08:33:16:febtest:INFO:	8-1 | XA-000-08-002-000-005-043-11 |  15.6 | 1265.4
08:33:16:febtest:INFO:	3-2 | XA-000-08-002-000-004-120-04 |  34.6 | 1212.7
08:33:16:febtest:INFO:	10-3 | XA-000-08-002-000-005-042-11 |  25.1 | 1224.5
08:33:17:febtest:INFO:	5-4 | XA-000-08-002-000-005-046-11 |  31.4 | 1218.6
08:33:17:febtest:INFO:	12-5 | XA-000-08-002-000-005-041-11 |  15.6 | 1259.6
08:33:17:febtest:INFO:	7-6 | XA-000-08-002-000-005-044-11 |  25.1 | 1242.0
08:33:17:febtest:INFO:	14-7 | XA-000-08-002-000-005-040-11 |  21.9 | 1236.2
08:33:18:ST3_smx:INFO:	Configuring SMX FAST
08:33:19:ST3_smx:INFO:	chip: 1-0 	 28.225000 C 	 1230.330540 mV
08:33:19:ST3_smx:INFO:		Electrons
08:33:19:ST3_smx:INFO:	# loops 0
08:33:21:ST3_smx:INFO:	# loops 1
08:33:23:ST3_smx:INFO:	# loops 2
08:33:24:ST3_smx:INFO:	# loops 3
08:33:26:ST3_smx:INFO:	# loops 4
08:33:27:ST3_smx:INFO:	Total # of broken channels: 1
08:33:27:ST3_smx:INFO:	List of broken channels: [127]
08:33:27:ST3_smx:INFO:	Total # of broken channels: 1
08:33:27:ST3_smx:INFO:	List of broken channels: [127]
08:33:28:ST3_smx:INFO:	Configuring SMX FAST
08:33:29:ST3_smx:INFO:	chip: 8-1 	 15.590880 C 	 1282.867635 mV
08:33:29:ST3_smx:INFO:		Electrons
08:33:30:ST3_smx:INFO:	# loops 0
08:33:31:ST3_smx:INFO:	# loops 1
08:33:33:ST3_smx:INFO:	# loops 2
08:33:35:ST3_smx:INFO:	# loops 3
08:33:36:ST3_smx:INFO:	# loops 4
08:33:38:ST3_smx:INFO:	Total # of broken channels: 1
08:33:38:ST3_smx:INFO:	List of broken channels: [79]
08:33:38:ST3_smx:INFO:	Total # of broken channels: 1
08:33:38:ST3_smx:INFO:	List of broken channels: [79]
08:33:38:ST3_smx:INFO:	Configuring SMX FAST
08:33:40:ST3_smx:INFO:	chip: 3-2 	 37.726682 C 	 1195.082160 mV
08:33:40:ST3_smx:INFO:		Electrons
08:33:40:ST3_smx:INFO:	# loops 0
08:33:42:ST3_smx:INFO:	# loops 1
08:33:43:ST3_smx:INFO:	# loops 2
08:33:45:ST3_smx:INFO:	# loops 3
08:33:46:ST3_smx:INFO:	# loops 4
08:33:48:ST3_smx:INFO:	Total # of broken channels: 0
08:33:48:ST3_smx:INFO:	List of broken channels: []
08:33:48:ST3_smx:INFO:	Total # of broken channels: 0
08:33:48:ST3_smx:INFO:	List of broken channels: []
08:33:48:ST3_smx:INFO:	Configuring SMX FAST
08:33:50:ST3_smx:INFO:	chip: 10-3 	 28.225000 C 	 1218.600960 mV
08:33:50:ST3_smx:INFO:		Electrons
08:33:50:ST3_smx:INFO:	# loops 0
08:33:52:ST3_smx:INFO:	# loops 1
08:33:53:ST3_smx:INFO:	# loops 2
08:33:55:ST3_smx:INFO:	# loops 3
08:33:56:ST3_smx:INFO:	# loops 4
08:33:58:ST3_smx:INFO:	Total # of broken channels: 0
08:33:58:ST3_smx:INFO:	List of broken channels: []
08:33:58:ST3_smx:INFO:	Total # of broken channels: 0
08:33:58:ST3_smx:INFO:	List of broken channels: []
08:33:58:ST3_smx:INFO:	Configuring SMX FAST
08:34:00:ST3_smx:INFO:	chip: 5-4 	 40.898880 C 	 1195.082160 mV
08:34:00:ST3_smx:INFO:		Electrons
08:34:00:ST3_smx:INFO:	# loops 0
08:34:02:ST3_smx:INFO:	# loops 1
08:34:04:ST3_smx:INFO:	# loops 2
08:34:05:ST3_smx:INFO:	# loops 3
08:34:07:ST3_smx:INFO:	# loops 4
08:34:09:ST3_smx:INFO:	Total # of broken channels: 0
08:34:09:ST3_smx:INFO:	List of broken channels: []
08:34:09:ST3_smx:INFO:	Total # of broken channels: 0
08:34:09:ST3_smx:INFO:	List of broken channels: []
08:34:09:ST3_smx:INFO:	Configuring SMX FAST
08:34:11:ST3_smx:INFO:	chip: 12-5 	 25.062742 C 	 1230.330540 mV
08:34:11:ST3_smx:INFO:		Electrons
08:34:11:ST3_smx:INFO:	# loops 0
08:34:12:ST3_smx:INFO:	# loops 1
08:34:14:ST3_smx:INFO:	# loops 2
08:34:15:ST3_smx:INFO:	# loops 3
08:34:17:ST3_smx:INFO:	# loops 4
08:34:19:ST3_smx:INFO:	Total # of broken channels: 0
08:34:19:ST3_smx:INFO:	List of broken channels: []
08:34:19:ST3_smx:INFO:	Total # of broken channels: 0
08:34:19:ST3_smx:INFO:	List of broken channels: []
08:34:19:ST3_smx:INFO:	Configuring SMX FAST
08:34:21:ST3_smx:INFO:	chip: 7-6 	 31.389742 C 	 1230.330540 mV
08:34:21:ST3_smx:INFO:		Electrons
08:34:21:ST3_smx:INFO:	# loops 0
08:34:22:ST3_smx:INFO:	# loops 1
08:34:24:ST3_smx:INFO:	# loops 2
08:34:26:ST3_smx:INFO:	# loops 3
08:34:27:ST3_smx:INFO:	# loops 4
08:34:29:ST3_smx:INFO:	Total # of broken channels: 0
08:34:29:ST3_smx:INFO:	List of broken channels: []
08:34:29:ST3_smx:INFO:	Total # of broken channels: 1
08:34:29:ST3_smx:INFO:	List of broken channels: [48]
08:34:29:ST3_smx:INFO:	Configuring SMX FAST
08:34:31:ST3_smx:INFO:	chip: 14-7 	 31.389742 C 	 1212.728715 mV
08:34:31:ST3_smx:INFO:		Electrons
08:34:31:ST3_smx:INFO:	# loops 0
08:34:33:ST3_smx:INFO:	# loops 1
08:34:34:ST3_smx:INFO:	# loops 2
08:34:36:ST3_smx:INFO:	# loops 3
08:34:37:ST3_smx:INFO:	# loops 4
08:34:39:ST3_smx:INFO:	Total # of broken channels: 0
08:34:39:ST3_smx:INFO:	List of broken channels: []
08:34:39:ST3_smx:INFO:	Total # of broken channels: 0
08:34:39:ST3_smx:INFO:	List of broken channels: []
08:34:39:febtest:INFO:	 Add. | ASIC-ID                      | T [C] | Vddm [mV]
08:34:40:febtest:INFO:	1-0 | XA-000-08-002-000-005-029-02 |  28.2 | 1230.3
08:34:40:febtest:INFO:	8-1 | XA-000-08-002-000-005-043-11 |  18.7 | 1288.7
08:34:40:febtest:INFO:	3-2 | XA-000-08-002-000-004-120-04 |  40.9 | 1195.1
08:34:40:febtest:INFO:	10-3 | XA-000-08-002-000-005-042-11 |  31.4 | 1218.6
08:34:41:febtest:INFO:	5-4 | XA-000-08-002-000-005-046-11 |  40.9 | 1201.0
08:34:41:febtest:INFO:	12-5 | XA-000-08-002-000-005-041-11 |  28.2 | 1230.3
08:34:41:febtest:INFO:	7-6 | XA-000-08-002-000-005-044-11 |  31.4 | 1230.3
08:34:41:febtest:INFO:	14-7 | XA-000-08-002-000-005-040-11 |  31.4 | 1206.9
############################################################
#                   S U M M A R Y                          #
############################################################
TEST_NAME : FEB-Sensor
TEST_DATE : 2024_01_09-08_32_26
OPERATOR  : Olga B.; Oleksandr S.; 
SITE      : GSI
SETUP     : GSI_TEST_SETUP_1
Set-ID    : 
---------------------------------------
MODULE_NAME : L4UL201031 M4UL2T2010312B2 42 A

FEB_SN : 1064
FEB_TYPE : 8.2
FEB_UPLINKS : 2
FEB_A : 1
FEB_B : 0
---------------------------------------
SENSOR_ID:	07402

MODULE_NAME:	L4UL201031 M4UL2T2010312B2 42 A

MODULE_TYPE:	
MODULE_LADDER:	L4UL201031
MODULE_MODULE:	M4UL2T2010312B2
MODULE_SIZE:	42
MODULE_GRADE:	A
---------------------------------------
VI_before_Init : ['2.450', '1.7810', '1.851', '0.4859', '7.000', '1.5490', '7.000', '1.5490']
VI_after__Init : ['2.450', '1.9980', '1.850', '0.5855', '7.000', '1.5500', '7.000', '1.5500']
VI_at__the_End : ['0', '0', '0', '0', '0', '0']
08:35:35:ST3_Shared:INFO:	/home/cbm/public_html/Production_LogDir//FEB/FEB_1064/TestDate_2024_01_09-08_32_26/
07:41:56:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
07:41:56:ST3_Shared:INFO:	-------------------------FEB-Sensor-------------------------
07:41:56:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
07:41:58:ST3_ModuleSelector:INFO:	L4UL201031 M4UL2T2010312B2 42 A

07:41:58:ST3_ModuleSelector:INFO:	07402

07:41:58:febtest:INFO:	Testing FEB with SN 2046
07:42:16:febtest:INFO:	FEB 8-2 selected
07:42:16:smx_tester:INFO:	Setting Elink clock mode to 160 MHz
07:42:19:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
07:42:19:ST3_Shared:INFO:	-------------------------FEB-Sensor-------------------------
07:42:19:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
07:42:43:ST3_ModuleSelector:INFO:	L4UL201031 M4UL2T4010314B2 124 C

07:42:43:ST3_ModuleSelector:INFO:	29064

07:42:43:febtest:INFO:	Testing FEB with SN 2046
07:42:44:smx_tester:INFO:	Scanning setup
07:42:44:elinks:INFO:	Disabling clock on downlink 0
07:42:44:elinks:INFO:	Disabling clock on downlink 1
07:42:44:elinks:INFO:	Disabling clock on downlink 2
07:42:44:elinks:INFO:	Disabling clock on downlink 3
07:42:44:elinks:INFO:	Disabling clock on downlink 4
07:42:44:setup_element:INFO:	Checking SOS, encoding_mode: SOS
07:42:44:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
07:42:44:setup_element:INFO:	SOS detected for group 0, downlink 0, uplink 0
07:42:44:setup_element:INFO:	SOS detected for group 0, downlink 0, uplink 1
07:42:44:setup_element:INFO:	SOS detected for group 0, downlink 0, uplink 2
07:42:44:setup_element:INFO:	SOS detected for group 0, downlink 0, uplink 3
07:42:44:setup_element:INFO:	SOS detected for group 0, downlink 0, uplink 4
07:42:44:setup_element:INFO:	SOS detected for group 0, downlink 0, uplink 5
07:42:44:setup_element:INFO:	SOS detected for group 0, downlink 0, uplink 6
07:42:44:setup_element:INFO:	SOS detected for group 0, downlink 0, uplink 7
07:42:44:setup_element:INFO:	SOS detected for group 0, downlink 0, uplink 8
07:42:44:setup_element:INFO:	SOS detected for group 0, downlink 0, uplink 9
07:42:44:setup_element:INFO:	SOS detected for group 0, downlink 0, uplink 10
07:42:44:setup_element:INFO:	SOS detected for group 0, downlink 0, uplink 11
07:42:44:setup_element:INFO:	SOS detected for group 0, downlink 0, uplink 12
07:42:44:setup_element:INFO:	SOS detected for group 0, downlink 0, uplink 13
07:42:44:setup_element:INFO:	SOS detected for group 0, downlink 0, uplink 14
07:42:44:setup_element:INFO:	SOS detected for group 0, downlink 0, uplink 15
07:42:44:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
07:42:44:elinks:INFO:	Disabling clock on downlink 0
07:42:44:elinks:INFO:	Disabling clock on downlink 1
07:42:44:elinks:INFO:	Disabling clock on downlink 2
07:42:44:elinks:INFO:	Disabling clock on downlink 3
07:42:44:elinks:INFO:	Disabling clock on downlink 4
07:42:44:setup_element:INFO:	Checking SOS, encoding_mode: SOS
07:42:44:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
07:42:44:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
07:42:44:elinks:INFO:	Disabling clock on downlink 0
07:42:44:elinks:INFO:	Disabling clock on downlink 1
07:42:44:elinks:INFO:	Disabling clock on downlink 2
07:42:44:elinks:INFO:	Disabling clock on downlink 3
07:42:44:elinks:INFO:	Disabling clock on downlink 4
07:42:44:setup_element:INFO:	Checking SOS, encoding_mode: SOS
07:42:44:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
07:42:45:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
07:42:45:elinks:INFO:	Disabling clock on downlink 0
07:42:45:elinks:INFO:	Disabling clock on downlink 1
07:42:45:elinks:INFO:	Disabling clock on downlink 2
07:42:45:elinks:INFO:	Disabling clock on downlink 3
07:42:45:elinks:INFO:	Disabling clock on downlink 4
07:42:45:setup_element:INFO:	Checking SOS, encoding_mode: SOS
07:42:45:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
07:42:45:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
07:42:45:elinks:INFO:	Disabling clock on downlink 0
07:42:45:elinks:INFO:	Disabling clock on downlink 1
07:42:45:elinks:INFO:	Disabling clock on downlink 2
07:42:45:elinks:INFO:	Disabling clock on downlink 3
07:42:45:elinks:INFO:	Disabling clock on downlink 4
07:42:45:setup_element:INFO:	Checking SOS, encoding_mode: SOS
07:42:45:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [4]
07:42:45:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
07:42:45:setup_element:INFO:	Scanning clock phase
07:42:45:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
07:42:45:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [0]
07:42:45:setup_element:INFO:	Clock phase scan results for group 0, downlink 0
07:42:45:setup_element:INFO:	Eye window for uplink 0 : ________________________________________________________________________XXXXXXXX
Clock Delay: 35
07:42:45:setup_element:INFO:	Eye window for uplink 1 : ________________________________________________________________________XXXXXXXX
Clock Delay: 35
07:42:45:setup_element:INFO:	Eye window for uplink 2 : _______________________________________________________________________XXXXXXXXX
Clock Delay: 35
07:42:45:setup_element:INFO:	Eye window for uplink 3 : _______________________________________________________________________XXXXXXXXX
Clock Delay: 35
07:42:45:setup_element:INFO:	Eye window for uplink 4 : X_______________________________________________________________________XXXXXXXX
Clock Delay: 36
07:42:45:setup_element:INFO:	Eye window for uplink 5 : X________________________________________________________________________XXXXXXX
Clock Delay: 36
07:42:45:setup_element:INFO:	Eye window for uplink 6 : ________________________________________________________________________XXXXXXXX
Clock Delay: 35
07:42:45:setup_element:INFO:	Eye window for uplink 7 : ________________________________________________________________________XXXXXXXX
Clock Delay: 35
07:42:45:setup_element:INFO:	Eye window for uplink 8 : ________________________________________________________________________XXXXXXXX
Clock Delay: 35
07:42:45:setup_element:INFO:	Eye window for uplink 9 : ________________________________________________________________________XXXXXXXX
Clock Delay: 35
07:42:45:setup_element:INFO:	Eye window for uplink 10: ________________________________________________________________________XXXXXXX_
Clock Delay: 35
07:42:45:setup_element:INFO:	Eye window for uplink 11: ________________________________________________________________________XXXXXXX_
Clock Delay: 35
07:42:45:setup_element:INFO:	Eye window for uplink 12: X_________________________________________________________________________XXXXXX
Clock Delay: 37
07:42:45:setup_element:INFO:	Eye window for uplink 13: X_________________________________________________________________________XXXXXX
Clock Delay: 37
07:42:45:setup_element:INFO:	Eye window for uplink 14: X_________________________________________________________________________XXXXXX
Clock Delay: 37
07:42:45:setup_element:INFO:	Eye window for uplink 15: X_________________________________________________________________________XXXXXX
Clock Delay: 37
07:42:45:setup_element:INFO:	Setting the clock phase to 35 for group 0, downlink 0
07:42:45:setup_element:INFO:	Scanning data phases
07:42:45:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
07:42:45:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [0]
07:42:50:setup_element:INFO:	Data phase scan results for group 0, downlink 0
07:42:50:setup_element:INFO:	Eye window for uplink 0 : _______________________________XXXXX____
Data delay found: 13
07:42:50:setup_element:INFO:	Eye window for uplink 1 : ___________________________XXXXX________
Data delay found: 9
07:42:50:setup_element:INFO:	Eye window for uplink 2 : ______________________________XXXXXX____
Data delay found: 12
07:42:50:setup_element:INFO:	Eye window for uplink 3 : ____________________________XXXXXX______
Data delay found: 10
07:42:50:setup_element:INFO:	Eye window for uplink 4 : _________________________________XXXXXX_
Data delay found: 15
07:42:50:setup_element:INFO:	Eye window for uplink 5 : ______________________________XXXXX_____
Data delay found: 12
07:42:50:setup_element:INFO:	Eye window for uplink 6 : ______________________________XXXXX_____
Data delay found: 12
07:42:50:setup_element:INFO:	Eye window for uplink 7 : ___________________________XXXXX________
Data delay found: 9
07:42:50:setup_element:INFO:	Eye window for uplink 8 : _________________________________XXXXX__
Data delay found: 15
07:42:50:setup_element:INFO:	Eye window for uplink 9 : XXXX__________________________________XX
Data delay found: 20
07:42:50:setup_element:INFO:	Eye window for uplink 10: XXXXX__________________________________X
Data delay found: 21
07:42:50:setup_element:INFO:	Eye window for uplink 11: ___XXXXXXX______________________________
Data delay found: 26
07:42:50:setup_element:INFO:	Eye window for uplink 12: _______XXXX_____________________________
Data delay found: 28
07:42:50:setup_element:INFO:	Eye window for uplink 13: _________XXXXX__________________________
Data delay found: 31
07:42:50:setup_element:INFO:	Eye window for uplink 14: _________XXXXX___XXXXXXXXXXXXXXXXXXXXXXX
Data delay found: 4
07:42:50:setup_element:INFO:	Eye window for uplink 15: ___________XXXXX_XXXXXXXXXXXXXXXXXXXXXXX
Data delay found: 5
07:42:50:setup_element:INFO:	Setting the data phase to 13 for uplink 0
07:42:50:setup_element:INFO:	Setting the data phase to 9 for uplink 1
07:42:50:setup_element:INFO:	Setting the data phase to 12 for uplink 2
07:42:50:setup_element:INFO:	Setting the data phase to 10 for uplink 3
07:42:50:setup_element:INFO:	Setting the data phase to 15 for uplink 4
07:42:50:setup_element:INFO:	Setting the data phase to 12 for uplink 5
07:42:50:setup_element:INFO:	Setting the data phase to 12 for uplink 6
07:42:50:setup_element:INFO:	Setting the data phase to 9 for uplink 7
07:42:50:setup_element:INFO:	Setting the data phase to 15 for uplink 8
07:42:50:setup_element:INFO:	Setting the data phase to 20 for uplink 9
07:42:50:setup_element:INFO:	Setting the data phase to 21 for uplink 10
07:42:50:setup_element:INFO:	Setting the data phase to 26 for uplink 11
07:42:50:setup_element:INFO:	Setting the data phase to 28 for uplink 12
07:42:50:setup_element:INFO:	Setting the data phase to 31 for uplink 13
07:42:50:setup_element:INFO:	Setting the data phase to 4 for uplink 14
07:42:50:setup_element:INFO:	Setting the data phase to 5 for uplink 15
07:42:50:ST3_emu:ERROR:	[
Setup Element:
  Group: 0
  Downlink: 0
  Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
  ASICs Map: None
  Clock Phase Characteristic:
    Optimal Phase: 35
    Window Length: 70
    Eye Windows:
      Uplink  0: ________________________________________________________________________XXXXXXXX
      Uplink  1: ________________________________________________________________________XXXXXXXX
      Uplink  2: _______________________________________________________________________XXXXXXXXX
      Uplink  3: _______________________________________________________________________XXXXXXXXX
      Uplink  4: X_______________________________________________________________________XXXXXXXX
      Uplink  5: X________________________________________________________________________XXXXXXX
      Uplink  6: ________________________________________________________________________XXXXXXXX
      Uplink  7: ________________________________________________________________________XXXXXXXX
      Uplink  8: ________________________________________________________________________XXXXXXXX
      Uplink  9: ________________________________________________________________________XXXXXXXX
      Uplink 10: ________________________________________________________________________XXXXXXX_
      Uplink 11: ________________________________________________________________________XXXXXXX_
      Uplink 12: X_________________________________________________________________________XXXXXX
      Uplink 13: X_________________________________________________________________________XXXXXX
      Uplink 14: X_________________________________________________________________________XXXXXX
      Uplink 15: X_________________________________________________________________________XXXXXX
  Data phase characteristics:
    Uplink 0:
      Optimal Phase: 13
      Window Length: 35
      Eye Window: _______________________________XXXXX____
    Uplink 1:
      Optimal Phase: 9
      Window Length: 35
      Eye Window: ___________________________XXXXX________
    Uplink 2:
      Optimal Phase: 12
      Window Length: 34
      Eye Window: ______________________________XXXXXX____
    Uplink 3:
      Optimal Phase: 10
      Window Length: 34
      Eye Window: ____________________________XXXXXX______
    Uplink 4:
      Optimal Phase: 15
      Window Length: 34
      Eye Window: _________________________________XXXXXX_
    Uplink 5:
      Optimal Phase: 12
      Window Length: 35
      Eye Window: ______________________________XXXXX_____
    Uplink 6:
      Optimal Phase: 12
      Window Length: 35
      Eye Window: ______________________________XXXXX_____
    Uplink 7:
      Optimal Phase: 9
      Window Length: 35
      Eye Window: ___________________________XXXXX________
    Uplink 8:
      Optimal Phase: 15
      Window Length: 35
      Eye Window: _________________________________XXXXX__
    Uplink 9:
      Optimal Phase: 20
      Window Length: 34
      Eye Window: XXXX__________________________________XX
    Uplink 10:
      Optimal Phase: 21
      Window Length: 34
      Eye Window: XXXXX__________________________________X
    Uplink 11:
      Optimal Phase: 26
      Window Length: 33
      Eye Window: ___XXXXXXX______________________________
    Uplink 12:
      Optimal Phase: 28
      Window Length: 36
      Eye Window: _______XXXX_____________________________
    Uplink 13:
      Optimal Phase: 31
      Window Length: 35
      Eye Window: _________XXXXX__________________________
    Uplink 14:
      Optimal Phase: 4
      Window Length: 9
      Eye Window: _________XXXXX___XXXXXXXXXXXXXXXXXXXXXXX
    Uplink 15:
      Optimal Phase: 5
      Window Length: 11
      Eye Window: ___________XXXXX_XXXXXXXXXXXXXXXXXXXXXXX
]
07:42:50:setup_element:INFO:	Beginning SMX ASICs map scan
07:42:50:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
07:42:50:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [0]
07:42:50:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [0]
07:42:50:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [0]
07:42:50:uplink:INFO:	Setting uplinks mask [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
07:42:50:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 0, uplink 7
07:42:50:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 1, uplink 6
07:42:51:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 0, uplink 14
07:42:51:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 1, uplink 15
07:42:51:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 0, uplink 5
07:42:51:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 1, uplink 4
07:42:51:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 0, uplink 12
07:42:51:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 1, uplink 13
07:42:51:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 0, uplink 3
07:42:51:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 1, uplink 2
07:42:51:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 0, uplink 10
07:42:51:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 1, uplink 11
07:42:51:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 0, uplink 1
07:42:51:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 1, uplink 0
07:42:52:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 0, uplink 8
07:42:52:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 1, uplink 9
07:42:53:ST3_emu:ERROR:	
Setup Element:
  Group: 0
  Downlink: 0
  Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
  ASICs Map:
    ASIC address 0x0: (ASIC uplink, uplink): (0, 7), (1, 6)
    ASIC address 0x1: (ASIC uplink, uplink): (0, 14), (1, 15)
    ASIC address 0x2: (ASIC uplink, uplink): (0, 5), (1, 4)
    ASIC address 0x3: (ASIC uplink, uplink): (0, 12), (1, 13)
    ASIC address 0x4: (ASIC uplink, uplink): (0, 3), (1, 2)
    ASIC address 0x5: (ASIC uplink, uplink): (0, 10), (1, 11)
    ASIC address 0x6: (ASIC uplink, uplink): (0, 1), (1, 0)
    ASIC address 0x7: (ASIC uplink, uplink): (0, 8), (1, 9)
  Clock Phase Characteristic:
    Optimal Phase: 35
    Window Length: 70
    Eye Windows:
      Uplink  0: ________________________________________________________________________XXXXXXXX
      Uplink  1: ________________________________________________________________________XXXXXXXX
      Uplink  2: _______________________________________________________________________XXXXXXXXX
      Uplink  3: _______________________________________________________________________XXXXXXXXX
      Uplink  4: X_______________________________________________________________________XXXXXXXX
      Uplink  5: X________________________________________________________________________XXXXXXX
      Uplink  6: ________________________________________________________________________XXXXXXXX
      Uplink  7: ________________________________________________________________________XXXXXXXX
      Uplink  8: ________________________________________________________________________XXXXXXXX
      Uplink  9: ________________________________________________________________________XXXXXXXX
      Uplink 10: ________________________________________________________________________XXXXXXX_
      Uplink 11: ________________________________________________________________________XXXXXXX_
      Uplink 12: X_________________________________________________________________________XXXXXX
      Uplink 13: X_________________________________________________________________________XXXXXX
      Uplink 14: X_________________________________________________________________________XXXXXX
      Uplink 15: X_________________________________________________________________________XXXXXX
  Data phase characteristics:
    Uplink 0:
      Optimal Phase: 13
      Window Length: 35
      Eye Window: _______________________________XXXXX____
    Uplink 1:
      Optimal Phase: 9
      Window Length: 35
      Eye Window: ___________________________XXXXX________
    Uplink 2:
      Optimal Phase: 12
      Window Length: 34
      Eye Window: ______________________________XXXXXX____
    Uplink 3:
      Optimal Phase: 10
      Window Length: 34
      Eye Window: ____________________________XXXXXX______
    Uplink 4:
      Optimal Phase: 15
      Window Length: 34
      Eye Window: _________________________________XXXXXX_
    Uplink 5:
      Optimal Phase: 12
      Window Length: 35
      Eye Window: ______________________________XXXXX_____
    Uplink 6:
      Optimal Phase: 12
      Window Length: 35
      Eye Window: ______________________________XXXXX_____
    Uplink 7:
      Optimal Phase: 9
      Window Length: 35
      Eye Window: ___________________________XXXXX________
    Uplink 8:
      Optimal Phase: 15
      Window Length: 35
      Eye Window: _________________________________XXXXX__
    Uplink 9:
      Optimal Phase: 20
      Window Length: 34
      Eye Window: XXXX__________________________________XX
    Uplink 10:
      Optimal Phase: 21
      Window Length: 34
      Eye Window: XXXXX__________________________________X
    Uplink 11:
      Optimal Phase: 26
      Window Length: 33
      Eye Window: ___XXXXXXX______________________________
    Uplink 12:
      Optimal Phase: 28
      Window Length: 36
      Eye Window: _______XXXX_____________________________
    Uplink 13:
      Optimal Phase: 31
      Window Length: 35
      Eye Window: _________XXXXX__________________________
    Uplink 14:
      Optimal Phase: 4
      Window Length: 9
      Eye Window: _________XXXXX___XXXXXXXXXXXXXXXXXXXXXXX
    Uplink 15:
      Optimal Phase: 5
      Window Length: 11
      Eye Window: ___________XXXXX_XXXXXXXXXXXXXXXXXXXXXXX

07:42:53:setup_element:INFO:	Performing Elink synchronization
07:42:53:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
07:42:53:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [0]
07:42:53:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [0]
07:42:53:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [0]
07:42:53:setup_element:INFO:	Writing SMX Elink masks for group 0, downlink 0
07:42:53:uplink:INFO:	Enabling uplinks [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
07:42:53:ST3_emu:INFO:	Number of chips: 8
addr  |  upli  |  dwnli  |  grp |  uplinks | uplinks_map
   0  |   [0]   |  0  |  0  |     [7]      |   [(0, 7), (1, 6)] 
   1  |   [0]   |  0  |  0  |     [14]     |  [(0, 14), (1, 15)]
   2  |   [0]   |  0  |  0  |     [5]      |   [(0, 5), (1, 4)] 
   3  |   [0]   |  0  |  0  |     [12]     |  [(0, 12), (1, 13)]
   4  |   [0]   |  0  |  0  |     [3]      |   [(0, 3), (1, 2)] 
   5  |   [0]   |  0  |  0  |     [10]     |  [(0, 10), (1, 11)]
   6  |   [0]   |  0  |  0  |     [1]      |   [(0, 1), (1, 0)] 
   7  |   [0]   |  0  |  0  |     [8]      |   [(0, 8), (1, 9)] 
07:42:54:febtest:INFO:	 Add. | ASIC-ID                      | T [C] | Vddm [mV]
07:42:54:febtest:INFO:	7-0 | XA-000-08-002-000-001-213-11 |  34.6 | 1165.6
07:42:54:febtest:INFO:	14-1 | XA-000-08-002-000-001-004-03 |  37.7 | 1165.6
07:42:54:febtest:INFO:	5-2 | XA-000-08-002-000-001-106-08 |  37.7 | 1171.5
07:42:55:febtest:INFO:	12-3 | XA-000-08-002-000-001-003-03 |  28.2 | 1189.2
07:42:55:febtest:INFO:	3-4 | XA-000-08-002-000-001-103-08 |  25.1 | 1212.7
07:42:55:febtest:INFO:	10-5 | XA-000-08-002-000-001-206-12 |  37.7 | 1141.9
07:42:55:febtest:INFO:	1-6 | XA-000-08-002-000-001-088-01 |  21.9 | 1224.5
07:42:56:febtest:INFO:	8-7 | XA-000-08-002-000-001-203-12 |  40.9 | 1141.9
07:42:56:ST3_smx:INFO:	Configuring SMX FAST
07:42:58:ST3_smx:INFO:	chip: 7-0 	 40.898880 C 	 1147.806000 mV
07:42:58:ST3_smx:INFO:		Electrons
07:42:58:ST3_smx:INFO:	# loops 0
07:43:00:ST3_smx:INFO:	# loops 1
07:43:01:ST3_smx:INFO:	# loops 2
07:43:03:ST3_smx:INFO:	# loops 3
07:43:04:ST3_smx:INFO:	# loops 4
07:43:06:ST3_smx:INFO:	Total # of broken channels: 0
07:43:06:ST3_smx:INFO:	List of broken channels: []
07:43:06:ST3_smx:INFO:	Total # of broken channels: 0
07:43:06:ST3_smx:INFO:	List of broken channels: []
07:43:06:ST3_smx:INFO:	Configuring SMX FAST
07:43:08:ST3_smx:INFO:	chip: 14-1 	 37.726682 C 	 1159.654860 mV
07:43:08:ST3_smx:INFO:		Electrons
07:43:08:ST3_smx:INFO:	# loops 0
07:43:10:ST3_smx:INFO:	# loops 1
07:43:12:ST3_smx:INFO:	# loops 2
07:43:13:ST3_smx:INFO:	# loops 3
07:43:15:ST3_smx:INFO:	# loops 4
07:43:16:ST3_smx:INFO:	Total # of broken channels: 0
07:43:16:ST3_smx:INFO:	List of broken channels: []
07:43:16:ST3_smx:INFO:	Total # of broken channels: 0
07:43:16:ST3_smx:INFO:	List of broken channels: []
07:43:17:ST3_smx:INFO:	Configuring SMX FAST
07:43:19:ST3_smx:INFO:	chip: 5-2 	 37.726682 C 	 1177.390875 mV
07:43:19:ST3_smx:INFO:		Electrons
07:43:19:ST3_smx:INFO:	# loops 0
07:43:20:ST3_smx:INFO:	# loops 1
07:43:22:ST3_smx:INFO:	# loops 2
07:43:23:ST3_smx:INFO:	# loops 3
07:43:25:ST3_smx:INFO:	# loops 4
07:43:27:ST3_smx:INFO:	Total # of broken channels: 0
07:43:27:ST3_smx:INFO:	List of broken channels: []
07:43:27:ST3_smx:INFO:	Total # of broken channels: 0
07:43:27:ST3_smx:INFO:	List of broken channels: []
07:43:27:ST3_smx:INFO:	Configuring SMX FAST
07:43:29:ST3_smx:INFO:	chip: 12-3 	 34.556970 C 	 1189.190035 mV
07:43:29:ST3_smx:INFO:		Electrons
07:43:29:ST3_smx:INFO:	# loops 0
07:43:31:ST3_smx:INFO:	# loops 1
07:43:32:ST3_smx:INFO:	# loops 2
07:43:34:ST3_smx:INFO:	# loops 3
07:43:36:ST3_smx:INFO:	# loops 4
07:43:37:ST3_smx:INFO:	Total # of broken channels: 0
07:43:37:ST3_smx:INFO:	List of broken channels: []
07:43:37:ST3_smx:INFO:	Total # of broken channels: 0
07:43:37:ST3_smx:INFO:	List of broken channels: []
07:43:38:ST3_smx:INFO:	Configuring SMX FAST
07:43:40:ST3_smx:INFO:	chip: 3-4 	 31.389742 C 	 1195.082160 mV
07:43:40:ST3_smx:INFO:		Electrons
07:43:40:ST3_smx:INFO:	# loops 0
07:43:41:ST3_smx:INFO:	# loops 1
07:43:43:ST3_smx:INFO:	# loops 2
07:43:44:ST3_smx:INFO:	# loops 3
07:43:46:ST3_smx:INFO:	# loops 4
07:43:48:ST3_smx:INFO:	Total # of broken channels: 0
07:43:48:ST3_smx:INFO:	List of broken channels: []
07:43:48:ST3_smx:INFO:	Total # of broken channels: 0
07:43:48:ST3_smx:INFO:	List of broken channels: []
07:43:48:ST3_smx:INFO:	Configuring SMX FAST
07:43:50:ST3_smx:INFO:	chip: 10-5 	 44.073563 C 	 1147.806000 mV
07:43:50:ST3_smx:INFO:		Electrons
07:43:50:ST3_smx:INFO:	# loops 0
07:43:51:ST3_smx:INFO:	# loops 1
07:43:53:ST3_smx:INFO:	# loops 2
07:43:55:ST3_smx:INFO:	# loops 3
07:43:56:ST3_smx:INFO:	# loops 4
07:43:58:ST3_smx:INFO:	Total # of broken channels: 0
07:43:58:ST3_smx:INFO:	List of broken channels: []
07:43:58:ST3_smx:INFO:	Total # of broken channels: 0
07:43:58:ST3_smx:INFO:	List of broken channels: []
07:43:58:ST3_smx:INFO:	Configuring SMX FAST
07:44:00:ST3_smx:INFO:	chip: 1-6 	 34.556970 C 	 1195.082160 mV
07:44:00:ST3_smx:INFO:		Electrons
07:44:00:ST3_smx:INFO:	# loops 0
07:44:02:ST3_smx:INFO:	# loops 1
07:44:03:ST3_smx:INFO:	# loops 2
07:44:05:ST3_smx:INFO:	# loops 3
07:44:07:ST3_smx:INFO:	# loops 4
07:44:08:ST3_smx:INFO:	Total # of broken channels: 0
07:44:08:ST3_smx:INFO:	List of broken channels: []
07:44:08:ST3_smx:INFO:	Total # of broken channels: 0
07:44:08:ST3_smx:INFO:	List of broken channels: []
07:44:09:ST3_smx:INFO:	Configuring SMX FAST
07:44:10:ST3_smx:INFO:	chip: 8-7 	 47.250730 C 	 1129.995435 mV
07:44:10:ST3_smx:INFO:		Electrons
07:44:11:ST3_smx:INFO:	# loops 0
07:44:12:ST3_smx:INFO:	# loops 1
07:44:14:ST3_smx:INFO:	# loops 2
07:44:15:ST3_smx:INFO:	# loops 3
07:44:17:ST3_smx:INFO:	# loops 4
07:44:19:ST3_smx:INFO:	Total # of broken channels: 0
07:44:19:ST3_smx:INFO:	List of broken channels: []
07:44:19:ST3_smx:INFO:	Total # of broken channels: 0
07:44:19:ST3_smx:INFO:	List of broken channels: []
07:44:19:febtest:INFO:	 Add. | ASIC-ID                      | T [C] | Vddm [mV]
07:44:19:febtest:INFO:	7-0 | XA-000-08-002-000-001-213-11 |  47.3 | 1147.8
07:44:20:febtest:INFO:	14-1 | XA-000-08-002-000-001-004-03 |  40.9 | 1165.6
07:44:20:febtest:INFO:	5-2 | XA-000-08-002-000-001-106-08 |  40.9 | 1177.4
07:44:20:febtest:INFO:	12-3 | XA-000-08-002-000-001-003-03 |  34.6 | 1189.2
07:44:20:febtest:INFO:	3-4 | XA-000-08-002-000-001-103-08 |  31.4 | 1195.1
07:44:21:febtest:INFO:	10-5 | XA-000-08-002-000-001-206-12 |  44.1 | 1147.8
07:44:21:febtest:INFO:	1-6 | XA-000-08-002-000-001-088-01 |  34.6 | 1195.1
07:44:21:febtest:INFO:	8-7 | XA-000-08-002-000-001-203-12 |  47.3 | 1130.0
############################################################
#                   S U M M A R Y                          #
############################################################
TEST_NAME : FEB-Sensor
TEST_DATE : 2024_01_10-07_42_19
OPERATOR  : Olga B.; Oleksandr S.; 
SITE      : GSI
SETUP     : GSI_TEST_SETUP_1
Set-ID    : 
---------------------------------------
MODULE_NAME : L4UL201031 M4UL2T4010314B2 124 C

FEB_SN : 2046
FEB_TYPE : 8.2
FEB_UPLINKS : 2
FEB_A : 1
FEB_B : 0
---------------------------------------
SENSOR_ID:	29064

MODULE_NAME:	L4UL201031 M4UL2T4010314B2 124 C

MODULE_TYPE:	
MODULE_LADDER:	L4UL201031
MODULE_MODULE:	M4UL2T2010312B2
MODULE_SIZE:	42
MODULE_GRADE:	A
---------------------------------------
VI_before_Init : ['2.450', '1.9060', '1.851', '0.4546', '7.000', '1.5280', '7.000', '1.5280']
VI_after__Init : ['2.450', '1.9990', '1.850', '0.6070', '7.000', '1.5310', '7.000', '1.5310']
VI_at__the_End : ['0', '0', '0', '0', '0', '0']
07:44:30:ST3_Shared:INFO:	/home/cbm/public_html/Production_LogDir//FEB/FEB_2046/TestDate_2024_01_10-07_42_19/