FEB_2076    10.01.24 10:59:36

TextEdit.txt
            10:57:43:ST3_Shared:INFO:	Listo of operators:Oleksandr S.; 
10:59:22:febtest:INFO:	FEB 8-2 selected
10:59:22:smx_tester:INFO:	Setting Elink clock mode to 160 MHz
10:59:36:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
10:59:36:ST3_Shared:INFO:	-----------------------FEB-Microcable-----------------------
10:59:36:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
10:59:37:febtest:INFO:	Testing FEB with SN 2076
10:59:38:smx_tester:INFO:	Scanning setup
10:59:38:elinks:INFO:	Disabling clock on downlink 0
10:59:38:elinks:INFO:	Disabling clock on downlink 1
10:59:38:elinks:INFO:	Disabling clock on downlink 2
10:59:38:elinks:INFO:	Disabling clock on downlink 3
10:59:38:elinks:INFO:	Disabling clock on downlink 4
10:59:38:setup_element:INFO:	Checking SOS, encoding_mode: SOS
10:59:38:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
10:59:38:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
10:59:38:elinks:INFO:	Disabling clock on downlink 0
10:59:38:elinks:INFO:	Disabling clock on downlink 1
10:59:38:elinks:INFO:	Disabling clock on downlink 2
10:59:38:elinks:INFO:	Disabling clock on downlink 3
10:59:38:elinks:INFO:	Disabling clock on downlink 4
10:59:38:setup_element:INFO:	Checking SOS, encoding_mode: SOS
10:59:38:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
10:59:38:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
10:59:38:elinks:INFO:	Disabling clock on downlink 0
10:59:38:elinks:INFO:	Disabling clock on downlink 1
10:59:38:elinks:INFO:	Disabling clock on downlink 2
10:59:38:elinks:INFO:	Disabling clock on downlink 3
10:59:38:elinks:INFO:	Disabling clock on downlink 4
10:59:38:setup_element:INFO:	Checking SOS, encoding_mode: SOS
10:59:38:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
10:59:38:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 24
10:59:38:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 25
10:59:38:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 26
10:59:38:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 27
10:59:38:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 28
10:59:38:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 29
10:59:38:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 30
10:59:38:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 31
10:59:38:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
10:59:38:elinks:INFO:	Disabling clock on downlink 0
10:59:38:elinks:INFO:	Disabling clock on downlink 1
10:59:38:elinks:INFO:	Disabling clock on downlink 2
10:59:38:elinks:INFO:	Disabling clock on downlink 3
10:59:38:elinks:INFO:	Disabling clock on downlink 4
10:59:38:setup_element:INFO:	Checking SOS, encoding_mode: SOS
10:59:38:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
10:59:39:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
10:59:39:elinks:INFO:	Disabling clock on downlink 0
10:59:39:elinks:INFO:	Disabling clock on downlink 1
10:59:39:elinks:INFO:	Disabling clock on downlink 2
10:59:39:elinks:INFO:	Disabling clock on downlink 3
10:59:39:elinks:INFO:	Disabling clock on downlink 4
10:59:39:setup_element:INFO:	Checking SOS, encoding_mode: SOS
10:59:39:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [4]
10:59:39:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
10:59:39:setup_element:INFO:	Scanning clock phase
10:59:39:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
10:59:39:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
10:59:39:setup_element:INFO:	Clock phase scan results for group 0, downlink 2
10:59:39:setup_element:INFO:	Eye window for uplink 24: _______________________________________________________________________XXXXXXXXX
Clock Delay: 35
10:59:39:setup_element:INFO:	Eye window for uplink 25: _______________________________________________________________________XXXXXXXXX
Clock Delay: 35
10:59:39:setup_element:INFO:	Eye window for uplink 26: _______________________________________________________________________XXXXXXXXX
Clock Delay: 35
10:59:39:setup_element:INFO:	Eye window for uplink 27: _______________________________________________________________________XXXXXXXXX
Clock Delay: 35
10:59:39:setup_element:INFO:	Eye window for uplink 28: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
10:59:39:setup_element:INFO:	Eye window for uplink 29: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
10:59:39:setup_element:INFO:	Eye window for uplink 30: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
10:59:39:setup_element:INFO:	Eye window for uplink 31: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
10:59:39:setup_element:INFO:	Setting the clock phase to 34 for group 0, downlink 2
10:59:39:setup_element:INFO:	Scanning data phases
10:59:39:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
10:59:39:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
10:59:44:setup_element:INFO:	Data phase scan results for group 0, downlink 2
10:59:44:setup_element:INFO:	Eye window for uplink 24: ______XXXXXX____________________________
Data delay found: 28
10:59:44:setup_element:INFO:	Eye window for uplink 25: _________XXXXXX_________________________
Data delay found: 31
10:59:44:setup_element:INFO:	Eye window for uplink 26: _________XXXXX__________________________
Data delay found: 31
10:59:44:setup_element:INFO:	Eye window for uplink 27: ____________XXXXXX______________________
Data delay found: 34
10:59:44:setup_element:INFO:	Eye window for uplink 28: ____________XXXXXX______________________
Data delay found: 34
10:59:44:setup_element:INFO:	Eye window for uplink 29: ______________XXXXX_____________________
Data delay found: 36
10:59:44:setup_element:INFO:	Eye window for uplink 30: _____________XXXXXX_____________________
Data delay found: 35
10:59:44:setup_element:INFO:	Eye window for uplink 31: ____________XXXXX_______________________
Data delay found: 34
10:59:44:setup_element:INFO:	Setting the data phase to 28 for uplink 24
10:59:44:setup_element:INFO:	Setting the data phase to 31 for uplink 25
10:59:44:setup_element:INFO:	Setting the data phase to 31 for uplink 26
10:59:44:setup_element:INFO:	Setting the data phase to 34 for uplink 27
10:59:44:setup_element:INFO:	Setting the data phase to 34 for uplink 28
10:59:44:setup_element:INFO:	Setting the data phase to 36 for uplink 29
10:59:44:setup_element:INFO:	Setting the data phase to 35 for uplink 30
10:59:44:setup_element:INFO:	Setting the data phase to 34 for uplink 31
10:59:44:ST3_emu:ERROR:	[
Setup Element:
  Group: 0
  Downlink: 2
  Uplinks: [24, 25, 26, 27, 28, 29, 30, 31]
  ASICs Map: None
  Clock Phase Characteristic:
    Optimal Phase: 34
    Window Length: 70
    Eye Windows:
      Uplink 24: _______________________________________________________________________XXXXXXXXX
      Uplink 25: _______________________________________________________________________XXXXXXXXX
      Uplink 26: _______________________________________________________________________XXXXXXXXX
      Uplink 27: _______________________________________________________________________XXXXXXXXX
      Uplink 28: ______________________________________________________________________XXXXXXXX__
      Uplink 29: ______________________________________________________________________XXXXXXXX__
      Uplink 30: _______________________________________________________________________XXXXXXXX_
      Uplink 31: _______________________________________________________________________XXXXXXXX_
  Data phase characteristics:
    Uplink 24:
      Optimal Phase: 28
      Window Length: 34
      Eye Window: ______XXXXXX____________________________
    Uplink 25:
      Optimal Phase: 31
      Window Length: 34
      Eye Window: _________XXXXXX_________________________
    Uplink 26:
      Optimal Phase: 31
      Window Length: 35
      Eye Window: _________XXXXX__________________________
    Uplink 27:
      Optimal Phase: 34
      Window Length: 34
      Eye Window: ____________XXXXXX______________________
    Uplink 28:
      Optimal Phase: 34
      Window Length: 34
      Eye Window: ____________XXXXXX______________________
    Uplink 29:
      Optimal Phase: 36
      Window Length: 35
      Eye Window: ______________XXXXX_____________________
    Uplink 30:
      Optimal Phase: 35
      Window Length: 34
      Eye Window: _____________XXXXXX_____________________
    Uplink 31:
      Optimal Phase: 34
      Window Length: 35
      Eye Window: ____________XXXXX_______________________
]
10:59:44:setup_element:INFO:	Beginning SMX ASICs map scan
10:59:44:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
10:59:44:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
10:59:45:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
10:59:45:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
10:59:45:uplink:INFO:	Setting uplinks mask [24, 25, 26, 27, 28, 29, 30, 31]
10:59:45:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 0, uplink 30
10:59:45:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 1, uplink 31
10:59:45:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 0, uplink 28
10:59:45:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 1, uplink 29
10:59:45:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 0, uplink 26
10:59:46:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 1, uplink 27
10:59:46:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 0, uplink 24
10:59:46:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 1, uplink 25
10:59:47:ST3_emu:ERROR:	
Setup Element:
  Group: 0
  Downlink: 2
  Uplinks: [24, 25, 26, 27, 28, 29, 30, 31]
  ASICs Map:
    ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
    ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
    ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
    ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
  Clock Phase Characteristic:
    Optimal Phase: 34
    Window Length: 70
    Eye Windows:
      Uplink 24: _______________________________________________________________________XXXXXXXXX
      Uplink 25: _______________________________________________________________________XXXXXXXXX
      Uplink 26: _______________________________________________________________________XXXXXXXXX
      Uplink 27: _______________________________________________________________________XXXXXXXXX
      Uplink 28: ______________________________________________________________________XXXXXXXX__
      Uplink 29: ______________________________________________________________________XXXXXXXX__
      Uplink 30: _______________________________________________________________________XXXXXXXX_
      Uplink 31: _______________________________________________________________________XXXXXXXX_
  Data phase characteristics:
    Uplink 24:
      Optimal Phase: 28
      Window Length: 34
      Eye Window: ______XXXXXX____________________________
    Uplink 25:
      Optimal Phase: 31
      Window Length: 34
      Eye Window: _________XXXXXX_________________________
    Uplink 26:
      Optimal Phase: 31
      Window Length: 35
      Eye Window: _________XXXXX__________________________
    Uplink 27:
      Optimal Phase: 34
      Window Length: 34
      Eye Window: ____________XXXXXX______________________
    Uplink 28:
      Optimal Phase: 34
      Window Length: 34
      Eye Window: ____________XXXXXX______________________
    Uplink 29:
      Optimal Phase: 36
      Window Length: 35
      Eye Window: ______________XXXXX_____________________
    Uplink 30:
      Optimal Phase: 35
      Window Length: 34
      Eye Window: _____________XXXXXX_____________________
    Uplink 31:
      Optimal Phase: 34
      Window Length: 35
      Eye Window: ____________XXXXX_______________________

10:59:47:setup_element:INFO:	Performing Elink synchronization
10:59:47:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
10:59:47:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
10:59:47:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
10:59:47:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
10:59:47:setup_element:INFO:	Writing SMX Elink masks for group 0, downlink 2
10:59:47:uplink:INFO:	Enabling uplinks [24, 25, 26, 27, 28, 29, 30, 31]
10:59:47:ST3_emu:INFO:	Number of chips: 4
addr  |  upli  |  dwnli  |  grp |  uplinks | uplinks_map
   1  |   [0]   |  2  |  0  |     [30]     |  [(0, 30), (1, 31)]
   3  |   [0]   |  2  |  0  |     [28]     |  [(0, 28), (1, 29)]
   5  |   [0]   |  2  |  0  |     [26]     |  [(0, 26), (1, 27)]
   7  |   [0]   |  2  |  0  |     [24]     |  [(0, 24), (1, 25)]
10:59:48:febtest:INFO:	 Add. | ASIC-ID                      | T [C] | Vddm [mV]
10:59:48:febtest:INFO:	30-1 | XA-000-08-002-000-005-230-04 |  21.9 | 1206.9
10:59:48:febtest:INFO:	28-3 | XA-000-08-002-000-005-214-13 |   9.3 | 1265.4
10:59:49:febtest:INFO:	26-5 | XA-000-08-002-000-005-196-10 |  25.1 | 1206.9
10:59:49:febtest:INFO:	24-7 | XA-000-08-002-000-005-183-06 |  37.7 | 1147.8
10:59:49:ST3_smx:INFO:	Configuring SMX FAST
10:59:51:ST3_smx:INFO:	chip: 30-1 	 34.556970 C 	 1165.571835 mV
10:59:51:ST3_smx:INFO:		Electrons
10:59:51:ST3_smx:INFO:	# loops 0
10:59:53:ST3_smx:INFO:	# loops 1
10:59:54:ST3_smx:INFO:	# loops 2
10:59:56:ST3_smx:INFO:	# loops 3
10:59:57:ST3_smx:INFO:	# loops 4
10:59:59:ST3_smx:INFO:	Total # of broken channels: 0
10:59:59:ST3_smx:INFO:	List of broken channels: []
10:59:59:ST3_smx:INFO:	Total # of broken channels: 0
10:59:59:ST3_smx:INFO:	List of broken channels: []
10:59:59:ST3_smx:INFO:	Configuring SMX FAST
11:00:01:ST3_smx:INFO:	chip: 28-3 	 21.902970 C 	 1212.728715 mV
11:00:01:ST3_smx:INFO:		Electrons
11:00:01:ST3_smx:INFO:	# loops 0
11:00:03:ST3_smx:INFO:	# loops 1
11:00:04:ST3_smx:INFO:	# loops 2
11:00:06:ST3_smx:INFO:	# loops 3
11:00:07:ST3_smx:INFO:	# loops 4
11:00:09:ST3_smx:INFO:	Total # of broken channels: 0
11:00:09:ST3_smx:INFO:	List of broken channels: []
11:00:09:ST3_smx:INFO:	Total # of broken channels: 0
11:00:09:ST3_smx:INFO:	List of broken channels: []
11:00:10:ST3_smx:INFO:	Configuring SMX FAST
11:00:11:ST3_smx:INFO:	chip: 26-5 	 34.556970 C 	 1177.390875 mV
11:00:11:ST3_smx:INFO:		Electrons
11:00:11:ST3_smx:INFO:	# loops 0
11:00:13:ST3_smx:INFO:	# loops 1
11:00:15:ST3_smx:INFO:	# loops 2
11:00:16:ST3_smx:INFO:	# loops 3
11:00:18:ST3_smx:INFO:	# loops 4
11:00:20:ST3_smx:INFO:	Total # of broken channels: 0
11:00:20:ST3_smx:INFO:	List of broken channels: []
11:00:20:ST3_smx:INFO:	Total # of broken channels: 0
11:00:20:ST3_smx:INFO:	List of broken channels: []
11:00:20:ST3_smx:INFO:	Configuring SMX FAST
11:00:22:ST3_smx:INFO:	chip: 24-7 	 28.225000 C 	 1177.390875 mV
11:00:22:ST3_smx:INFO:		Electrons
11:00:22:ST3_smx:INFO:	# loops 0
11:00:24:ST3_smx:INFO:	# loops 1
11:00:26:ST3_smx:INFO:	# loops 2
11:00:27:ST3_smx:INFO:	# loops 3
11:00:29:ST3_smx:INFO:	# loops 4
11:00:30:ST3_smx:INFO:	Total # of broken channels: 0
11:00:30:ST3_smx:INFO:	List of broken channels: []
11:00:30:ST3_smx:INFO:	Total # of broken channels: 0
11:00:30:ST3_smx:INFO:	List of broken channels: []
11:00:31:febtest:INFO:	 Add. | ASIC-ID                      | T [C] | Vddm [mV]
11:00:31:febtest:INFO:	30-1 | XA-000-08-002-000-005-230-04 |  37.7 | 1165.6
11:00:31:febtest:INFO:	28-3 | XA-000-08-002-000-005-214-13 |  25.1 | 1212.7
11:00:32:febtest:INFO:	26-5 | XA-000-08-002-000-005-196-10 |  34.6 | 1177.4
11:00:32:febtest:INFO:	24-7 | XA-000-08-002-000-005-183-06 |  28.2 | 1177.4
############################################################
#                   S U M M A R Y                          #
############################################################
TEST_NAME : FEB-Microcable
TEST_DATE : 2024_01_10-10_59_36
OPERATOR  : Oleksandr S.; 
SITE      : GSI
SETUP     : GSI_TEST_SETUP_1
Set-ID    : 
---------------------------------------
MODULE_NAME : L6DL200120 M6DL2B4001204B2 124 C

FEB_SN : 2076
FEB_TYPE : 8.2
FEB_UPLINKS : 2
FEB_A : 1
FEB_B : 0
---------------------------------------
---------------------------------------
VI_before_Init : ['2.449', '0.9268', '1.847', '1.4230', '7.000', '1.5480', '7.000', '1.5480']
VI_after__Init : ['2.450', '1.9830', '1.850', '0.5867', '7.000', '1.5480', '7.000', '1.5480']
VI_at__the_End : ['0', '0', '0', '0', '0', '0']
11:01:49:ST3_Shared:INFO:	/home/cbm/public_html/Production_LogDir//FEB/FEB_2076/TestDate_2024_01_10-10_59_36/