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FEB_2096 05.02.24 12:29:16
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12:29:16:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
12:29:16:ST3_Shared:INFO: -----------------------FEB-Microcable-----------------------
12:29:16:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
12:29:17:febtest:INFO: Testing FEB with SN 2096
12:29:20:smx_tester:INFO: Scanning setup
12:29:20:elinks:INFO: Disabling clock on downlink 0
12:29:20:elinks:INFO: Disabling clock on downlink 1
12:29:20:elinks:INFO: Disabling clock on downlink 2
12:29:20:elinks:INFO: Disabling clock on downlink 3
12:29:20:elinks:INFO: Disabling clock on downlink 4
12:29:20:setup_element:INFO: Checking SOS, encoding_mode: SOS
12:29:20:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
12:29:20:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
12:29:20:elinks:INFO: Disabling clock on downlink 0
12:29:20:elinks:INFO: Disabling clock on downlink 1
12:29:20:elinks:INFO: Disabling clock on downlink 2
12:29:20:elinks:INFO: Disabling clock on downlink 3
12:29:20:elinks:INFO: Disabling clock on downlink 4
12:29:20:setup_element:INFO: Checking SOS, encoding_mode: SOS
12:29:20:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
12:29:20:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
12:29:20:elinks:INFO: Disabling clock on downlink 0
12:29:20:elinks:INFO: Disabling clock on downlink 1
12:29:20:elinks:INFO: Disabling clock on downlink 2
12:29:20:elinks:INFO: Disabling clock on downlink 3
12:29:20:elinks:INFO: Disabling clock on downlink 4
12:29:20:setup_element:INFO: Checking SOS, encoding_mode: SOS
12:29:20:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
12:29:20:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24
12:29:20:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25
12:29:20:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26
12:29:20:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27
12:29:20:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28
12:29:20:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29
12:29:20:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30
12:29:20:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31
12:29:20:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
12:29:20:elinks:INFO: Disabling clock on downlink 0
12:29:20:elinks:INFO: Disabling clock on downlink 1
12:29:20:elinks:INFO: Disabling clock on downlink 2
12:29:20:elinks:INFO: Disabling clock on downlink 3
12:29:20:elinks:INFO: Disabling clock on downlink 4
12:29:20:setup_element:INFO: Checking SOS, encoding_mode: SOS
12:29:20:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
12:29:20:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
12:29:20:elinks:INFO: Disabling clock on downlink 0
12:29:20:elinks:INFO: Disabling clock on downlink 1
12:29:20:elinks:INFO: Disabling clock on downlink 2
12:29:20:elinks:INFO: Disabling clock on downlink 3
12:29:20:elinks:INFO: Disabling clock on downlink 4
12:29:20:setup_element:INFO: Checking SOS, encoding_mode: SOS
12:29:20:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
12:29:21:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
12:29:21:setup_element:INFO: Scanning clock phase
12:29:21:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
12:29:21:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
12:29:21:setup_element:INFO: Clock phase scan results for group 0, downlink 2
12:29:21:setup_element:INFO: Eye window for uplink 24: ______________________________________________________________________XXXXXXXXX_
Clock Delay: 34
12:29:21:setup_element:INFO: Eye window for uplink 25: ______________________________________________________________________XXXXXXXXX_
Clock Delay: 34
12:29:21:setup_element:INFO: Eye window for uplink 26: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
12:29:21:setup_element:INFO: Eye window for uplink 27: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
12:29:21:setup_element:INFO: Eye window for uplink 28: _____________________________________________________________________XXXXXXX____
Clock Delay: 32
12:29:21:setup_element:INFO: Eye window for uplink 29: _____________________________________________________________________XXXXXXX____
Clock Delay: 32
12:29:21:setup_element:INFO: Eye window for uplink 30: ______________________________________________________________________XXXXXX____
Clock Delay: 32
12:29:21:setup_element:INFO: Eye window for uplink 31: ______________________________________________________________________XXXXXX____
Clock Delay: 32
12:29:21:setup_element:INFO: Setting the clock phase to 33 for group 0, downlink 2
12:29:21:setup_element:INFO: Scanning data phases
12:29:21:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
12:29:21:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
12:29:26:setup_element:INFO: Data phase scan results for group 0, downlink 2
12:29:26:setup_element:INFO: Eye window for uplink 24: _______XXXXX____________________________
Data delay found: 29
12:29:26:setup_element:INFO: Eye window for uplink 25: __________XXXXX_________________________
Data delay found: 32
12:29:26:setup_element:INFO: Eye window for uplink 26: __________XXXXX_________________________
Data delay found: 32
12:29:26:setup_element:INFO: Eye window for uplink 27: ______________XXXX______________________
Data delay found: 35
12:29:26:setup_element:INFO: Eye window for uplink 28: _________XXXXX__________________________
Data delay found: 31
12:29:26:setup_element:INFO: Eye window for uplink 29: __________XXXXXX________________________
Data delay found: 32
12:29:26:setup_element:INFO: Eye window for uplink 30: _____________XXXXXX_____________________
Data delay found: 35
12:29:26:setup_element:INFO: Eye window for uplink 31: ____________XXXXX_______________________
Data delay found: 34
12:29:26:setup_element:INFO: Setting the data phase to 29 for uplink 24
12:29:26:setup_element:INFO: Setting the data phase to 32 for uplink 25
12:29:26:setup_element:INFO: Setting the data phase to 32 for uplink 26
12:29:26:setup_element:INFO: Setting the data phase to 35 for uplink 27
12:29:26:setup_element:INFO: Setting the data phase to 31 for uplink 28
12:29:26:setup_element:INFO: Setting the data phase to 32 for uplink 29
12:29:26:setup_element:INFO: Setting the data phase to 35 for uplink 30
12:29:26:setup_element:INFO: Setting the data phase to 34 for uplink 31
12:29:26:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 2
Uplinks: [24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 33
Window Length: 70
Eye Windows:
Uplink 24: ______________________________________________________________________XXXXXXXXX_
Uplink 25: ______________________________________________________________________XXXXXXXXX_
Uplink 26: _______________________________________________________________________XXXXXXXX_
Uplink 27: _______________________________________________________________________XXXXXXXX_
Uplink 28: _____________________________________________________________________XXXXXXX____
Uplink 29: _____________________________________________________________________XXXXXXX____
Uplink 30: ______________________________________________________________________XXXXXX____
Uplink 31: ______________________________________________________________________XXXXXX____
Data phase characteristics:
Uplink 24:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 25:
Optimal Phase: 32
Window Length: 35
Eye Window: __________XXXXX_________________________
Uplink 26:
Optimal Phase: 32
Window Length: 35
Eye Window: __________XXXXX_________________________
Uplink 27:
Optimal Phase: 35
Window Length: 36
Eye Window: ______________XXXX______________________
Uplink 28:
Optimal Phase: 31
Window Length: 35
Eye Window: _________XXXXX__________________________
Uplink 29:
Optimal Phase: 32
Window Length: 34
Eye Window: __________XXXXXX________________________
Uplink 30:
Optimal Phase: 35
Window Length: 34
Eye Window: _____________XXXXXX_____________________
Uplink 31:
Optimal Phase: 34
Window Length: 35
Eye Window: ____________XXXXX_______________________
]
12:29:26:setup_element:INFO: Beginning SMX ASICs map scan
12:29:26:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
12:29:26:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
12:29:26:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
12:29:26:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
12:29:26:uplink:INFO: Setting uplinks mask [24, 25, 26, 27, 28, 29, 30, 31]
12:29:27:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 30
12:29:27:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 31
12:29:27:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28
12:29:27:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 29
12:29:27:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26
12:29:27:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 27
12:29:28:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 24
12:29:28:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 25
12:29:29:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 2
Uplinks: [24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map:
ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
Clock Phase Characteristic:
Optimal Phase: 33
Window Length: 70
Eye Windows:
Uplink 24: ______________________________________________________________________XXXXXXXXX_
Uplink 25: ______________________________________________________________________XXXXXXXXX_
Uplink 26: _______________________________________________________________________XXXXXXXX_
Uplink 27: _______________________________________________________________________XXXXXXXX_
Uplink 28: _____________________________________________________________________XXXXXXX____
Uplink 29: _____________________________________________________________________XXXXXXX____
Uplink 30: ______________________________________________________________________XXXXXX____
Uplink 31: ______________________________________________________________________XXXXXX____
Data phase characteristics:
Uplink 24:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 25:
Optimal Phase: 32
Window Length: 35
Eye Window: __________XXXXX_________________________
Uplink 26:
Optimal Phase: 32
Window Length: 35
Eye Window: __________XXXXX_________________________
Uplink 27:
Optimal Phase: 35
Window Length: 36
Eye Window: ______________XXXX______________________
Uplink 28:
Optimal Phase: 31
Window Length: 35
Eye Window: _________XXXXX__________________________
Uplink 29:
Optimal Phase: 32
Window Length: 34
Eye Window: __________XXXXXX________________________
Uplink 30:
Optimal Phase: 35
Window Length: 34
Eye Window: _____________XXXXXX_____________________
Uplink 31:
Optimal Phase: 34
Window Length: 35
Eye Window: ____________XXXXX_______________________
12:29:29:setup_element:INFO: Performing Elink synchronization
12:29:29:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
12:29:29:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
12:29:29:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
12:29:29:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
12:29:29:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2
12:29:29:uplink:INFO: Enabling uplinks [24, 25, 26, 27, 28, 29, 30, 31]
12:29:29:ST3_emu:INFO: Number of chips: 4
addr | upli | dwnli | grp | uplinks | uplinks_map
1 | [0] | 2 | 0 | [30] | [(0, 30), (1, 31)]
3 | [0] | 2 | 0 | [28] | [(0, 28), (1, 29)]
5 | [0] | 2 | 0 | [26] | [(0, 26), (1, 27)]
7 | [0] | 2 | 0 | [24] | [(0, 24), (1, 25)]
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_h_1_30 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_h_1_30 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_h_1_30 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_h_1_30 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_h_1_30 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_h_1_30 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_e_1_30 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_e_1_30 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_e_1_30 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_e_1_30 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_e_1_30 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_e_1_30 (Potential memory leak).
TCanvas::Constructor:0: RuntimeWarning: Deleting canvas with same name: cDist_FEB_B__addr_1__upli_30
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_h_3_28 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_h_3_28 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_h_3_28 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_h_3_28 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_h_3_28 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_h_3_28 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_e_3_28 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_e_3_28 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_e_3_28 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_e_3_28 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_e_3_28 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_e_3_28 (Potential memory leak).
TCanvas::Constructor:0: RuntimeWarning: Deleting canvas with same name: cDist_FEB_B__addr_3__upli_28
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_h_5_26 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_h_5_26 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_h_5_26 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_h_5_26 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_h_5_26 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_h_5_26 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_e_5_26 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_e_5_26 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_e_5_26 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_e_5_26 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_e_5_26 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_e_5_26 (Potential memory leak).
TCanvas::Constructor:0: RuntimeWarning: Deleting canvas with same name: cDist_FEB_B__addr_5__upli_26
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_h_7_24 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_h_7_24 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_h_7_24 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_h_7_24 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_h_7_24 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_h_7_24 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_e_7_24 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_e_7_24 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_e_7_24 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_e_7_24 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_e_7_24 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_e_7_24 (Potential memory leak).
TCanvas::Constructor:0: RuntimeWarning: Deleting canvas with same name: cDist_FEB_B__addr_7__upli_24
12:29:30:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
12:29:31:febtest:INFO: 30-1 | XA-000-08-002-000-005-074-00 | 18.7 | 1230.3
12:29:31:febtest:INFO: 28-3 | XA-000-08-002-000-000-150-03 | 40.9 | 1165.6
12:29:31:febtest:INFO: 26-5 | XA-000-08-002-002-008-047-05 | 28.2 | 1195.1
12:29:31:febtest:INFO: 24-7 | XA-000-08-002-002-008-043-05 | 21.9 | 1212.7
12:29:31:ST3_smx:INFO: Configuring SMX FAST
12:29:33:ST3_smx:INFO: chip: 30-1 28.225000 C 1195.082160 mV
12:29:33:ST3_smx:INFO: Electrons
12:29:33:ST3_smx:INFO: # loops 0
12:29:35:ST3_smx:INFO: # loops 1
12:29:37:ST3_smx:INFO: # loops 2
12:29:39:ST3_smx:INFO: # loops 3
12:29:40:ST3_smx:INFO: # loops 4
12:29:42:ST3_smx:INFO: Total # of broken channels: 0
12:29:42:ST3_smx:INFO: List of broken channels: []
12:29:42:ST3_smx:INFO: Total # of broken channels: 0
12:29:42:ST3_smx:INFO: List of broken channels: []
12:29:43:ST3_smx:INFO: Configuring SMX FAST
12:29:45:ST3_smx:INFO: chip: 28-3 44.073563 C 1159.654860 mV
12:29:45:ST3_smx:INFO: Electrons
12:29:45:ST3_smx:INFO: # loops 0
12:29:46:ST3_smx:INFO: # loops 1
12:29:48:ST3_smx:INFO: # loops 2
12:29:49:ST3_smx:INFO: # loops 3
12:29:51:ST3_smx:INFO: # loops 4
12:29:52:ST3_smx:INFO: Total # of broken channels: 0
12:29:52:ST3_smx:INFO: List of broken channels: []
12:29:52:ST3_smx:INFO: Total # of broken channels: 0
12:29:52:ST3_smx:INFO: List of broken channels: []
12:29:53:ST3_smx:INFO: Configuring SMX FAST
12:29:55:ST3_smx:INFO: chip: 26-5 28.225000 C 1189.190035 mV
12:29:55:ST3_smx:INFO: Electrons
12:29:55:ST3_smx:INFO: # loops 0
12:29:57:ST3_smx:INFO: # loops 1
12:29:58:ST3_smx:INFO: # loops 2
12:30:00:ST3_smx:INFO: # loops 3
12:30:01:ST3_smx:INFO: # loops 4
12:30:03:ST3_smx:INFO: Total # of broken channels: 0
12:30:03:ST3_smx:INFO: List of broken channels: []
12:30:03:ST3_smx:INFO: Total # of broken channels: 0
12:30:03:ST3_smx:INFO: List of broken channels: []
12:30:04:ST3_smx:INFO: Configuring SMX FAST
12:30:06:ST3_smx:INFO: chip: 24-7 31.389742 C 1195.082160 mV
12:30:06:ST3_smx:INFO: Electrons
12:30:06:ST3_smx:INFO: # loops 0
12:30:08:ST3_smx:INFO: # loops 1
12:30:09:ST3_smx:INFO: # loops 2
12:30:11:ST3_smx:INFO: # loops 3
12:30:12:ST3_smx:INFO: # loops 4
12:30:14:ST3_smx:INFO: Total # of broken channels: 0
12:30:14:ST3_smx:INFO: List of broken channels: []
12:30:14:ST3_smx:INFO: Total # of broken channels: 0
12:30:14:ST3_smx:INFO: List of broken channels: []
12:30:15:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
12:30:15:febtest:INFO: 30-1 | XA-000-08-002-000-005-074-00 | 28.2 | 1195.1
12:30:15:febtest:INFO: 28-3 | XA-000-08-002-000-000-150-03 | 40.9 | 1159.7
12:30:16:febtest:INFO: 26-5 | XA-000-08-002-002-008-047-05 | 28.2 | 1195.1
12:30:16:febtest:INFO: 24-7 | XA-000-08-002-002-008-043-05 | 31.4 | 1195.1
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-Microcable
TEST_DATE : 2024_02_05-12_29_16
OPERATOR : Robert V.;
SITE : GSI
SETUP : GSI_TEST_SETUP_1
Set-ID :
---------------------------------------
MODULE_NAME : L4DL200116 M4DL2T1001161A2 42 A
FEB_SN : 2096
FEB_TYPE : 8.2
FEB_UPLINKS : 2
FEB_A : 1
FEB_B : 0
---------------------------------------
---------------------------------------
VI_before_Init : ['2.451', '0.9245', '1.850', '1.2050', '2.450', '0.0002', '1.850', '0.0001']
VI_after__Init : ['2.450', '0.0003', '1.850', '0.0000', '2.450', '1.9900', '1.850', '0.3206']
VI_at__the_End : ['0', '0', '0', '0', '0', '0']
12:30:43:ST3_Shared:INFO: /home/cbm/public_html/Production_LogDir//FEB/FEB_2096/TestDate_2024_02_05-12_29_16/