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FEB_2097 31.01.24 15:08:40
Info
15:08:20:ST3_hmp4040:INFO: ROHDE&SCHWARZ,HMP4040,123796,HW50020003/SW2.71
15:08:21:febtest:INFO: FEB 8-2 selected
15:08:21:smx_tester:INFO: Setting Elink clock mode to 160 MHz
15:08:27:febtest:INFO: FEB 8-2 selected
15:08:27:smx_tester:INFO: Setting Elink clock mode to 160 MHz
15:08:33:febtest:INFO: FEB 8-2 selected
15:08:33:smx_tester:INFO: Setting Elink clock mode to 160 MHz
15:08:36:ST3_Shared:INFO: Listo of operators:Robert V.;
15:08:37:ST3_Shared:INFO: Listo of operators:Robert V.; Irakli K.;
15:08:40:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
15:08:40:ST3_Shared:INFO: -----------------------FEB-Microcable-----------------------
15:08:40:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
15:08:41:febtest:INFO: Testing FEB with SN 2097
15:08:43:smx_tester:INFO: Scanning setup
15:08:43:elinks:INFO: Disabling clock on downlink 0
15:08:43:elinks:INFO: Disabling clock on downlink 1
15:08:43:elinks:INFO: Disabling clock on downlink 2
15:08:43:elinks:INFO: Disabling clock on downlink 3
15:08:43:elinks:INFO: Disabling clock on downlink 4
15:08:43:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:08:43:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
15:08:43:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:08:43:elinks:INFO: Disabling clock on downlink 0
15:08:43:elinks:INFO: Disabling clock on downlink 1
15:08:43:elinks:INFO: Disabling clock on downlink 2
15:08:43:elinks:INFO: Disabling clock on downlink 3
15:08:43:elinks:INFO: Disabling clock on downlink 4
15:08:43:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:08:43:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
15:08:43:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:08:43:elinks:INFO: Disabling clock on downlink 0
15:08:43:elinks:INFO: Disabling clock on downlink 1
15:08:43:elinks:INFO: Disabling clock on downlink 2
15:08:43:elinks:INFO: Disabling clock on downlink 3
15:08:43:elinks:INFO: Disabling clock on downlink 4
15:08:43:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:08:43:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:08:43:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24
15:08:43:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25
15:08:43:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26
15:08:43:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27
15:08:43:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28
15:08:43:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29
15:08:43:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30
15:08:43:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31
15:08:43:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:08:43:elinks:INFO: Disabling clock on downlink 0
15:08:43:elinks:INFO: Disabling clock on downlink 1
15:08:43:elinks:INFO: Disabling clock on downlink 2
15:08:43:elinks:INFO: Disabling clock on downlink 3
15:08:43:elinks:INFO: Disabling clock on downlink 4
15:08:43:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:08:43:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
15:08:43:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:08:43:elinks:INFO: Disabling clock on downlink 0
15:08:43:elinks:INFO: Disabling clock on downlink 1
15:08:43:elinks:INFO: Disabling clock on downlink 2
15:08:43:elinks:INFO: Disabling clock on downlink 3
15:08:43:elinks:INFO: Disabling clock on downlink 4
15:08:43:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:08:43:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
15:08:43:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:08:43:setup_element:INFO: Scanning clock phase
15:08:43:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:08:44:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
15:08:44:setup_element:INFO: Clock phase scan results for group 0, downlink 2
15:08:44:setup_element:INFO: Eye window for uplink 24: ____________________________________________________________________XXXXXXXXX___
Clock Delay: 32
15:08:44:setup_element:INFO: Eye window for uplink 25: ____________________________________________________________________XXXXXXXXX___
Clock Delay: 32
15:08:44:setup_element:INFO: Eye window for uplink 26: ______________________________________________________________________XXXXXXX___
Clock Delay: 33
15:08:44:setup_element:INFO: Eye window for uplink 27: ______________________________________________________________________XXXXXXX___
Clock Delay: 33
15:08:44:setup_element:INFO: Eye window for uplink 28: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
15:08:44:setup_element:INFO: Eye window for uplink 29: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
15:08:44:setup_element:INFO: Eye window for uplink 30: _____________________________________________________________________XXXXXXX____
Clock Delay: 32
15:08:44:setup_element:INFO: Eye window for uplink 31: _____________________________________________________________________XXXXXXX____
Clock Delay: 32
15:08:44:setup_element:INFO: Setting the clock phase to 32 for group 0, downlink 2
15:08:44:setup_element:INFO: Scanning data phases
15:08:44:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:08:44:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
15:08:49:setup_element:INFO: Data phase scan results for group 0, downlink 2
15:08:49:setup_element:INFO: Eye window for uplink 24: _____XXXXX______________________________
Data delay found: 27
15:08:49:setup_element:INFO: Eye window for uplink 25: ________XXXXX___________________________
Data delay found: 30
15:08:49:setup_element:INFO: Eye window for uplink 26: ______XXXXX_____________________________
Data delay found: 28
15:08:49:setup_element:INFO: Eye window for uplink 27: _________XXXXXX_________________________
Data delay found: 31
15:08:49:setup_element:INFO: Eye window for uplink 28: _____________XXXXX______________________
Data delay found: 35
15:08:49:setup_element:INFO: Eye window for uplink 29: ______________XXXXXX____________________
Data delay found: 36
15:08:49:setup_element:INFO: Eye window for uplink 30: _____________XXXXXX_____________________
Data delay found: 35
15:08:49:setup_element:INFO: Eye window for uplink 31: ____________XXXX________________________
Data delay found: 33
15:08:49:setup_element:INFO: Setting the data phase to 27 for uplink 24
15:08:49:setup_element:INFO: Setting the data phase to 30 for uplink 25
15:08:49:setup_element:INFO: Setting the data phase to 28 for uplink 26
15:08:49:setup_element:INFO: Setting the data phase to 31 for uplink 27
15:08:49:setup_element:INFO: Setting the data phase to 35 for uplink 28
15:08:49:setup_element:INFO: Setting the data phase to 36 for uplink 29
15:08:49:setup_element:INFO: Setting the data phase to 35 for uplink 30
15:08:49:setup_element:INFO: Setting the data phase to 33 for uplink 31
15:08:49:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 2
Uplinks: [24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 32
Window Length: 70
Eye Windows:
Uplink 24: ____________________________________________________________________XXXXXXXXX___
Uplink 25: ____________________________________________________________________XXXXXXXXX___
Uplink 26: ______________________________________________________________________XXXXXXX___
Uplink 27: ______________________________________________________________________XXXXXXX___
Uplink 28: ______________________________________________________________________XXXXXXXX__
Uplink 29: ______________________________________________________________________XXXXXXXX__
Uplink 30: _____________________________________________________________________XXXXXXX____
Uplink 31: _____________________________________________________________________XXXXXXX____
Data phase characteristics:
Uplink 24:
Optimal Phase: 27
Window Length: 35
Eye Window: _____XXXXX______________________________
Uplink 25:
Optimal Phase: 30
Window Length: 35
Eye Window: ________XXXXX___________________________
Uplink 26:
Optimal Phase: 28
Window Length: 35
Eye Window: ______XXXXX_____________________________
Uplink 27:
Optimal Phase: 31
Window Length: 34
Eye Window: _________XXXXXX_________________________
Uplink 28:
Optimal Phase: 35
Window Length: 35
Eye Window: _____________XXXXX______________________
Uplink 29:
Optimal Phase: 36
Window Length: 34
Eye Window: ______________XXXXXX____________________
Uplink 30:
Optimal Phase: 35
Window Length: 34
Eye Window: _____________XXXXXX_____________________
Uplink 31:
Optimal Phase: 33
Window Length: 36
Eye Window: ____________XXXX________________________
]
15:08:49:setup_element:INFO: Beginning SMX ASICs map scan
15:08:49:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:08:49:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
15:08:49:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
15:08:49:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
15:08:49:uplink:INFO: Setting uplinks mask [24, 25, 26, 27, 28, 29, 30, 31]
15:08:49:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 30
15:08:49:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 31
15:08:50:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28
15:08:50:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 29
15:08:50:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26
15:08:50:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 27
15:08:50:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 24
15:08:50:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 25
15:08:52:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 2
Uplinks: [24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map:
ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
Clock Phase Characteristic:
Optimal Phase: 32
Window Length: 70
Eye Windows:
Uplink 24: ____________________________________________________________________XXXXXXXXX___
Uplink 25: ____________________________________________________________________XXXXXXXXX___
Uplink 26: ______________________________________________________________________XXXXXXX___
Uplink 27: ______________________________________________________________________XXXXXXX___
Uplink 28: ______________________________________________________________________XXXXXXXX__
Uplink 29: ______________________________________________________________________XXXXXXXX__
Uplink 30: _____________________________________________________________________XXXXXXX____
Uplink 31: _____________________________________________________________________XXXXXXX____
Data phase characteristics:
Uplink 24:
Optimal Phase: 27
Window Length: 35
Eye Window: _____XXXXX______________________________
Uplink 25:
Optimal Phase: 30
Window Length: 35
Eye Window: ________XXXXX___________________________
Uplink 26:
Optimal Phase: 28
Window Length: 35
Eye Window: ______XXXXX_____________________________
Uplink 27:
Optimal Phase: 31
Window Length: 34
Eye Window: _________XXXXXX_________________________
Uplink 28:
Optimal Phase: 35
Window Length: 35
Eye Window: _____________XXXXX______________________
Uplink 29:
Optimal Phase: 36
Window Length: 34
Eye Window: ______________XXXXXX____________________
Uplink 30:
Optimal Phase: 35
Window Length: 34
Eye Window: _____________XXXXXX_____________________
Uplink 31:
Optimal Phase: 33
Window Length: 36
Eye Window: ____________XXXX________________________
15:08:52:setup_element:INFO: Performing Elink synchronization
15:08:52:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:08:52:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
15:08:52:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
15:08:52:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
15:08:52:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2
15:08:52:uplink:INFO: Enabling uplinks [24, 25, 26, 27, 28, 29, 30, 31]
15:08:52:ST3_emu:INFO: Number of chips: 4
addr | upli | dwnli | grp | uplinks | uplinks_map
1 | [0] | 2 | 0 | [30] | [(0, 30), (1, 31)]
3 | [0] | 2 | 0 | [28] | [(0, 28), (1, 29)]
5 | [0] | 2 | 0 | [26] | [(0, 26), (1, 27)]
7 | [0] | 2 | 0 | [24] | [(0, 24), (1, 25)]
15:08:53:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:08:53:febtest:INFO: 30-1 | XA-000-08-002-000-003-244-06 | 44.1 | 1159.7
15:08:54:febtest:INFO: 28-3 | XA-000-08-002-000-003-246-06 | 50.4 | 1141.9
15:08:54:febtest:INFO: 26-5 | XA-000-08-002-000-003-245-06 | 31.4 | 1212.7
15:08:54:febtest:INFO: 24-7 | XA-000-08-002-000-003-242-06 | 47.3 | 1165.6
15:08:54:ST3_smx:INFO: Configuring SMX FAST
15:08:56:ST3_smx:INFO: chip: 30-1 53.612520 C 1135.937260 mV
15:08:56:ST3_smx:INFO: Electrons
15:08:56:ST3_smx:INFO: # loops 0
15:08:58:ST3_smx:INFO: # loops 1
15:08:59:ST3_smx:INFO: # loops 2
15:09:01:ST3_smx:INFO: # loops 3
15:09:03:ST3_smx:INFO: # loops 4
15:09:04:ST3_smx:INFO: Total # of broken channels: 0
15:09:04:ST3_smx:INFO: List of broken channels: []
15:09:04:ST3_smx:INFO: Total # of broken channels: 0
15:09:04:ST3_smx:INFO: List of broken channels: []
15:09:06:ST3_smx:INFO: Configuring SMX FAST
15:09:08:ST3_smx:INFO: chip: 28-3 44.073563 C 1165.571835 mV
15:09:08:ST3_smx:INFO: Electrons
15:09:08:ST3_smx:INFO: # loops 0
15:09:09:ST3_smx:INFO: # loops 1
15:09:11:ST3_smx:INFO: # loops 2
15:09:12:ST3_smx:INFO: # loops 3
15:09:14:ST3_smx:INFO: # loops 4
15:09:16:ST3_smx:INFO: Total # of broken channels: 0
15:09:16:ST3_smx:INFO: List of broken channels: []
15:09:16:ST3_smx:INFO: Total # of broken channels: 0
15:09:16:ST3_smx:INFO: List of broken channels: []
15:09:17:ST3_smx:INFO: Configuring SMX FAST
15:09:19:ST3_smx:INFO: chip: 26-5 34.556970 C 1212.728715 mV
15:09:19:ST3_smx:INFO: Electrons
15:09:19:ST3_smx:INFO: # loops 0
15:09:20:ST3_smx:INFO: # loops 1
15:09:22:ST3_smx:INFO: # loops 2
15:09:24:ST3_smx:INFO: # loops 3
15:09:25:ST3_smx:INFO: # loops 4
15:09:27:ST3_smx:INFO: Total # of broken channels: 0
15:09:27:ST3_smx:INFO: List of broken channels: []
15:09:27:ST3_smx:INFO: Total # of broken channels: 0
15:09:27:ST3_smx:INFO: List of broken channels: []
15:09:28:ST3_smx:INFO: Configuring SMX FAST
15:09:30:ST3_smx:INFO: chip: 24-7 40.898880 C 1183.292940 mV
15:09:30:ST3_smx:INFO: Electrons
15:09:30:ST3_smx:INFO: # loops 0
15:09:31:ST3_smx:INFO: # loops 1
15:09:33:ST3_smx:INFO: # loops 2
15:09:35:ST3_smx:INFO: # loops 3
15:09:36:ST3_smx:INFO: # loops 4
15:09:38:ST3_smx:INFO: Total # of broken channels: 0
15:09:38:ST3_smx:INFO: List of broken channels: []
15:09:38:ST3_smx:INFO: Total # of broken channels: 0
15:09:38:ST3_smx:INFO: List of broken channels: []
15:09:39:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:09:39:febtest:INFO: 30-1 | XA-000-08-002-000-003-244-06 | 53.6 | 1135.9
15:09:39:febtest:INFO: 28-3 | XA-000-08-002-000-003-246-06 | 44.1 | 1165.6
15:09:40:febtest:INFO: 26-5 | XA-000-08-002-000-003-245-06 | 34.6 | 1212.7
15:09:40:febtest:INFO: 24-7 | XA-000-08-002-000-003-242-06 | 40.9 | 1183.3
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-Microcable
TEST_DATE : 2024_01_31-15_08_40
OPERATOR : Robert V.; Irakli K.;
SITE : GSI
SETUP : GSI_TEST_SETUP_1
Set-ID :
---------------------------------------
MODULE_NAME :
FEB_SN : 2097
FEB_TYPE : 8.2
FEB_UPLINKS : 2
FEB_A : 1
FEB_B : 0
---------------------------------------
---------------------------------------
VI_before_Init : ['2.450', '1.0220', '1.850', '0.9894', '2.450', '0.0002', '1.851', '0.0001']
VI_after__Init : ['0', '0', '0', '0', '0', '0']
VI_at__the_End : ['0', '0', '0', '0', '0', '0']
15:09:45:ST3_Shared:INFO: /home/cbm/public_html/Production_LogDir//FEB/FEB_2097/TestDate_2024_01_31-15_08_40/