14:54:36:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:54:36:ST3_Shared:INFO:	                          FEB-ASIC                          
14:54:36:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:54:37:febtest:INFO:	Testing FEB with SN 2125
14:54:39:smx_tester:INFO:	Scanning setup
14:54:39:elinks:INFO:	Disabling clock on downlink 0
14:54:39:elinks:INFO:	Disabling clock on downlink 1
14:54:40:elinks:INFO:	Disabling clock on downlink 2
14:54:40:elinks:INFO:	Disabling clock on downlink 3
14:54:40:elinks:INFO:	Disabling clock on downlink 4
14:54:40:setup_element:INFO:	Checking SOS, encoding_mode: SOS
14:54:40:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
14:54:40:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
14:54:40:elinks:INFO:	Disabling clock on downlink 0
14:54:40:elinks:INFO:	Disabling clock on downlink 1
14:54:40:elinks:INFO:	Disabling clock on downlink 2
14:54:40:elinks:INFO:	Disabling clock on downlink 3
14:54:40:elinks:INFO:	Disabling clock on downlink 4
14:54:40:setup_element:INFO:	Checking SOS, encoding_mode: SOS
14:54:40:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
14:54:40:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
14:54:40:elinks:INFO:	Disabling clock on downlink 0
14:54:40:elinks:INFO:	Disabling clock on downlink 1
14:54:40:elinks:INFO:	Disabling clock on downlink 2
14:54:40:elinks:INFO:	Disabling clock on downlink 3
14:54:40:elinks:INFO:	Disabling clock on downlink 4
14:54:40:setup_element:INFO:	Checking SOS, encoding_mode: SOS
14:54:40:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
14:54:40:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 16
14:54:40:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 17
14:54:40:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 18
14:54:40:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 19
14:54:40:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 20
14:54:40:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 21
14:54:40:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 24
14:54:40:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 25
14:54:40:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 26
14:54:40:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 27
14:54:40:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 28
14:54:40:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 29
14:54:40:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 30
14:54:40:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 31
14:54:40:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
14:54:40:elinks:INFO:	Disabling clock on downlink 0
14:54:40:elinks:INFO:	Disabling clock on downlink 1
14:54:40:elinks:INFO:	Disabling clock on downlink 2
14:54:40:elinks:INFO:	Disabling clock on downlink 3
14:54:40:elinks:INFO:	Disabling clock on downlink 4
14:54:40:setup_element:INFO:	Checking SOS, encoding_mode: SOS
14:54:40:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
14:54:40:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
14:54:40:elinks:INFO:	Disabling clock on downlink 0
14:54:40:elinks:INFO:	Disabling clock on downlink 1
14:54:40:elinks:INFO:	Disabling clock on downlink 2
14:54:40:elinks:INFO:	Disabling clock on downlink 3
14:54:40:elinks:INFO:	Disabling clock on downlink 4
14:54:40:setup_element:INFO:	Checking SOS, encoding_mode: SOS
14:54:40:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [4]
14:54:40:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
14:54:40:setup_element:INFO:	Scanning clock phase
14:54:40:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
14:54:40:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
14:54:41:setup_element:INFO:	Clock phase scan results for group 0, downlink 2
14:54:41:setup_element:INFO:	Eye window for uplink 16: ____________________________________________________________________XXXXXXX_____
Clock Delay: 31
14:54:41:setup_element:INFO:	Eye window for uplink 17: ____________________________________________________________________XXXXXXX_____
Clock Delay: 31
14:54:41:setup_element:INFO:	Eye window for uplink 18: ____________________________________________________________________XXXXXXXXX___
Clock Delay: 32
14:54:41:setup_element:INFO:	Eye window for uplink 19: ____________________________________________________________________XXXXXXXXX___
Clock Delay: 32
14:54:41:setup_element:INFO:	Eye window for uplink 20: ___________________________________________________________________XXXXXXXXX____
Clock Delay: 31
14:54:41:setup_element:INFO:	Eye window for uplink 21: ___________________________________________________________________XXXXXXXXX____
Clock Delay: 31
14:54:41:setup_element:INFO:	Eye window for uplink 24: ___________________________________________________________________XXXXXXX______
Clock Delay: 30
14:54:41:setup_element:INFO:	Eye window for uplink 25: ___________________________________________________________________XXXXXXX______
Clock Delay: 30
14:54:41:setup_element:INFO:	Eye window for uplink 26: ________________________________________________________________________________
Clock Delay: 40
14:54:41:setup_element:INFO:	Eye window for uplink 27: ________________________________________________________________________________
Clock Delay: 40
14:54:41:setup_element:INFO:	Eye window for uplink 28: ________________________________________________________________________________
Clock Delay: 40
14:54:41:setup_element:INFO:	Eye window for uplink 29: ________________________________________________________________________________
Clock Delay: 40
14:54:41:setup_element:INFO:	Eye window for uplink 30: ________________________________________________________________________________
Clock Delay: 40
14:54:41:setup_element:INFO:	Eye window for uplink 31: ________________________________________________________________________________
Clock Delay: 40
14:54:41:setup_element:INFO:	Setting the clock phase to 31 for group 0, downlink 2
14:54:41:setup_element:INFO:	Scanning data phases
14:54:41:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
14:54:41:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
14:54:46:setup_element:INFO:	Data phase scan results for group 0, downlink 2
14:54:46:setup_element:INFO:	Eye window for uplink 16: XX__________________________________XXXX
Data delay found: 18
14:54:46:setup_element:INFO:	Eye window for uplink 17: __________________________________XXXXX_
Data delay found: 16
14:54:46:setup_element:INFO:	Eye window for uplink 18: XX__________________________________XXXX
Data delay found: 18
14:54:46:setup_element:INFO:	Eye window for uplink 19: X_________________________________XXXXX_
Data delay found: 17
14:54:46:setup_element:INFO:	Eye window for uplink 20: ___________________________________XXXXX
Data delay found: 17
14:54:46:setup_element:INFO:	Eye window for uplink 21: __________________________________XXXXX_
Data delay found: 16
14:54:46:setup_element:INFO:	Eye window for uplink 24: _______XXXXX____________________________
Data delay found: 29
14:54:46:setup_element:INFO:	Eye window for uplink 25: _________XXXXX__________________________
Data delay found: 31
14:54:46:setup_element:INFO:	Eye window for uplink 26: ________XXXXX___________________________
Data delay found: 30
14:54:46:setup_element:INFO:	Eye window for uplink 27: ___________XXXXXX_______________________
Data delay found: 33
14:54:46:setup_element:INFO:	Eye window for uplink 28: _____________XXXXX______________________
Data delay found: 35
14:54:46:setup_element:INFO:	Eye window for uplink 29: _______________XXXXXX___________________
Data delay found: 37
14:54:46:setup_element:INFO:	Eye window for uplink 30: ________________XXXXXX__________________
Data delay found: 38
14:54:46:setup_element:INFO:	Eye window for uplink 31: _______________XXXXXXXX_________________
Data delay found: 38
14:54:46:setup_element:INFO:	Setting the data phase to 18 for uplink 16
14:54:46:setup_element:INFO:	Setting the data phase to 16 for uplink 17
14:54:46:setup_element:INFO:	Setting the data phase to 18 for uplink 18
14:54:46:setup_element:INFO:	Setting the data phase to 17 for uplink 19
14:54:46:setup_element:INFO:	Setting the data phase to 17 for uplink 20
14:54:46:setup_element:INFO:	Setting the data phase to 16 for uplink 21
14:54:46:setup_element:INFO:	Setting the data phase to 29 for uplink 24
14:54:46:setup_element:INFO:	Setting the data phase to 31 for uplink 25
14:54:46:setup_element:INFO:	Setting the data phase to 30 for uplink 26
14:54:46:setup_element:INFO:	Setting the data phase to 33 for uplink 27
14:54:46:setup_element:INFO:	Setting the data phase to 35 for uplink 28
14:54:46:setup_element:INFO:	Setting the data phase to 37 for uplink 29
14:54:46:setup_element:INFO:	Setting the data phase to 38 for uplink 30
14:54:46:setup_element:INFO:	Setting the data phase to 38 for uplink 31
14:54:46:ST3_emu:ERROR:	[
Setup Element:
  Group: 0
  Downlink: 2
  Uplinks: [16, 17, 18, 19, 20, 21, 24, 25, 26, 27, 28, 29, 30, 31]
  ASICs Map: None
  Clock Phase Characteristic:
    Optimal Phase: 31
    Window Length: 70
    Eye Windows:
      Uplink 16: ____________________________________________________________________XXXXXXX_____
      Uplink 17: ____________________________________________________________________XXXXXXX_____
      Uplink 18: ____________________________________________________________________XXXXXXXXX___
      Uplink 19: ____________________________________________________________________XXXXXXXXX___
      Uplink 20: ___________________________________________________________________XXXXXXXXX____
      Uplink 21: ___________________________________________________________________XXXXXXXXX____
      Uplink 24: ___________________________________________________________________XXXXXXX______
      Uplink 25: ___________________________________________________________________XXXXXXX______
      Uplink 26: ________________________________________________________________________________
      Uplink 27: ________________________________________________________________________________
      Uplink 28: ________________________________________________________________________________
      Uplink 29: ________________________________________________________________________________
      Uplink 30: ________________________________________________________________________________
      Uplink 31: ________________________________________________________________________________
  Data phase characteristics:
    Uplink 16:
      Optimal Phase: 18
      Window Length: 34
      Eye Window: XX__________________________________XXXX
    Uplink 17:
      Optimal Phase: 16
      Window Length: 35
      Eye Window: __________________________________XXXXX_
    Uplink 18:
      Optimal Phase: 18
      Window Length: 34
      Eye Window: XX__________________________________XXXX
    Uplink 19:
      Optimal Phase: 17
      Window Length: 33
      Eye Window: X_________________________________XXXXX_
    Uplink 20:
      Optimal Phase: 17
      Window Length: 35
      Eye Window: ___________________________________XXXXX
    Uplink 21:
      Optimal Phase: 16
      Window Length: 35
      Eye Window: __________________________________XXXXX_
    Uplink 24:
      Optimal Phase: 29
      Window Length: 35
      Eye Window: _______XXXXX____________________________
    Uplink 25:
      Optimal Phase: 31
      Window Length: 35
      Eye Window: _________XXXXX__________________________
    Uplink 26:
      Optimal Phase: 30
      Window Length: 35
      Eye Window: ________XXXXX___________________________
    Uplink 27:
      Optimal Phase: 33
      Window Length: 34
      Eye Window: ___________XXXXXX_______________________
    Uplink 28:
      Optimal Phase: 35
      Window Length: 35
      Eye Window: _____________XXXXX______________________
    Uplink 29:
      Optimal Phase: 37
      Window Length: 34
      Eye Window: _______________XXXXXX___________________
    Uplink 30:
      Optimal Phase: 38
      Window Length: 34
      Eye Window: ________________XXXXXX__________________
    Uplink 31:
      Optimal Phase: 38
      Window Length: 32
      Eye Window: _______________XXXXXXXX_________________
]
14:54:46:setup_element:INFO:	Beginning SMX ASICs map scan
14:54:46:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
14:54:46:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
14:54:46:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
14:54:46:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
14:54:46:uplink:INFO:	Setting uplinks mask [16, 17, 18, 19, 20, 21, 24, 25, 26, 27, 28, 29, 30, 31]
14:54:47:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 0, uplink 30
14:54:47:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 1, uplink 31
14:54:47:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 0, uplink 21
14:54:47:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 1, uplink 20
14:54:47:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 0, uplink 28
14:54:47:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 1, uplink 29
14:54:47:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 0, uplink 19
14:54:47:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 1, uplink 18
14:54:47:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 0, uplink 26
14:54:47:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 1, uplink 27
14:54:48:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 0, uplink 17
14:54:48:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 1, uplink 16
14:54:48:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 0, uplink 24
14:54:48:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 1, uplink 25
14:54:49:ST3_emu:ERROR:	
Setup Element:
  Group: 0
  Downlink: 2
  Uplinks: [16, 17, 18, 19, 20, 21, 24, 25, 26, 27, 28, 29, 30, 31]
  ASICs Map:
    ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
    ASIC address 0x2: (ASIC uplink, uplink): (0, 21), (1, 20)
    ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
    ASIC address 0x4: (ASIC uplink, uplink): (0, 19), (1, 18)
    ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
    ASIC address 0x6: (ASIC uplink, uplink): (0, 17), (1, 16)
    ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
  Clock Phase Characteristic:
    Optimal Phase: 31
    Window Length: 70
    Eye Windows:
      Uplink 16: ____________________________________________________________________XXXXXXX_____
      Uplink 17: ____________________________________________________________________XXXXXXX_____
      Uplink 18: ____________________________________________________________________XXXXXXXXX___
      Uplink 19: ____________________________________________________________________XXXXXXXXX___
      Uplink 20: ___________________________________________________________________XXXXXXXXX____
      Uplink 21: ___________________________________________________________________XXXXXXXXX____
      Uplink 24: ___________________________________________________________________XXXXXXX______
      Uplink 25: ___________________________________________________________________XXXXXXX______
      Uplink 26: ________________________________________________________________________________
      Uplink 27: ________________________________________________________________________________
      Uplink 28: ________________________________________________________________________________
      Uplink 29: ________________________________________________________________________________
      Uplink 30: ________________________________________________________________________________
      Uplink 31: ________________________________________________________________________________
  Data phase characteristics:
    Uplink 16:
      Optimal Phase: 18
      Window Length: 34
      Eye Window: XX__________________________________XXXX
    Uplink 17:
      Optimal Phase: 16
      Window Length: 35
      Eye Window: __________________________________XXXXX_
    Uplink 18:
      Optimal Phase: 18
      Window Length: 34
      Eye Window: XX__________________________________XXXX
    Uplink 19:
      Optimal Phase: 17
      Window Length: 33
      Eye Window: X_________________________________XXXXX_
    Uplink 20:
      Optimal Phase: 17
      Window Length: 35
      Eye Window: ___________________________________XXXXX
    Uplink 21:
      Optimal Phase: 16
      Window Length: 35
      Eye Window: __________________________________XXXXX_
    Uplink 24:
      Optimal Phase: 29
      Window Length: 35
      Eye Window: _______XXXXX____________________________
    Uplink 25:
      Optimal Phase: 31
      Window Length: 35
      Eye Window: _________XXXXX__________________________
    Uplink 26:
      Optimal Phase: 30
      Window Length: 35
      Eye Window: ________XXXXX___________________________
    Uplink 27:
      Optimal Phase: 33
      Window Length: 34
      Eye Window: ___________XXXXXX_______________________
    Uplink 28:
      Optimal Phase: 35
      Window Length: 35
      Eye Window: _____________XXXXX______________________
    Uplink 29:
      Optimal Phase: 37
      Window Length: 34
      Eye Window: _______________XXXXXX___________________
    Uplink 30:
      Optimal Phase: 38
      Window Length: 34
      Eye Window: ________________XXXXXX__________________
    Uplink 31:
      Optimal Phase: 38
      Window Length: 32
      Eye Window: _______________XXXXXXXX_________________

14:54:49:setup_element:INFO:	Performing Elink synchronization
14:54:49:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
14:54:49:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
14:54:49:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
14:54:49:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
14:54:49:setup_element:INFO:	Writing SMX Elink masks for group 0, downlink 2
14:54:49:uplink:INFO:	Enabling uplinks [16, 17, 18, 19, 20, 21, 24, 25, 26, 27, 28, 29, 30, 31]
14:54:49:ST3_emu:INFO:	Number of chips: 7
addr  |  upli  |  dwnli  |  grp |  uplinks | uplinks_map
   1  |   [0]   |  2  |  0  |     [30]     |  [(0, 30), (1, 31)]
   2  |   [0]   |  2  |  0  |     [21]     |  [(0, 21), (1, 20)]
   3  |   [0]   |  2  |  0  |     [28]     |  [(0, 28), (1, 29)]
   4  |   [0]   |  2  |  0  |     [19]     |  [(0, 19), (1, 18)]
   5  |   [0]   |  2  |  0  |     [26]     |  [(0, 26), (1, 27)]
   6  |   [0]   |  2  |  0  |     [17]     |  [(0, 17), (1, 16)]
   7  |   [0]   |  2  |  0  |     [24]     |  [(0, 24), (1, 25)]
FEB type: B FEB_A: 0 FEB_B: 1
14:54:50:febtest:ERROR:	HW addres 1 != 0
14:54:55:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:54:56:febtest:INFO:	30-01 | XA-000-08-002-000-005-163-01 |  50.4 | 1183.3
14:54:56:febtest:INFO:	21-02 | XA-000-08-002-000-005-161-01 |  21.9 | 1300.3
14:54:56:febtest:INFO:	28-03 | XA-000-08-002-000-005-156-08 |  50.4 | 1183.3
14:54:56:febtest:INFO:	19-04 | XA-000-08-002-000-005-158-08 |  37.7 | 1236.2
14:54:57:febtest:INFO:	26-05 | XA-000-08-002-000-005-159-08 |  34.6 | 1242.0
14:54:57:febtest:INFO:	17-06 | XA-000-08-002-000-005-155-08 |  34.6 | 1242.0
14:54:57:febtest:INFO:	24-07 | XA-000-08-002-000-005-162-01 |  63.2 | 1141.9
14:54:57:ST3_smx:INFO:	Configuring SMX FAST
14:54:59:ST3_smx:INFO:	chip: 30-1 	 40.898880 C 	 1224.468235 mV
14:54:59:ST3_smx:INFO:		Electrons
14:54:59:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
14:55:01:ST3_smx:INFO:	----> Checking Analog response
14:55:01:ST3_smx:INFO:	----> Checking broken channels
14:55:02:ST3_smx:INFO:	Total # broken ch: 2
14:55:02:ST3_smx:INFO:	List FAST: [6, 42]
14:55:02:ST3_smx:INFO:	List SLOW: []
14:55:02:ST3_smx:INFO:		Holes
14:55:02:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
14:55:04:ST3_smx:INFO:	----> Checking Analog response
14:55:04:ST3_smx:INFO:	----> Checking broken channels
14:55:04:ST3_smx:INFO:	Total # broken ch: 2
14:55:04:ST3_smx:INFO:	List FAST: [6, 42]
14:55:04:ST3_smx:INFO:	List SLOW: []
14:55:04:ST3_smx:INFO:	Configuring SMX FAST
14:55:06:ST3_smx:INFO:	chip: 21-2 	 34.556970 C 	 1253.730060 mV
14:55:06:ST3_smx:INFO:		Electrons
14:55:06:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
14:55:08:ST3_smx:INFO:	----> Checking Analog response
14:55:08:ST3_smx:INFO:	----> Checking broken channels
14:55:09:ST3_smx:INFO:	Total # broken ch: 2
14:55:09:ST3_smx:INFO:	List FAST: [2, 4]
14:55:09:ST3_smx:INFO:	List SLOW: []
14:55:09:ST3_smx:INFO:		Holes
14:55:09:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
14:55:11:ST3_smx:INFO:	----> Checking Analog response
14:55:11:ST3_smx:INFO:	----> Checking broken channels
14:55:11:ST3_smx:INFO:	Total # broken ch: 2
14:55:11:ST3_smx:INFO:	List FAST: [2, 4]
14:55:11:ST3_smx:INFO:	List SLOW: []
14:55:12:ST3_smx:INFO:	Configuring SMX FAST
14:55:14:ST3_smx:INFO:	chip: 28-3 	 56.797143 C 	 1165.571835 mV
14:55:14:ST3_smx:INFO:		Electrons
14:55:14:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
14:55:16:ST3_smx:INFO:	----> Checking Analog response
14:55:16:ST3_smx:INFO:	----> Checking broken channels
14:55:16:ST3_smx:INFO:	Total # broken ch: 1
14:55:16:ST3_smx:INFO:	List FAST: [108]
14:55:16:ST3_smx:INFO:	List SLOW: []
14:55:16:ST3_smx:INFO:		Holes
14:55:16:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
14:55:18:ST3_smx:INFO:	----> Checking Analog response
14:55:18:ST3_smx:INFO:	----> Checking broken channels
14:55:18:ST3_smx:INFO:	Total # broken ch: 1
14:55:18:ST3_smx:INFO:	List FAST: [108]
14:55:18:ST3_smx:INFO:	List SLOW: []
14:55:19:ST3_smx:INFO:	Configuring SMX FAST
14:55:21:ST3_smx:INFO:	chip: 19-4 	 44.073563 C 	 1212.728715 mV
14:55:21:ST3_smx:INFO:		Electrons
14:55:21:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
14:55:23:ST3_smx:INFO:	----> Checking Analog response
14:55:23:ST3_smx:INFO:	----> Checking broken channels
14:55:23:ST3_smx:INFO:	Total # broken ch: 3
14:55:23:ST3_smx:INFO:	List FAST: [1, 42, 76]
14:55:23:ST3_smx:INFO:	List SLOW: []
14:55:23:ST3_smx:INFO:		Holes
14:55:23:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
14:55:25:ST3_smx:INFO:	----> Checking Analog response
14:55:25:ST3_smx:INFO:	----> Checking broken channels
14:55:25:ST3_smx:INFO:	Total # broken ch: 3
14:55:25:ST3_smx:INFO:	List FAST: [1, 42, 76]
14:55:25:ST3_smx:INFO:	List SLOW: []
14:55:26:ST3_smx:INFO:	Configuring SMX FAST
14:55:28:ST3_smx:INFO:	chip: 26-5 	 47.250730 C 	 1206.851500 mV
14:55:28:ST3_smx:INFO:		Electrons
14:55:28:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
14:55:30:ST3_smx:INFO:	----> Checking Analog response
14:55:30:ST3_smx:INFO:	----> Checking broken channels
14:55:30:ST3_smx:INFO:	Total # broken ch: 4
14:55:30:ST3_smx:INFO:	List FAST: [46, 50, 68, 82]
14:55:30:ST3_smx:INFO:	List SLOW: []
14:55:30:ST3_smx:INFO:		Holes
14:55:30:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
14:55:32:ST3_smx:INFO:	----> Checking Analog response
14:55:32:ST3_smx:INFO:	----> Checking broken channels
14:55:32:ST3_smx:INFO:	Total # broken ch: 4
14:55:32:ST3_smx:INFO:	List FAST: [46, 50, 68, 82]
14:55:32:ST3_smx:INFO:	List SLOW: []
14:55:33:ST3_smx:INFO:	Configuring SMX FAST
14:55:35:ST3_smx:INFO:	chip: 17-6 	 37.726682 C 	 1230.330540 mV
14:55:35:ST3_smx:INFO:		Electrons
14:55:35:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
14:55:37:ST3_smx:INFO:	----> Checking Analog response
14:55:37:ST3_smx:INFO:	----> Checking broken channels
14:55:37:ST3_smx:INFO:	Total # broken ch: 4
14:55:37:ST3_smx:INFO:	List FAST: [52, 92, 106, 114]
14:55:37:ST3_smx:INFO:	List SLOW: []
14:55:37:ST3_smx:INFO:		Holes
14:55:37:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
14:55:39:ST3_smx:INFO:	----> Checking Analog response
14:55:39:ST3_smx:INFO:	----> Checking broken channels
14:55:40:ST3_smx:INFO:	Total # broken ch: 4
14:55:40:ST3_smx:INFO:	List FAST: [52, 92, 106, 114]
14:55:40:ST3_smx:INFO:	List SLOW: []
14:55:40:ST3_smx:INFO:	Configuring SMX FAST
14:55:42:ST3_smx:INFO:	chip: 24-7 	 63.173842 C 	 1141.874115 mV
14:55:42:ST3_smx:INFO:		Electrons
14:55:42:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
14:55:44:ST3_smx:INFO:	----> Checking Analog response
14:55:44:ST3_smx:INFO:	----> Checking broken channels
14:55:44:ST3_smx:INFO:	Total # broken ch: 1
14:55:44:ST3_smx:INFO:	List FAST: [126]
14:55:44:ST3_smx:INFO:	List SLOW: []
14:55:44:ST3_smx:INFO:		Holes
14:55:44:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
14:55:46:ST3_smx:INFO:	----> Checking Analog response
14:55:46:ST3_smx:INFO:	----> Checking broken channels
14:55:47:ST3_smx:INFO:	Total # broken ch: 1
14:55:47:ST3_smx:INFO:	List FAST: [126]
14:55:47:ST3_smx:INFO:	List SLOW: []
14:55:47:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:55:47:febtest:INFO:	30-01 | XA-000-08-002-000-005-163-01 |  40.9 | 1224.5
14:55:48:febtest:INFO:	21-02 | XA-000-08-002-000-005-161-01 |  37.7 | 1253.7
14:55:48:febtest:INFO:	28-03 | XA-000-08-002-000-005-156-08 |  56.8 | 1165.6
14:55:48:febtest:INFO:	19-04 | XA-000-08-002-000-005-158-08 |  47.3 | 1206.9
14:55:48:febtest:INFO:	26-05 | XA-000-08-002-000-005-159-08 |  47.3 | 1201.0
14:55:48:febtest:INFO:	17-06 | XA-000-08-002-000-005-155-08 |  40.9 | 1230.3
14:55:49:febtest:INFO:	24-07 | XA-000-08-002-000-005-162-01 |  63.2 | 1135.9
############################################################
#                   S U M M A R Y                          #
############################################################
===============================

{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

############################################################
#                   S U M M A R Y                          #
############################################################
TEST_NAME : FEB-ASIC
TEST_DATE : 24_04_09-14_54_36
OPERATOR  : Irakli K.; Ralf K.; 
SITE      : GSI
SETUP     : GSI_TEST_SETUP_1
Set-ID    : 
---------------------------------------
MODULE_NAME : 
FEB_SN : 2125
FEB_TYPE : 8.2
FEB_UPLINKS : 2
FEB_A : 0
FEB_B : 1
---------------------------------------
MODULE_NAME
---------------------------------------
VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.3930', '1.852', '2.2650']
VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.7700', '1.850', '0.2779']
VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.7690', '1.850', '0.2779']