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FEB_2128 28.05.24 13:45:43
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13:45:43:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
13:45:43:ST3_Shared:INFO: FEB-Microcable
13:45:43:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
13:45:43:febtest:INFO: Testing FEB with SN 2128
13:45:44:smx_tester:INFO: Scanning setup
13:45:44:elinks:INFO: Disabling clock on downlink 0
13:45:44:elinks:INFO: Disabling clock on downlink 1
13:45:44:elinks:INFO: Disabling clock on downlink 2
13:45:44:elinks:INFO: Disabling clock on downlink 3
13:45:44:elinks:INFO: Disabling clock on downlink 4
13:45:44:setup_element:INFO: Checking SOS, encoding_mode: SOS
13:45:44:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
13:45:44:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
13:45:44:elinks:INFO: Disabling clock on downlink 0
13:45:44:elinks:INFO: Disabling clock on downlink 1
13:45:44:elinks:INFO: Disabling clock on downlink 2
13:45:44:elinks:INFO: Disabling clock on downlink 3
13:45:44:elinks:INFO: Disabling clock on downlink 4
13:45:44:setup_element:INFO: Checking SOS, encoding_mode: SOS
13:45:44:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
13:45:45:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
13:45:45:elinks:INFO: Disabling clock on downlink 0
13:45:45:elinks:INFO: Disabling clock on downlink 1
13:45:45:elinks:INFO: Disabling clock on downlink 2
13:45:45:elinks:INFO: Disabling clock on downlink 3
13:45:45:elinks:INFO: Disabling clock on downlink 4
13:45:45:setup_element:INFO: Checking SOS, encoding_mode: SOS
13:45:45:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
13:45:45:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24
13:45:45:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25
13:45:45:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26
13:45:45:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27
13:45:45:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28
13:45:45:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29
13:45:45:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30
13:45:45:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31
13:45:45:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
13:45:45:elinks:INFO: Disabling clock on downlink 0
13:45:45:elinks:INFO: Disabling clock on downlink 1
13:45:45:elinks:INFO: Disabling clock on downlink 2
13:45:45:elinks:INFO: Disabling clock on downlink 3
13:45:45:elinks:INFO: Disabling clock on downlink 4
13:45:45:setup_element:INFO: Checking SOS, encoding_mode: SOS
13:45:45:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
13:45:45:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
13:45:45:elinks:INFO: Disabling clock on downlink 0
13:45:45:elinks:INFO: Disabling clock on downlink 1
13:45:45:elinks:INFO: Disabling clock on downlink 2
13:45:45:elinks:INFO: Disabling clock on downlink 3
13:45:45:elinks:INFO: Disabling clock on downlink 4
13:45:45:setup_element:INFO: Checking SOS, encoding_mode: SOS
13:45:45:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
13:45:45:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
13:45:45:setup_element:INFO: Scanning clock phase
13:45:45:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
13:45:45:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
13:45:45:setup_element:INFO: Clock phase scan results for group 0, downlink 2
13:45:45:setup_element:INFO: Eye window for uplink 24: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
13:45:45:setup_element:INFO: Eye window for uplink 25: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
13:45:45:setup_element:INFO: Eye window for uplink 26: ___________________________________________________________________XXXXXXXXX____
Clock Delay: 31
13:45:45:setup_element:INFO: Eye window for uplink 27: ___________________________________________________________________XXXXXXXXX____
Clock Delay: 31
13:45:45:setup_element:INFO: Eye window for uplink 28: ___________________________________________________________________XXXXXXX______
Clock Delay: 30
13:45:45:setup_element:INFO: Eye window for uplink 29: ___________________________________________________________________XXXXXXX______
Clock Delay: 30
13:45:45:setup_element:INFO: Eye window for uplink 30: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
13:45:45:setup_element:INFO: Eye window for uplink 31: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
13:45:45:setup_element:INFO: Setting the clock phase to 31 for group 0, downlink 2
13:45:45:setup_element:INFO: Scanning data phases
13:45:45:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
13:45:45:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
13:45:50:setup_element:INFO: Data phase scan results for group 0, downlink 2
13:45:50:setup_element:INFO: Eye window for uplink 24: __________XXXXXX________________________
Data delay found: 32
13:45:50:setup_element:INFO: Eye window for uplink 25: ____________XXXXXX______________________
Data delay found: 34
13:45:50:setup_element:INFO: Eye window for uplink 26: __________XXXX__________________________
Data delay found: 31
13:45:50:setup_element:INFO: Eye window for uplink 27: _____________XXXXX______________________
Data delay found: 35
13:45:51:setup_element:INFO: Eye window for uplink 28: ____________XXXXX_______________________
Data delay found: 34
13:45:51:setup_element:INFO: Eye window for uplink 29: ______________XXXXX_____________________
Data delay found: 36
13:45:51:setup_element:INFO: Eye window for uplink 30: _________________XXXXX__________________
Data delay found: 39
13:45:51:setup_element:INFO: Eye window for uplink 31: _________________XXXXXX_________________
Data delay found: 39
13:45:51:setup_element:INFO: Setting the data phase to 32 for uplink 24
13:45:51:setup_element:INFO: Setting the data phase to 34 for uplink 25
13:45:51:setup_element:INFO: Setting the data phase to 31 for uplink 26
13:45:51:setup_element:INFO: Setting the data phase to 35 for uplink 27
13:45:51:setup_element:INFO: Setting the data phase to 34 for uplink 28
13:45:51:setup_element:INFO: Setting the data phase to 36 for uplink 29
13:45:51:setup_element:INFO: Setting the data phase to 39 for uplink 30
13:45:51:setup_element:INFO: Setting the data phase to 39 for uplink 31
13:45:51:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 2
Uplinks: [24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 31
Window Length: 71
Eye Windows:
Uplink 24: ____________________________________________________________________XXXXXXXX____
Uplink 25: ____________________________________________________________________XXXXXXXX____
Uplink 26: ___________________________________________________________________XXXXXXXXX____
Uplink 27: ___________________________________________________________________XXXXXXXXX____
Uplink 28: ___________________________________________________________________XXXXXXX______
Uplink 29: ___________________________________________________________________XXXXXXX______
Uplink 30: ____________________________________________________________________XXXXXXXX____
Uplink 31: ____________________________________________________________________XXXXXXXX____
Data phase characteristics:
Uplink 24:
Optimal Phase: 32
Window Length: 34
Eye Window: __________XXXXXX________________________
Uplink 25:
Optimal Phase: 34
Window Length: 34
Eye Window: ____________XXXXXX______________________
Uplink 26:
Optimal Phase: 31
Window Length: 36
Eye Window: __________XXXX__________________________
Uplink 27:
Optimal Phase: 35
Window Length: 35
Eye Window: _____________XXXXX______________________
Uplink 28:
Optimal Phase: 34
Window Length: 35
Eye Window: ____________XXXXX_______________________
Uplink 29:
Optimal Phase: 36
Window Length: 35
Eye Window: ______________XXXXX_____________________
Uplink 30:
Optimal Phase: 39
Window Length: 35
Eye Window: _________________XXXXX__________________
Uplink 31:
Optimal Phase: 39
Window Length: 34
Eye Window: _________________XXXXXX_________________
]
13:45:51:setup_element:INFO: Beginning SMX ASICs map scan
13:45:51:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
13:45:51:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
13:45:51:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
13:45:51:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
13:45:51:uplink:INFO: Setting uplinks mask [24, 25, 26, 27, 28, 29, 30, 31]
13:45:51:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 30
13:45:51:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 31
13:45:51:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28
13:45:51:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 29
13:45:52:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26
13:45:52:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 27
13:45:52:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 24
13:45:52:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 25
13:45:53:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 2
Uplinks: [24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map:
ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
Clock Phase Characteristic:
Optimal Phase: 31
Window Length: 71
Eye Windows:
Uplink 24: ____________________________________________________________________XXXXXXXX____
Uplink 25: ____________________________________________________________________XXXXXXXX____
Uplink 26: ___________________________________________________________________XXXXXXXXX____
Uplink 27: ___________________________________________________________________XXXXXXXXX____
Uplink 28: ___________________________________________________________________XXXXXXX______
Uplink 29: ___________________________________________________________________XXXXXXX______
Uplink 30: ____________________________________________________________________XXXXXXXX____
Uplink 31: ____________________________________________________________________XXXXXXXX____
Data phase characteristics:
Uplink 24:
Optimal Phase: 32
Window Length: 34
Eye Window: __________XXXXXX________________________
Uplink 25:
Optimal Phase: 34
Window Length: 34
Eye Window: ____________XXXXXX______________________
Uplink 26:
Optimal Phase: 31
Window Length: 36
Eye Window: __________XXXX__________________________
Uplink 27:
Optimal Phase: 35
Window Length: 35
Eye Window: _____________XXXXX______________________
Uplink 28:
Optimal Phase: 34
Window Length: 35
Eye Window: ____________XXXXX_______________________
Uplink 29:
Optimal Phase: 36
Window Length: 35
Eye Window: ______________XXXXX_____________________
Uplink 30:
Optimal Phase: 39
Window Length: 35
Eye Window: _________________XXXXX__________________
Uplink 31:
Optimal Phase: 39
Window Length: 34
Eye Window: _________________XXXXXX_________________
13:45:53:setup_element:INFO: Performing Elink synchronization
13:45:53:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
13:45:53:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
13:45:53:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
13:45:53:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
13:45:53:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2
13:45:53:uplink:INFO: Enabling uplinks [24, 25, 26, 27, 28, 29, 30, 31]
13:45:53:ST3_emu:INFO: Number of chips: 4
addr | upli | dwnli | grp | uplinks | uplinks_map
1 | [0] | 2 | 0 | [30] | [(0, 30), (1, 31)]
3 | [0] | 2 | 0 | [28] | [(0, 28), (1, 29)]
5 | [0] | 2 | 0 | [26] | [(0, 26), (1, 27)]
7 | [0] | 2 | 0 | [24] | [(0, 24), (1, 25)]
13:45:54:febtest:INFO: Init all SMX (CSA): 30
13:46:01:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
13:46:02:febtest:INFO: 30-01 | XA-000-08-002-001-006-045-13 | 28.2 | 1189.2
13:46:02:febtest:INFO: 28-03 | XA-000-08-002-001-006-055-10 | 47.3 | 1124.0
13:46:02:febtest:INFO: 26-05 | XA-000-08-002-001-006-011-03 | 37.7 | 1147.8
13:46:02:febtest:INFO: 24-07 | XA-000-08-002-001-006-014-03 | 37.7 | 1147.8
13:46:03:febtest:INFO: Set all CSA to ZERO
FEB type: B FEB_A: 0 FEB_B: 1
13:46:05:ST3_smx:INFO: chip: 30-1 31.389742 C 1200.969315 mV
13:46:05:ST3_discr_histo:WARNING: Not enough entries for fit!!!
13:46:05:ST3_discr_histo:WARNING: Not enough entries for fit!!!
13:46:05:ST3_smx:INFO: Electrons
13:46:05:ST3_smx:INFO: # loops 0
13:46:07:ST3_smx:INFO: # loops 1
13:46:09:ST3_smx:INFO: # loops 2
13:46:10:ST3_smx:INFO: Total # of broken channels: 0
13:46:10:ST3_smx:INFO: List of broken channels: []
13:46:10:ST3_smx:INFO: Total # of broken channels: 0
13:46:10:ST3_smx:INFO: List of broken channels: []
13:46:12:ST3_smx:INFO: chip: 28-3 47.250730 C 1129.995435 mV
13:46:12:ST3_discr_histo:WARNING: Not enough entries for fit!!!
13:46:12:ST3_discr_histo:WARNING: Not enough entries for fit!!!
13:46:12:ST3_smx:INFO: Electrons
13:46:12:ST3_smx:INFO: # loops 0
13:46:14:ST3_smx:INFO: # loops 1
13:46:15:ST3_smx:INFO: # loops 2
13:46:17:ST3_smx:INFO: Total # of broken channels: 0
13:46:17:ST3_smx:INFO: List of broken channels: []
13:46:17:ST3_smx:INFO: Total # of broken channels: 0
13:46:17:ST3_smx:INFO: List of broken channels: []
13:46:19:ST3_smx:INFO: chip: 26-5 37.726682 C 1159.654860 mV
13:46:19:ST3_discr_histo:WARNING: Not enough entries for fit!!!
13:46:19:ST3_discr_histo:WARNING: Not enough entries for fit!!!
13:46:19:ST3_smx:INFO: Electrons
13:46:19:ST3_smx:INFO: # loops 0
13:46:21:ST3_smx:INFO: # loops 1
13:46:22:ST3_smx:INFO: # loops 2
13:46:24:ST3_smx:INFO: Total # of broken channels: 0
13:46:24:ST3_smx:INFO: List of broken channels: []
13:46:24:ST3_smx:INFO: Total # of broken channels: 0
13:46:24:ST3_smx:INFO: List of broken channels: []
13:46:26:ST3_smx:INFO: chip: 24-7 37.726682 C 1153.732915 mV
13:46:26:ST3_discr_histo:WARNING: Not enough entries for fit!!!
13:46:26:ST3_discr_histo:WARNING: Not enough entries for fit!!!
13:46:26:ST3_smx:INFO: Electrons
13:46:26:ST3_smx:INFO: # loops 0
13:46:27:ST3_smx:INFO: # loops 1
13:46:29:ST3_smx:INFO: # loops 2
13:46:31:ST3_smx:INFO: Total # of broken channels: 0
13:46:31:ST3_smx:INFO: List of broken channels: []
13:46:31:ST3_smx:INFO: Total # of broken channels: 0
13:46:31:ST3_smx:INFO: List of broken channels: []
13:46:31:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
13:46:31:febtest:INFO: 30-01 | XA-000-08-002-001-006-045-13 | 31.4 | 1218.6
13:46:32:febtest:INFO: 28-03 | XA-000-08-002-001-006-055-10 | 47.3 | 1153.7
13:46:32:febtest:INFO: 26-05 | XA-000-08-002-001-006-011-03 | 40.9 | 1177.4
13:46:32:febtest:INFO: 24-07 | XA-000-08-002-001-006-014-03 | 40.9 | 1171.5
############################################################
# S U M M A R Y #
############################################################
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-Microcable
TEST_DATE : 24_05_28-13_45_43
OPERATOR : Oleksandr S.; Robert V.;
SITE : GSI | SETUP : GSI_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 2128| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_B
------------------------------------------------------------
------------------------------------------------------------
VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '0.7943', '1.852', '1.1540']
VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.0200', '1.850', '1.2640']
VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '0.9970', '1.850', '0.2624']