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FEB_2128 09.04.24 14:59:13
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14:59:13:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:59:13:ST3_Shared:INFO: FEB-ASIC
14:59:13:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:59:14:febtest:INFO: Testing FEB with SN 2128
14:59:16:smx_tester:INFO: Scanning setup
14:59:16:elinks:INFO: Disabling clock on downlink 0
14:59:16:elinks:INFO: Disabling clock on downlink 1
14:59:16:elinks:INFO: Disabling clock on downlink 2
14:59:16:elinks:INFO: Disabling clock on downlink 3
14:59:16:elinks:INFO: Disabling clock on downlink 4
14:59:16:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:59:16:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
14:59:16:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:59:16:elinks:INFO: Disabling clock on downlink 0
14:59:16:elinks:INFO: Disabling clock on downlink 1
14:59:16:elinks:INFO: Disabling clock on downlink 2
14:59:16:elinks:INFO: Disabling clock on downlink 3
14:59:16:elinks:INFO: Disabling clock on downlink 4
14:59:16:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:59:16:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
14:59:16:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:59:16:elinks:INFO: Disabling clock on downlink 0
14:59:16:elinks:INFO: Disabling clock on downlink 1
14:59:16:elinks:INFO: Disabling clock on downlink 2
14:59:16:elinks:INFO: Disabling clock on downlink 3
14:59:16:elinks:INFO: Disabling clock on downlink 4
14:59:16:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:59:16:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
14:59:17:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24
14:59:17:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25
14:59:17:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26
14:59:17:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27
14:59:17:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30
14:59:17:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31
14:59:17:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:59:17:elinks:INFO: Disabling clock on downlink 0
14:59:17:elinks:INFO: Disabling clock on downlink 1
14:59:17:elinks:INFO: Disabling clock on downlink 2
14:59:17:elinks:INFO: Disabling clock on downlink 3
14:59:17:elinks:INFO: Disabling clock on downlink 4
14:59:17:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:59:17:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
14:59:17:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:59:17:elinks:INFO: Disabling clock on downlink 0
14:59:17:elinks:INFO: Disabling clock on downlink 1
14:59:17:elinks:INFO: Disabling clock on downlink 2
14:59:17:elinks:INFO: Disabling clock on downlink 3
14:59:17:elinks:INFO: Disabling clock on downlink 4
14:59:17:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:59:17:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
14:59:17:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:59:17:setup_element:INFO: Scanning clock phase
14:59:17:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
14:59:17:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
14:59:17:setup_element:INFO: Clock phase scan results for group 0, downlink 2
14:59:17:setup_element:INFO: Eye window for uplink 24: ___________________________________________________________________XXXXXXXX_____
Clock Delay: 30
14:59:17:setup_element:INFO: Eye window for uplink 25: ___________________________________________________________________XXXXXXXX_____
Clock Delay: 30
14:59:17:setup_element:INFO: Eye window for uplink 26: _________________________________________________________________XXXXXXXX_______
Clock Delay: 28
14:59:17:setup_element:INFO: Eye window for uplink 27: _________________________________________________________________XXXXXXXX_______
Clock Delay: 28
14:59:17:setup_element:INFO: Eye window for uplink 30: ___________________________________________________________________XXXXXXX______
Clock Delay: 30
14:59:17:setup_element:INFO: Eye window for uplink 31: ___________________________________________________________________XXXXXXX______
Clock Delay: 30
14:59:17:setup_element:INFO: Setting the clock phase to 29 for group 0, downlink 2
14:59:17:setup_element:INFO: Scanning data phases
14:59:17:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
14:59:17:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
14:59:23:setup_element:INFO: Data phase scan results for group 0, downlink 2
14:59:23:setup_element:INFO: Eye window for uplink 24: ________XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Data delay found: 3
14:59:23:setup_element:INFO: Eye window for uplink 25: ________XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Data delay found: 3
14:59:23:setup_element:INFO: Eye window for uplink 26: ______XXXXX_____________________________
Data delay found: 28
14:59:23:setup_element:INFO: Eye window for uplink 27: _________XXXXXX_________________________
Data delay found: 31
14:59:23:setup_element:INFO: Eye window for uplink 30: ______________XXXXXX____________________
Data delay found: 36
14:59:23:setup_element:INFO: Eye window for uplink 31: _______________XXXXXX___________________
Data delay found: 37
14:59:23:setup_element:INFO: Setting the data phase to 3 for uplink 24
14:59:23:setup_element:INFO: Setting the data phase to 3 for uplink 25
14:59:23:setup_element:INFO: Setting the data phase to 28 for uplink 26
14:59:23:setup_element:INFO: Setting the data phase to 31 for uplink 27
14:59:23:setup_element:INFO: Setting the data phase to 36 for uplink 30
14:59:23:setup_element:INFO: Setting the data phase to 37 for uplink 31
14:59:23:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 2
Uplinks: [24, 25, 26, 27, 30, 31]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 29
Window Length: 70
Eye Windows:
Uplink 24: ___________________________________________________________________XXXXXXXX_____
Uplink 25: ___________________________________________________________________XXXXXXXX_____
Uplink 26: _________________________________________________________________XXXXXXXX_______
Uplink 27: _________________________________________________________________XXXXXXXX_______
Uplink 30: ___________________________________________________________________XXXXXXX______
Uplink 31: ___________________________________________________________________XXXXXXX______
Data phase characteristics:
Uplink 24:
Optimal Phase: 3
Window Length: 8
Eye Window: ________XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Uplink 25:
Optimal Phase: 3
Window Length: 8
Eye Window: ________XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Uplink 26:
Optimal Phase: 28
Window Length: 35
Eye Window: ______XXXXX_____________________________
Uplink 27:
Optimal Phase: 31
Window Length: 34
Eye Window: _________XXXXXX_________________________
Uplink 30:
Optimal Phase: 36
Window Length: 34
Eye Window: ______________XXXXXX____________________
Uplink 31:
Optimal Phase: 37
Window Length: 34
Eye Window: _______________XXXXXX___________________
]
14:59:23:setup_element:INFO: Beginning SMX ASICs map scan
14:59:23:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
14:59:23:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
14:59:23:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
14:59:23:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
14:59:23:uplink:INFO: Setting uplinks mask [24, 25, 26, 27, 30, 31]
14:59:23:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 30
14:59:23:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 31
14:59:24:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26
14:59:24:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 27
14:59:24:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 24
14:59:24:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 25
14:59:25:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 2
Uplinks: [24, 25, 26, 27, 30, 31]
ASICs Map:
ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
Clock Phase Characteristic:
Optimal Phase: 29
Window Length: 70
Eye Windows:
Uplink 24: ___________________________________________________________________XXXXXXXX_____
Uplink 25: ___________________________________________________________________XXXXXXXX_____
Uplink 26: _________________________________________________________________XXXXXXXX_______
Uplink 27: _________________________________________________________________XXXXXXXX_______
Uplink 30: ___________________________________________________________________XXXXXXX______
Uplink 31: ___________________________________________________________________XXXXXXX______
Data phase characteristics:
Uplink 24:
Optimal Phase: 3
Window Length: 8
Eye Window: ________XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Uplink 25:
Optimal Phase: 3
Window Length: 8
Eye Window: ________XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Uplink 26:
Optimal Phase: 28
Window Length: 35
Eye Window: ______XXXXX_____________________________
Uplink 27:
Optimal Phase: 31
Window Length: 34
Eye Window: _________XXXXXX_________________________
Uplink 30:
Optimal Phase: 36
Window Length: 34
Eye Window: ______________XXXXXX____________________
Uplink 31:
Optimal Phase: 37
Window Length: 34
Eye Window: _______________XXXXXX___________________
14:59:25:setup_element:INFO: Performing Elink synchronization
14:59:25:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
14:59:25:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
14:59:25:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
14:59:25:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
14:59:25:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2
14:59:25:uplink:INFO: Enabling uplinks [24, 25, 26, 27, 30, 31]
14:59:25:ST3_emu:INFO: Number of chips: 3
addr | upli | dwnli | grp | uplinks | uplinks_map
1 | [0] | 2 | 0 | [30] | [(0, 30), (1, 31)]
5 | [0] | 2 | 0 | [26] | [(0, 26), (1, 27)]
7 | [0] | 2 | 0 | [24] | [(0, 24), (1, 25)]
FEB type: B FEB_A: 0 FEB_B: 1
14:59:26:febtest:ERROR: HW addres 1 != 0
14:59:34:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:59:34:febtest:INFO: 30-01 | XA-000-08-002-001-007-081-12 | 63.2 | 1124.0
14:59:34:febtest:INFO: 26-05 | XA-000-08-002-001-007-066-11 | 37.7 | 1206.9
14:59:34:febtest:INFO: 24-07 | XA-000-08-002-001-007-144-03 | 53.6 | 1147.8
14:59:34:ST3_smx:INFO: Configuring SMX FAST
14:59:36:ST3_smx:INFO: chip: 30-1 63.173842 C 1129.995435 mV
14:59:36:ST3_smx:INFO: Electrons
14:59:36:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:59:38:ST3_smx:INFO: ----> Checking Analog response
14:59:38:ST3_smx:INFO: ----> Checking broken channels
14:59:39:ST3_smx:INFO: Total # broken ch: 1
14:59:39:ST3_smx:INFO: List FAST: [19]
14:59:39:ST3_smx:INFO: List SLOW: []
14:59:39:ST3_smx:INFO: Holes
14:59:39:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:59:41:ST3_smx:INFO: ----> Checking Analog response
14:59:41:ST3_smx:INFO: ----> Checking broken channels
14:59:41:ST3_smx:INFO: Total # broken ch: 1
14:59:41:ST3_smx:INFO: List FAST: [19]
14:59:41:ST3_smx:INFO: List SLOW: []
14:59:42:ST3_smx:INFO: Configuring SMX FAST
14:59:44:ST3_smx:INFO: chip: 26-5 50.430383 C 1171.483840 mV
14:59:44:ST3_smx:INFO: Electrons
14:59:44:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:59:46:ST3_smx:INFO: ----> Checking Analog response
14:59:46:ST3_smx:INFO: ----> Checking broken channels
14:59:46:ST3_smx:INFO: Total # broken ch: 0
14:59:46:ST3_smx:INFO: List FAST: []
14:59:46:ST3_smx:INFO: List SLOW: []
14:59:46:ST3_smx:INFO: Holes
14:59:46:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:59:48:ST3_smx:INFO: ----> Checking Analog response
14:59:48:ST3_smx:INFO: ----> Checking broken channels
14:59:48:ST3_smx:INFO: Total # broken ch: 0
14:59:48:ST3_smx:INFO: List FAST: []
14:59:48:ST3_smx:INFO: List SLOW: []
14:59:49:ST3_smx:INFO: Configuring SMX FAST
14:59:51:ST3_smx:INFO: chip: 24-7 47.250730 C 1177.390875 mV
14:59:51:ST3_smx:INFO: Electrons
14:59:51:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:59:53:ST3_smx:INFO: ----> Checking Analog response
14:59:53:ST3_smx:INFO: ----> Checking broken channels
14:59:53:ST3_smx:INFO: Total # broken ch: 2
14:59:53:ST3_smx:INFO: List FAST: [15, 33]
14:59:53:ST3_smx:INFO: List SLOW: []
14:59:53:ST3_smx:INFO: Holes
14:59:53:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:59:55:ST3_smx:INFO: ----> Checking Analog response
14:59:55:ST3_smx:INFO: ----> Checking broken channels
14:59:56:ST3_smx:INFO: Total # broken ch: 2
14:59:56:ST3_smx:INFO: List FAST: [15, 33]
14:59:56:ST3_smx:INFO: List SLOW: []
14:59:56:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:59:56:febtest:INFO: 30-01 | XA-000-08-002-001-007-081-12 | 63.2 | 1124.0
14:59:57:febtest:INFO: 26-05 | XA-000-08-002-001-007-066-11 | 50.4 | 1171.5
14:59:57:febtest:INFO: 24-07 | XA-000-08-002-001-007-144-03 | 47.3 | 1171.5
############################################################
# S U M M A R Y #
############################################################
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-ASIC
TEST_DATE : 24_04_09-14_59_13
OPERATOR : Irakli K.; Ralf K.;
SITE : GSI
SETUP : GSI_TEST_SETUP_1
Set-ID :
---------------------------------------
MODULE_NAME :
FEB_SN : 2128
FEB_TYPE : 8.2
FEB_UPLINKS : 2
FEB_A : 0
FEB_B : 1
---------------------------------------
MODULE_NAME
---------------------------------------
VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '0.9204', '1.850', '1.1250']
VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '0.9437', '1.850', '0.3273']
VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '0.9432', '1.850', '0.3273']