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FEB_2150 04.04.24 11:07:51
Info
11:07:51:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
11:07:51:ST3_Shared:INFO: FEB-ASIC
11:07:51:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
11:07:52:febtest:INFO: Testing FEB with SN 2150
11:07:54:smx_tester:INFO: Scanning setup
11:07:54:elinks:INFO: Disabling clock on downlink 0
11:07:54:elinks:INFO: Disabling clock on downlink 1
11:07:54:elinks:INFO: Disabling clock on downlink 2
11:07:54:elinks:INFO: Disabling clock on downlink 3
11:07:54:elinks:INFO: Disabling clock on downlink 4
11:07:54:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:07:54:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
11:07:54:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:07:54:elinks:INFO: Disabling clock on downlink 0
11:07:54:elinks:INFO: Disabling clock on downlink 1
11:07:54:elinks:INFO: Disabling clock on downlink 2
11:07:54:elinks:INFO: Disabling clock on downlink 3
11:07:54:elinks:INFO: Disabling clock on downlink 4
11:07:54:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:07:54:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
11:07:55:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:07:55:elinks:INFO: Disabling clock on downlink 0
11:07:55:elinks:INFO: Disabling clock on downlink 1
11:07:55:elinks:INFO: Disabling clock on downlink 2
11:07:55:elinks:INFO: Disabling clock on downlink 3
11:07:55:elinks:INFO: Disabling clock on downlink 4
11:07:55:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:07:55:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
11:07:55:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 16
11:07:55:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 17
11:07:55:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 18
11:07:55:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 19
11:07:55:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 20
11:07:55:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 21
11:07:55:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 22
11:07:55:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 23
11:07:55:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24
11:07:55:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25
11:07:55:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26
11:07:55:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27
11:07:55:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28
11:07:55:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29
11:07:55:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30
11:07:55:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31
11:07:55:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:07:55:elinks:INFO: Disabling clock on downlink 0
11:07:55:elinks:INFO: Disabling clock on downlink 1
11:07:55:elinks:INFO: Disabling clock on downlink 2
11:07:55:elinks:INFO: Disabling clock on downlink 3
11:07:55:elinks:INFO: Disabling clock on downlink 4
11:07:55:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:07:55:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
11:07:55:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:07:55:elinks:INFO: Disabling clock on downlink 0
11:07:55:elinks:INFO: Disabling clock on downlink 1
11:07:55:elinks:INFO: Disabling clock on downlink 2
11:07:55:elinks:INFO: Disabling clock on downlink 3
11:07:55:elinks:INFO: Disabling clock on downlink 4
11:07:55:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:07:55:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
11:07:55:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:07:55:setup_element:INFO: Scanning clock phase
11:07:55:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
11:07:55:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
11:07:55:setup_element:INFO: Clock phase scan results for group 0, downlink 2
11:07:55:setup_element:INFO: Eye window for uplink 16: _____________________________________________________________________XXXXXXXXX__
Clock Delay: 33
11:07:55:setup_element:INFO: Eye window for uplink 17: _____________________________________________________________________XXXXXXXXX__
Clock Delay: 33
11:07:55:setup_element:INFO: Eye window for uplink 18: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
11:07:55:setup_element:INFO: Eye window for uplink 19: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
11:07:55:setup_element:INFO: Eye window for uplink 20: _____________________________________________________________________XXXXXXX____
Clock Delay: 32
11:07:55:setup_element:INFO: Eye window for uplink 21: _____________________________________________________________________XXXXXXX____
Clock Delay: 32
11:07:55:setup_element:INFO: Eye window for uplink 22: ________________________________________________________________________________
Clock Delay: 40
11:07:55:setup_element:INFO: Eye window for uplink 23: ________________________________________________________________________________
Clock Delay: 40
11:07:55:setup_element:INFO: Eye window for uplink 24: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
11:07:55:setup_element:INFO: Eye window for uplink 25: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
11:07:55:setup_element:INFO: Eye window for uplink 26: _____________________________________________________________________XXXXXXXXX__
Clock Delay: 33
11:07:55:setup_element:INFO: Eye window for uplink 27: _____________________________________________________________________XXXXXXXXX__
Clock Delay: 33
11:07:55:setup_element:INFO: Eye window for uplink 28: _____________________________________________________________________XXXXXXXXXX_
Clock Delay: 33
11:07:55:setup_element:INFO: Eye window for uplink 29: _____________________________________________________________________XXXXXXXXXX_
Clock Delay: 33
11:07:55:setup_element:INFO: Eye window for uplink 30: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
11:07:55:setup_element:INFO: Eye window for uplink 31: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
11:07:55:setup_element:INFO: Setting the clock phase to 33 for group 0, downlink 2
11:07:55:setup_element:INFO: Scanning data phases
11:07:55:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
11:07:56:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
11:08:01:setup_element:INFO: Data phase scan results for group 0, downlink 2
11:08:01:setup_element:INFO: Eye window for uplink 16: XX____________________________________XX
Data delay found: 19
11:08:01:setup_element:INFO: Eye window for uplink 17: X___________________________________XXXX
Data delay found: 18
11:08:01:setup_element:INFO: Eye window for uplink 18: X_______________________________XXXXXXXX
Data delay found: 16
11:08:01:setup_element:INFO: Eye window for uplink 19: ________________________________XXXXXXXX
Data delay found: 15
11:08:01:setup_element:INFO: Eye window for uplink 20: XX____________________________________XX
Data delay found: 19
11:08:01:setup_element:INFO: Eye window for uplink 21: XX_________________________________XXXXX
Data delay found: 18
11:08:01:setup_element:INFO: Eye window for uplink 22: XXX_____________________________XXXXXXXX
Data delay found: 17
11:08:01:setup_element:INFO: Eye window for uplink 23: XXXXX___________________________XXXXXXXX
Data delay found: 18
11:08:01:setup_element:INFO: Eye window for uplink 24: _______XXXXX____________________________
Data delay found: 29
11:08:01:setup_element:INFO: Eye window for uplink 25: __________XXXX__________________________
Data delay found: 31
11:08:01:setup_element:INFO: Eye window for uplink 26: __________XXXXX_________________________
Data delay found: 32
11:08:01:setup_element:INFO: Eye window for uplink 27: ______________XXXXX_____________________
Data delay found: 36
11:08:01:setup_element:INFO: Eye window for uplink 28: ________________XXXXX___________________
Data delay found: 38
11:08:01:setup_element:INFO: Eye window for uplink 29: __________________XXXXX_________________
Data delay found: 0
11:08:01:setup_element:INFO: Eye window for uplink 30: _________________XXXXXX_________________
Data delay found: 39
11:08:01:setup_element:INFO: Eye window for uplink 31: ________________XXXXXXXX________________
Data delay found: 39
11:08:01:setup_element:INFO: Setting the data phase to 19 for uplink 16
11:08:01:setup_element:INFO: Setting the data phase to 18 for uplink 17
11:08:01:setup_element:INFO: Setting the data phase to 16 for uplink 18
11:08:01:setup_element:INFO: Setting the data phase to 15 for uplink 19
11:08:01:setup_element:INFO: Setting the data phase to 19 for uplink 20
11:08:01:setup_element:INFO: Setting the data phase to 18 for uplink 21
11:08:01:setup_element:INFO: Setting the data phase to 17 for uplink 22
11:08:01:setup_element:INFO: Setting the data phase to 18 for uplink 23
11:08:01:setup_element:INFO: Setting the data phase to 29 for uplink 24
11:08:01:setup_element:INFO: Setting the data phase to 31 for uplink 25
11:08:01:setup_element:INFO: Setting the data phase to 32 for uplink 26
11:08:01:setup_element:INFO: Setting the data phase to 36 for uplink 27
11:08:01:setup_element:INFO: Setting the data phase to 38 for uplink 28
11:08:01:setup_element:INFO: Setting the data phase to 0 for uplink 29
11:08:01:setup_element:INFO: Setting the data phase to 39 for uplink 30
11:08:01:setup_element:INFO: Setting the data phase to 39 for uplink 31
11:08:01:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 33
Window Length: 69
Eye Windows:
Uplink 16: _____________________________________________________________________XXXXXXXXX__
Uplink 17: _____________________________________________________________________XXXXXXXXX__
Uplink 18: _____________________________________________________________________XXXXXXXX___
Uplink 19: _____________________________________________________________________XXXXXXXX___
Uplink 20: _____________________________________________________________________XXXXXXX____
Uplink 21: _____________________________________________________________________XXXXXXX____
Uplink 22: ________________________________________________________________________________
Uplink 23: ________________________________________________________________________________
Uplink 24: ____________________________________________________________________XXXXXXXX____
Uplink 25: ____________________________________________________________________XXXXXXXX____
Uplink 26: _____________________________________________________________________XXXXXXXXX__
Uplink 27: _____________________________________________________________________XXXXXXXXX__
Uplink 28: _____________________________________________________________________XXXXXXXXXX_
Uplink 29: _____________________________________________________________________XXXXXXXXXX_
Uplink 30: _______________________________________________________________________XXXXXXXX_
Uplink 31: _______________________________________________________________________XXXXXXXX_
Data phase characteristics:
Uplink 16:
Optimal Phase: 19
Window Length: 36
Eye Window: XX____________________________________XX
Uplink 17:
Optimal Phase: 18
Window Length: 35
Eye Window: X___________________________________XXXX
Uplink 18:
Optimal Phase: 16
Window Length: 31
Eye Window: X_______________________________XXXXXXXX
Uplink 19:
Optimal Phase: 15
Window Length: 32
Eye Window: ________________________________XXXXXXXX
Uplink 20:
Optimal Phase: 19
Window Length: 36
Eye Window: XX____________________________________XX
Uplink 21:
Optimal Phase: 18
Window Length: 33
Eye Window: XX_________________________________XXXXX
Uplink 22:
Optimal Phase: 17
Window Length: 29
Eye Window: XXX_____________________________XXXXXXXX
Uplink 23:
Optimal Phase: 18
Window Length: 27
Eye Window: XXXXX___________________________XXXXXXXX
Uplink 24:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 25:
Optimal Phase: 31
Window Length: 36
Eye Window: __________XXXX__________________________
Uplink 26:
Optimal Phase: 32
Window Length: 35
Eye Window: __________XXXXX_________________________
Uplink 27:
Optimal Phase: 36
Window Length: 35
Eye Window: ______________XXXXX_____________________
Uplink 28:
Optimal Phase: 38
Window Length: 35
Eye Window: ________________XXXXX___________________
Uplink 29:
Optimal Phase: 0
Window Length: 35
Eye Window: __________________XXXXX_________________
Uplink 30:
Optimal Phase: 39
Window Length: 34
Eye Window: _________________XXXXXX_________________
Uplink 31:
Optimal Phase: 39
Window Length: 32
Eye Window: ________________XXXXXXXX________________
]
11:08:01:setup_element:INFO: Beginning SMX ASICs map scan
11:08:01:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
11:08:01:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
11:08:01:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
11:08:01:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
11:08:01:uplink:INFO: Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
11:08:01:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 23
11:08:01:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 22
11:08:01:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 30
11:08:01:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 31
11:08:02:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 21
11:08:02:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 20
11:08:02:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28
11:08:02:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 29
11:08:02:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 19
11:08:02:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 18
11:08:02:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26
11:08:02:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 27
11:08:02:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 17
11:08:02:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 16
11:08:02:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 24
11:08:03:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 25
11:08:04:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 23), (1, 22)
ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
ASIC address 0x2: (ASIC uplink, uplink): (0, 21), (1, 20)
ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
ASIC address 0x4: (ASIC uplink, uplink): (0, 19), (1, 18)
ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
ASIC address 0x6: (ASIC uplink, uplink): (0, 17), (1, 16)
ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
Clock Phase Characteristic:
Optimal Phase: 33
Window Length: 69
Eye Windows:
Uplink 16: _____________________________________________________________________XXXXXXXXX__
Uplink 17: _____________________________________________________________________XXXXXXXXX__
Uplink 18: _____________________________________________________________________XXXXXXXX___
Uplink 19: _____________________________________________________________________XXXXXXXX___
Uplink 20: _____________________________________________________________________XXXXXXX____
Uplink 21: _____________________________________________________________________XXXXXXX____
Uplink 22: ________________________________________________________________________________
Uplink 23: ________________________________________________________________________________
Uplink 24: ____________________________________________________________________XXXXXXXX____
Uplink 25: ____________________________________________________________________XXXXXXXX____
Uplink 26: _____________________________________________________________________XXXXXXXXX__
Uplink 27: _____________________________________________________________________XXXXXXXXX__
Uplink 28: _____________________________________________________________________XXXXXXXXXX_
Uplink 29: _____________________________________________________________________XXXXXXXXXX_
Uplink 30: _______________________________________________________________________XXXXXXXX_
Uplink 31: _______________________________________________________________________XXXXXXXX_
Data phase characteristics:
Uplink 16:
Optimal Phase: 19
Window Length: 36
Eye Window: XX____________________________________XX
Uplink 17:
Optimal Phase: 18
Window Length: 35
Eye Window: X___________________________________XXXX
Uplink 18:
Optimal Phase: 16
Window Length: 31
Eye Window: X_______________________________XXXXXXXX
Uplink 19:
Optimal Phase: 15
Window Length: 32
Eye Window: ________________________________XXXXXXXX
Uplink 20:
Optimal Phase: 19
Window Length: 36
Eye Window: XX____________________________________XX
Uplink 21:
Optimal Phase: 18
Window Length: 33
Eye Window: XX_________________________________XXXXX
Uplink 22:
Optimal Phase: 17
Window Length: 29
Eye Window: XXX_____________________________XXXXXXXX
Uplink 23:
Optimal Phase: 18
Window Length: 27
Eye Window: XXXXX___________________________XXXXXXXX
Uplink 24:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 25:
Optimal Phase: 31
Window Length: 36
Eye Window: __________XXXX__________________________
Uplink 26:
Optimal Phase: 32
Window Length: 35
Eye Window: __________XXXXX_________________________
Uplink 27:
Optimal Phase: 36
Window Length: 35
Eye Window: ______________XXXXX_____________________
Uplink 28:
Optimal Phase: 38
Window Length: 35
Eye Window: ________________XXXXX___________________
Uplink 29:
Optimal Phase: 0
Window Length: 35
Eye Window: __________________XXXXX_________________
Uplink 30:
Optimal Phase: 39
Window Length: 34
Eye Window: _________________XXXXXX_________________
Uplink 31:
Optimal Phase: 39
Window Length: 32
Eye Window: ________________XXXXXXXX________________
11:08:04:setup_element:INFO: Performing Elink synchronization
11:08:04:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
11:08:04:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
11:08:04:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
11:08:04:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
11:08:04:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2
11:08:04:uplink:INFO: Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
11:08:04:ST3_emu:INFO: Number of chips: 8
addr | upli | dwnli | grp | uplinks | uplinks_map
0 | [0] | 2 | 0 | [23] | [(0, 23), (1, 22)]
1 | [0] | 2 | 0 | [30] | [(0, 30), (1, 31)]
2 | [0] | 2 | 0 | [21] | [(0, 21), (1, 20)]
3 | [0] | 2 | 0 | [28] | [(0, 28), (1, 29)]
4 | [0] | 2 | 0 | [19] | [(0, 19), (1, 18)]
5 | [0] | 2 | 0 | [26] | [(0, 26), (1, 27)]
6 | [0] | 2 | 0 | [17] | [(0, 17), (1, 16)]
7 | [0] | 2 | 0 | [24] | [(0, 24), (1, 25)]
FEB type: B FEB_A: 0 FEB_B: 1
11:08:06:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
11:08:06:febtest:INFO: 23-00 | XA-000-08-002-001-008-163-14 | 6.1 | 1282.9
11:08:06:febtest:INFO: 30-01 | XA-000-08-002-002-006-025-05 | 28.2 | 1224.5
11:08:06:febtest:INFO: 21-02 | XA-000-08-002-001-008-161-14 | 3.0 | 1300.3
11:08:07:febtest:INFO: 28-03 | XA-000-08-002-002-006-027-05 | 31.4 | 1317.7
11:08:07:febtest:INFO: 19-04 | XA-000-08-002-001-008-153-07 | 15.6 | 1259.6
11:08:07:febtest:INFO: 26-05 | XA-000-08-002-002-006-028-05 | 44.1 | 1177.4
11:08:07:febtest:INFO: 17-06 | XA-000-08-002-001-008-198-05 | 34.6 | 1195.1
11:08:08:febtest:INFO: 24-07 | XA-000-08-002-002-006-050-11 | 12.4 | 1277.1
11:08:08:ST3_smx:INFO: Configuring SMX FAST
11:08:10:ST3_smx:INFO: chip: 23-0 18.745682 C 1242.040240 mV
11:08:10:ST3_smx:INFO: Electrons
11:08:10:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
11:08:12:ST3_smx:INFO: ----> Checking Analog response
11:08:12:ST3_smx:INFO: ----> Checking broken channels
11:08:12:ST3_smx:INFO: Total # broken ch: 0
11:08:12:ST3_smx:INFO: List FAST: []
11:08:12:ST3_smx:INFO: List SLOW: []
11:08:12:ST3_smx:INFO: Holes
11:08:12:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
11:08:14:ST3_smx:INFO: ----> Checking Analog response
11:08:14:ST3_smx:INFO: ----> Checking broken channels
11:08:14:ST3_smx:INFO: Total # broken ch: 0
11:08:14:ST3_smx:INFO: List FAST: []
11:08:14:ST3_smx:INFO: List SLOW: []
11:08:15:ST3_smx:INFO: Configuring SMX FAST
11:08:17:ST3_smx:INFO: chip: 30-1 31.389742 C 1212.728715 mV
11:08:17:ST3_smx:INFO: Electrons
11:08:17:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
11:08:19:ST3_smx:INFO: ----> Checking Analog response
11:08:19:ST3_smx:INFO: ----> Checking broken channels
11:08:19:ST3_smx:INFO: Total # broken ch: 0
11:08:19:ST3_smx:INFO: List FAST: []
11:08:19:ST3_smx:INFO: List SLOW: []
11:08:19:ST3_smx:INFO: Holes
11:08:19:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
11:08:21:ST3_smx:INFO: ----> Checking Analog response
11:08:21:ST3_smx:INFO: ----> Checking broken channels
11:08:22:ST3_smx:INFO: Total # broken ch: 0
11:08:22:ST3_smx:INFO: List FAST: []
11:08:22:ST3_smx:INFO: List SLOW: []
11:08:22:ST3_smx:INFO: Configuring SMX FAST
11:08:24:ST3_smx:INFO: chip: 21-2 15.590880 C 1265.400000 mV
11:08:24:ST3_smx:INFO: Electrons
11:08:24:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
11:08:26:ST3_smx:INFO: ----> Checking Analog response
11:08:26:ST3_smx:INFO: ----> Checking broken channels
11:08:26:ST3_smx:INFO: Total # broken ch: 0
11:08:26:ST3_smx:INFO: List FAST: []
11:08:26:ST3_smx:INFO: List SLOW: []
11:08:26:ST3_smx:INFO: Holes
11:08:26:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
11:08:28:ST3_smx:INFO: ----> Checking Analog response
11:08:28:ST3_smx:INFO: ----> Checking broken channels
11:08:29:ST3_smx:INFO: Total # broken ch: 0
11:08:29:ST3_smx:INFO: List FAST: []
11:08:29:ST3_smx:INFO: List SLOW: []
11:08:29:ST3_smx:INFO: Configuring SMX FAST
11:08:31:ST3_smx:INFO: chip: 28-3 28.225000 C 1363.791835 mV
11:08:31:ST3_smx:INFO: Electrons
11:08:31:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
11:08:33:ST3_smx:INFO: ----> Checking Analog response
11:08:33:ST3_smx:INFO: ----> Checking broken channels
11:08:33:ST3_smx:INFO: Total # broken ch: 0
11:08:33:ST3_smx:INFO: List FAST: []
11:08:33:ST3_smx:INFO: List SLOW: []
11:08:33:ST3_smx:INFO: Holes
11:08:34:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
11:08:35:ST3_smx:INFO: ----> Checking Analog response
11:08:35:ST3_smx:INFO: ----> Checking broken channels
11:08:36:ST3_smx:INFO: Total # broken ch: 0
11:08:36:ST3_smx:INFO: List FAST: []
11:08:36:ST3_smx:INFO: List SLOW: []
11:08:36:ST3_smx:INFO: Configuring SMX FAST
11:08:38:ST3_smx:INFO: chip: 19-4 28.225000 C 1224.468235 mV
11:08:38:ST3_smx:INFO: Electrons
11:08:38:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
11:08:40:ST3_smx:INFO: ----> Checking Analog response
11:08:40:ST3_smx:INFO: ----> Checking broken channels
11:08:40:ST3_smx:INFO: Total # broken ch: 0
11:08:40:ST3_smx:INFO: List FAST: []
11:08:40:ST3_smx:INFO: List SLOW: []
11:08:40:ST3_smx:INFO: Holes
11:08:40:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
11:08:42:ST3_smx:INFO: ----> Checking Analog response
11:08:42:ST3_smx:INFO: ----> Checking broken channels
11:08:43:ST3_smx:INFO: Total # broken ch: 0
11:08:43:ST3_smx:INFO: List FAST: []
11:08:43:ST3_smx:INFO: List SLOW: []
11:08:43:ST3_smx:INFO: Configuring SMX FAST
11:08:45:ST3_smx:INFO: chip: 26-5 50.430383 C 1159.654860 mV
11:08:45:ST3_smx:INFO: Electrons
11:08:45:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
11:08:47:ST3_smx:INFO: ----> Checking Analog response
11:08:47:ST3_smx:INFO: ----> Checking broken channels
11:08:47:ST3_smx:INFO: Total # broken ch: 0
11:08:47:ST3_smx:INFO: List FAST: []
11:08:47:ST3_smx:INFO: List SLOW: []
11:08:47:ST3_smx:INFO: Holes
11:08:47:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
11:08:49:ST3_smx:INFO: ----> Checking Analog response
11:08:49:ST3_smx:INFO: ----> Checking broken channels
11:08:50:ST3_smx:INFO: Total # broken ch: 0
11:08:50:ST3_smx:INFO: List FAST: []
11:08:50:ST3_smx:INFO: List SLOW: []
11:08:50:ST3_smx:INFO: Configuring SMX FAST
11:08:52:ST3_smx:INFO: chip: 17-6 40.898880 C 1177.390875 mV
11:08:52:ST3_smx:INFO: Electrons
11:08:52:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
11:08:54:ST3_smx:INFO: ----> Checking Analog response
11:08:54:ST3_smx:INFO: ----> Checking broken channels
11:08:54:ST3_smx:INFO: Total # broken ch: 0
11:08:54:ST3_smx:INFO: List FAST: []
11:08:54:ST3_smx:INFO: List SLOW: []
11:08:54:ST3_smx:INFO: Holes
11:08:54:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
11:08:56:ST3_smx:INFO: ----> Checking Analog response
11:08:56:ST3_smx:INFO: ----> Checking broken channels
11:08:57:ST3_smx:INFO: Total # broken ch: 0
11:08:57:ST3_smx:INFO: List FAST: []
11:08:57:ST3_smx:INFO: List SLOW: []
11:08:57:ST3_smx:INFO: Configuring SMX FAST
11:08:59:ST3_smx:INFO: chip: 24-7 9.288730 C 1300.290540 mV
11:08:59:ST3_smx:INFO: Electrons
11:08:59:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
11:09:01:ST3_smx:INFO: ----> Checking Analog response
11:09:01:ST3_smx:INFO: ----> Checking broken channels
11:09:02:ST3_smx:INFO: Total # broken ch: 0
11:09:02:ST3_smx:INFO: List FAST: []
11:09:02:ST3_smx:INFO: List SLOW: []
11:09:02:ST3_smx:INFO: Holes
11:09:02:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
11:09:03:ST3_smx:INFO: ----> Checking Analog response
11:09:03:ST3_smx:INFO: ----> Checking broken channels
11:09:04:ST3_smx:INFO: Total # broken ch: 0
11:09:04:ST3_smx:INFO: List FAST: []
11:09:04:ST3_smx:INFO: List SLOW: []
11:09:04:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
11:09:05:febtest:INFO: 23-00 | XA-000-08-002-001-008-163-14 | 25.1 | 1236.2
11:09:05:febtest:INFO: 30-01 | XA-000-08-002-002-006-025-05 | 34.6 | 1212.7
11:09:05:febtest:INFO: 21-02 | XA-000-08-002-001-008-161-14 | 18.7 | 1259.6
11:09:05:febtest:INFO: 28-03 | XA-000-08-002-002-006-027-05 | 31.4 | 1472.1
11:09:05:febtest:INFO: 19-04 | XA-000-08-002-001-008-153-07 | 31.4 | 1218.6
11:09:06:febtest:INFO: 26-05 | XA-000-08-002-002-006-028-05 | 50.4 | 1159.7
11:09:06:febtest:INFO: 17-06 | XA-000-08-002-001-008-198-05 | 40.9 | 1171.5
11:09:06:febtest:INFO: 24-07 | XA-000-08-002-002-006-050-11 | 9.3 | 1294.5
############################################################
# S U M M A R Y #
############################################################
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-ASIC
TEST_DATE : 24_04_04-11_07_51
OPERATOR : Oleksandr S.;
SITE : GSI
SETUP : GSI_TEST_SETUP_1
Set-ID :
---------------------------------------
MODULE_NAME :
FEB_SN : 2150
FEB_TYPE : 8.2
FEB_UPLINKS : 2
FEB_A : 0
FEB_B : 1
---------------------------------------
MODULE_NAME
---------------------------------------
VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.3800', '1.852', '1.7690']
VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.9950', '1.850', '0.3142']
VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.9920', '1.850', '0.3141']
Comment
Test FEB from EE with ASICs ADC not 0