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FEB_2158 05.06.24 08:35:28
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08:35:28:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
08:35:28:ST3_Shared:INFO: FEB-Sensor
08:35:28:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
08:35:31:ST3_ModuleSelector:INFO: L4DL000161 M4DL0T3001613A2 124 C
08:35:31:ST3_ModuleSelector:INFO: 23094
08:35:31:febtest:INFO: Testing FEB with SN 2158
08:35:32:smx_tester:INFO: Scanning setup
08:35:32:elinks:INFO: Disabling clock on downlink 0
08:35:32:elinks:INFO: Disabling clock on downlink 1
08:35:32:elinks:INFO: Disabling clock on downlink 2
08:35:32:elinks:INFO: Disabling clock on downlink 3
08:35:32:elinks:INFO: Disabling clock on downlink 4
08:35:32:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:35:32:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
08:35:32:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:35:32:elinks:INFO: Disabling clock on downlink 0
08:35:32:elinks:INFO: Disabling clock on downlink 1
08:35:32:elinks:INFO: Disabling clock on downlink 2
08:35:32:elinks:INFO: Disabling clock on downlink 3
08:35:32:elinks:INFO: Disabling clock on downlink 4
08:35:32:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:35:32:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
08:35:32:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:35:32:elinks:INFO: Disabling clock on downlink 0
08:35:32:elinks:INFO: Disabling clock on downlink 1
08:35:32:elinks:INFO: Disabling clock on downlink 2
08:35:33:elinks:INFO: Disabling clock on downlink 3
08:35:33:elinks:INFO: Disabling clock on downlink 4
08:35:33:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:35:33:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
08:35:33:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 16
08:35:33:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 17
08:35:33:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 18
08:35:33:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 19
08:35:33:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 20
08:35:33:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 21
08:35:33:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 22
08:35:33:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 23
08:35:33:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24
08:35:33:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25
08:35:33:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26
08:35:33:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27
08:35:33:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28
08:35:33:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29
08:35:33:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30
08:35:33:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31
08:35:33:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:35:33:elinks:INFO: Disabling clock on downlink 0
08:35:33:elinks:INFO: Disabling clock on downlink 1
08:35:33:elinks:INFO: Disabling clock on downlink 2
08:35:33:elinks:INFO: Disabling clock on downlink 3
08:35:33:elinks:INFO: Disabling clock on downlink 4
08:35:33:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:35:33:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
08:35:33:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:35:33:elinks:INFO: Disabling clock on downlink 0
08:35:33:elinks:INFO: Disabling clock on downlink 1
08:35:33:elinks:INFO: Disabling clock on downlink 2
08:35:33:elinks:INFO: Disabling clock on downlink 3
08:35:33:elinks:INFO: Disabling clock on downlink 4
08:35:33:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:35:33:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
08:35:33:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:35:33:setup_element:INFO: Scanning clock phase
08:35:33:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
08:35:33:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
08:35:33:setup_element:INFO: Clock phase scan results for group 0, downlink 2
08:35:33:setup_element:INFO: Eye window for uplink 16: ______________________________________________________________________XXXXXXX___
Clock Delay: 33
08:35:33:setup_element:INFO: Eye window for uplink 17: ______________________________________________________________________XXXXXXX___
Clock Delay: 33
08:35:33:setup_element:INFO: Eye window for uplink 18: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
08:35:33:setup_element:INFO: Eye window for uplink 19: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
08:35:33:setup_element:INFO: Eye window for uplink 20: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
08:35:33:setup_element:INFO: Eye window for uplink 21: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
08:35:33:setup_element:INFO: Eye window for uplink 22: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
08:35:33:setup_element:INFO: Eye window for uplink 23: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
08:35:33:setup_element:INFO: Eye window for uplink 24: ____________________________________________________________________XXXXXXX_____
Clock Delay: 31
08:35:33:setup_element:INFO: Eye window for uplink 25: ____________________________________________________________________XXXXXXX_____
Clock Delay: 31
08:35:33:setup_element:INFO: Eye window for uplink 26: ____________________________________________________________________XXXXXXXXX___
Clock Delay: 32
08:35:33:setup_element:INFO: Eye window for uplink 27: ____________________________________________________________________XXXXXXXXX___
Clock Delay: 32
08:35:33:setup_element:INFO: Eye window for uplink 28: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
08:35:33:setup_element:INFO: Eye window for uplink 29: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
08:35:33:setup_element:INFO: Eye window for uplink 30: ________________________________________________________________________________
Clock Delay: 40
08:35:33:setup_element:INFO: Eye window for uplink 31: ________________________________________________________________________________
Clock Delay: 40
08:35:33:setup_element:INFO: Setting the clock phase to 32 for group 0, downlink 2
08:35:33:setup_element:INFO: Scanning data phases
08:35:33:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
08:35:34:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
08:35:39:setup_element:INFO: Data phase scan results for group 0, downlink 2
08:35:39:setup_element:INFO: Eye window for uplink 16: XXX___________________________________XX
Data delay found: 20
08:35:39:setup_element:INFO: Eye window for uplink 17: XX__________________________________XXXX
Data delay found: 18
08:35:39:setup_element:INFO: Eye window for uplink 18: XXX__________________________________XXX
Data delay found: 19
08:35:39:setup_element:INFO: Eye window for uplink 19: X__________________________________XXXXX
Data delay found: 17
08:35:39:setup_element:INFO: Eye window for uplink 20: ___________________________________XXXXX
Data delay found: 17
08:35:39:setup_element:INFO: Eye window for uplink 21: __________________________________XXXXX_
Data delay found: 16
08:35:39:setup_element:INFO: Eye window for uplink 22: XX_____XXXXX_________________________XXX
Data delay found: 24
08:35:39:setup_element:INFO: Eye window for uplink 23: XXXXXX_XXXXX_______________________XXXXX
Data delay found: 23
08:35:39:setup_element:INFO: Eye window for uplink 24: _______XXXXXX___________________________
Data delay found: 29
08:35:39:setup_element:INFO: Eye window for uplink 25: __________XXXXX_________________________
Data delay found: 32
08:35:39:setup_element:INFO: Eye window for uplink 26: __________XXXXX_________________________
Data delay found: 32
08:35:39:setup_element:INFO: Eye window for uplink 27: ______________XXXXX_____________________
Data delay found: 36
08:35:39:setup_element:INFO: Eye window for uplink 28: _____________XXXXX______________________
Data delay found: 35
08:35:39:setup_element:INFO: Eye window for uplink 29: _______________XXXXXX___________________
Data delay found: 37
08:35:39:setup_element:INFO: Eye window for uplink 30: ________________XXXXXX__________________
Data delay found: 38
08:35:39:setup_element:INFO: Eye window for uplink 31: ________________XXXXXX__________________
Data delay found: 38
08:35:39:setup_element:INFO: Setting the data phase to 20 for uplink 16
08:35:39:setup_element:INFO: Setting the data phase to 18 for uplink 17
08:35:39:setup_element:INFO: Setting the data phase to 19 for uplink 18
08:35:39:setup_element:INFO: Setting the data phase to 17 for uplink 19
08:35:39:setup_element:INFO: Setting the data phase to 17 for uplink 20
08:35:39:setup_element:INFO: Setting the data phase to 16 for uplink 21
08:35:39:setup_element:INFO: Setting the data phase to 24 for uplink 22
08:35:39:setup_element:INFO: Setting the data phase to 23 for uplink 23
08:35:39:setup_element:INFO: Setting the data phase to 29 for uplink 24
08:35:39:setup_element:INFO: Setting the data phase to 32 for uplink 25
08:35:39:setup_element:INFO: Setting the data phase to 32 for uplink 26
08:35:39:setup_element:INFO: Setting the data phase to 36 for uplink 27
08:35:39:setup_element:INFO: Setting the data phase to 35 for uplink 28
08:35:39:setup_element:INFO: Setting the data phase to 37 for uplink 29
08:35:39:setup_element:INFO: Setting the data phase to 38 for uplink 30
08:35:39:setup_element:INFO: Setting the data phase to 38 for uplink 31
08:35:39:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 32
Window Length: 71
Eye Windows:
Uplink 16: ______________________________________________________________________XXXXXXX___
Uplink 17: ______________________________________________________________________XXXXXXX___
Uplink 18: _____________________________________________________________________XXXXXXXX___
Uplink 19: _____________________________________________________________________XXXXXXXX___
Uplink 20: ____________________________________________________________________XXXXXXXX____
Uplink 21: ____________________________________________________________________XXXXXXXX____
Uplink 22: _____________________________________________________________________XXXXXXXX___
Uplink 23: _____________________________________________________________________XXXXXXXX___
Uplink 24: ____________________________________________________________________XXXXXXX_____
Uplink 25: ____________________________________________________________________XXXXXXX_____
Uplink 26: ____________________________________________________________________XXXXXXXXX___
Uplink 27: ____________________________________________________________________XXXXXXXXX___
Uplink 28: ____________________________________________________________________XXXXXXXX____
Uplink 29: ____________________________________________________________________XXXXXXXX____
Uplink 30: ________________________________________________________________________________
Uplink 31: ________________________________________________________________________________
Data phase characteristics:
Uplink 16:
Optimal Phase: 20
Window Length: 35
Eye Window: XXX___________________________________XX
Uplink 17:
Optimal Phase: 18
Window Length: 34
Eye Window: XX__________________________________XXXX
Uplink 18:
Optimal Phase: 19
Window Length: 34
Eye Window: XXX__________________________________XXX
Uplink 19:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXXX
Uplink 20:
Optimal Phase: 17
Window Length: 35
Eye Window: ___________________________________XXXXX
Uplink 21:
Optimal Phase: 16
Window Length: 35
Eye Window: __________________________________XXXXX_
Uplink 22:
Optimal Phase: 24
Window Length: 25
Eye Window: XX_____XXXXX_________________________XXX
Uplink 23:
Optimal Phase: 23
Window Length: 23
Eye Window: XXXXXX_XXXXX_______________________XXXXX
Uplink 24:
Optimal Phase: 29
Window Length: 34
Eye Window: _______XXXXXX___________________________
Uplink 25:
Optimal Phase: 32
Window Length: 35
Eye Window: __________XXXXX_________________________
Uplink 26:
Optimal Phase: 32
Window Length: 35
Eye Window: __________XXXXX_________________________
Uplink 27:
Optimal Phase: 36
Window Length: 35
Eye Window: ______________XXXXX_____________________
Uplink 28:
Optimal Phase: 35
Window Length: 35
Eye Window: _____________XXXXX______________________
Uplink 29:
Optimal Phase: 37
Window Length: 34
Eye Window: _______________XXXXXX___________________
Uplink 30:
Optimal Phase: 38
Window Length: 34
Eye Window: ________________XXXXXX__________________
Uplink 31:
Optimal Phase: 38
Window Length: 34
Eye Window: ________________XXXXXX__________________
]
08:35:39:setup_element:INFO: Beginning SMX ASICs map scan
08:35:39:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
08:35:39:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
08:35:39:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
08:35:39:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
08:35:39:uplink:INFO: Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
08:35:39:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 23
08:35:39:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 22
08:35:40:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 30
08:35:40:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 31
08:35:40:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 21
08:35:40:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 20
08:35:40:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28
08:35:40:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 29
08:35:40:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 19
08:35:40:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 18
08:35:40:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26
08:35:40:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 27
08:35:40:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 17
08:35:40:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 16
08:35:41:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 24
08:35:41:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 25
08:35:42:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 23), (1, 22)
ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
ASIC address 0x2: (ASIC uplink, uplink): (0, 21), (1, 20)
ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
ASIC address 0x4: (ASIC uplink, uplink): (0, 19), (1, 18)
ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
ASIC address 0x6: (ASIC uplink, uplink): (0, 17), (1, 16)
ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
Clock Phase Characteristic:
Optimal Phase: 32
Window Length: 71
Eye Windows:
Uplink 16: ______________________________________________________________________XXXXXXX___
Uplink 17: ______________________________________________________________________XXXXXXX___
Uplink 18: _____________________________________________________________________XXXXXXXX___
Uplink 19: _____________________________________________________________________XXXXXXXX___
Uplink 20: ____________________________________________________________________XXXXXXXX____
Uplink 21: ____________________________________________________________________XXXXXXXX____
Uplink 22: _____________________________________________________________________XXXXXXXX___
Uplink 23: _____________________________________________________________________XXXXXXXX___
Uplink 24: ____________________________________________________________________XXXXXXX_____
Uplink 25: ____________________________________________________________________XXXXXXX_____
Uplink 26: ____________________________________________________________________XXXXXXXXX___
Uplink 27: ____________________________________________________________________XXXXXXXXX___
Uplink 28: ____________________________________________________________________XXXXXXXX____
Uplink 29: ____________________________________________________________________XXXXXXXX____
Uplink 30: ________________________________________________________________________________
Uplink 31: ________________________________________________________________________________
Data phase characteristics:
Uplink 16:
Optimal Phase: 20
Window Length: 35
Eye Window: XXX___________________________________XX
Uplink 17:
Optimal Phase: 18
Window Length: 34
Eye Window: XX__________________________________XXXX
Uplink 18:
Optimal Phase: 19
Window Length: 34
Eye Window: XXX__________________________________XXX
Uplink 19:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXXX
Uplink 20:
Optimal Phase: 17
Window Length: 35
Eye Window: ___________________________________XXXXX
Uplink 21:
Optimal Phase: 16
Window Length: 35
Eye Window: __________________________________XXXXX_
Uplink 22:
Optimal Phase: 24
Window Length: 25
Eye Window: XX_____XXXXX_________________________XXX
Uplink 23:
Optimal Phase: 23
Window Length: 23
Eye Window: XXXXXX_XXXXX_______________________XXXXX
Uplink 24:
Optimal Phase: 29
Window Length: 34
Eye Window: _______XXXXXX___________________________
Uplink 25:
Optimal Phase: 32
Window Length: 35
Eye Window: __________XXXXX_________________________
Uplink 26:
Optimal Phase: 32
Window Length: 35
Eye Window: __________XXXXX_________________________
Uplink 27:
Optimal Phase: 36
Window Length: 35
Eye Window: ______________XXXXX_____________________
Uplink 28:
Optimal Phase: 35
Window Length: 35
Eye Window: _____________XXXXX______________________
Uplink 29:
Optimal Phase: 37
Window Length: 34
Eye Window: _______________XXXXXX___________________
Uplink 30:
Optimal Phase: 38
Window Length: 34
Eye Window: ________________XXXXXX__________________
Uplink 31:
Optimal Phase: 38
Window Length: 34
Eye Window: ________________XXXXXX__________________
08:35:42:setup_element:INFO: Performing Elink synchronization
08:35:42:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
08:35:42:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
08:35:42:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
08:35:42:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
08:35:42:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2
08:35:42:uplink:INFO: Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
08:35:42:ST3_emu:INFO: Number of chips: 8
addr | upli | dwnli | grp | uplinks | uplinks_map
0 | [0] | 2 | 0 | [23] | [(0, 23), (1, 22)]
1 | [0] | 2 | 0 | [30] | [(0, 30), (1, 31)]
2 | [0] | 2 | 0 | [21] | [(0, 21), (1, 20)]
3 | [0] | 2 | 0 | [28] | [(0, 28), (1, 29)]
4 | [0] | 2 | 0 | [19] | [(0, 19), (1, 18)]
5 | [0] | 2 | 0 | [26] | [(0, 26), (1, 27)]
6 | [0] | 2 | 0 | [17] | [(0, 17), (1, 16)]
7 | [0] | 2 | 0 | [24] | [(0, 24), (1, 25)]
08:35:43:febtest:INFO: Init all SMX (CSA): 30
08:35:57:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
08:35:57:febtest:INFO: 23-00 | XA-000-08-002-002-006-092-00 | 44.1 | 1118.1
08:35:57:febtest:INFO: 30-01 | XA-000-08-002-000-007-005-06 | 15.6 | 1212.7
08:35:58:febtest:INFO: 21-02 | XA-000-08-002-002-008-174-15 | 28.2 | 1177.4
08:35:58:febtest:INFO: 28-03 | XA-000-08-002-000-007-025-01 | 25.1 | 1183.3
08:35:58:febtest:INFO: 19-04 | XA-000-08-002-002-006-068-07 | 34.6 | 1171.5
08:35:58:febtest:INFO: 26-05 | XA-000-08-002-002-006-074-07 | 12.4 | 1230.3
08:35:58:febtest:INFO: 17-06 | XA-000-08-002-002-006-075-07 | 34.6 | 1159.7
08:35:59:febtest:INFO: 24-07 | XA-000-08-002-002-006-098-09 | 34.6 | 1159.7
08:36:00:febtest:INFO: Set all CSA to ZERO
FEB type: B FEB_A: 0 FEB_B: 1
08:36:02:ST3_smx:INFO: chip: 23-0 44.073563 C 1124.048640 mV
08:36:02:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:36:02:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:36:02:ST3_smx:INFO: Electrons
08:36:02:ST3_smx:INFO: # loops 0
08:36:03:ST3_smx:INFO: # loops 1
08:36:05:ST3_smx:INFO: # loops 2
08:36:07:ST3_smx:INFO: # loops 3
08:36:08:ST3_smx:INFO: # loops 4
08:36:10:ST3_smx:INFO: Total # of broken channels: 0
08:36:10:ST3_smx:INFO: List of broken channels: []
08:36:10:ST3_smx:INFO: Total # of broken channels: 0
08:36:10:ST3_smx:INFO: List of broken channels: []
08:36:12:ST3_smx:INFO: chip: 30-1 18.745682 C 1212.728715 mV
08:36:12:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:36:12:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:36:12:ST3_smx:INFO: Electrons
08:36:12:ST3_smx:INFO: # loops 0
08:36:13:ST3_smx:INFO: # loops 1
08:36:15:ST3_smx:INFO: # loops 2
08:36:17:ST3_smx:INFO: # loops 3
08:36:18:ST3_smx:INFO: # loops 4
08:36:20:ST3_smx:INFO: Total # of broken channels: 0
08:36:20:ST3_smx:INFO: List of broken channels: []
08:36:20:ST3_smx:INFO: Total # of broken channels: 1
08:36:20:ST3_smx:INFO: List of broken channels: [0]
08:36:22:ST3_smx:INFO: chip: 21-2 31.389742 C 1177.390875 mV
08:36:22:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:36:22:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:36:22:ST3_smx:INFO: Electrons
08:36:22:ST3_smx:INFO: # loops 0
08:36:23:ST3_smx:INFO: # loops 1
08:36:25:ST3_smx:INFO: # loops 2
08:36:27:ST3_smx:INFO: # loops 3
08:36:28:ST3_smx:INFO: # loops 4
08:36:30:ST3_smx:INFO: Total # of broken channels: 0
08:36:30:ST3_smx:INFO: List of broken channels: []
08:36:30:ST3_smx:INFO: Total # of broken channels: 0
08:36:30:ST3_smx:INFO: List of broken channels: []
08:36:32:ST3_smx:INFO: chip: 28-3 28.225000 C 1183.292940 mV
08:36:32:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:36:32:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:36:32:ST3_smx:INFO: Electrons
08:36:32:ST3_smx:INFO: # loops 0
08:36:33:ST3_smx:INFO: # loops 1
08:36:35:ST3_smx:INFO: # loops 2
08:36:37:ST3_smx:INFO: # loops 3
08:36:38:ST3_smx:INFO: # loops 4
08:36:40:ST3_smx:INFO: Total # of broken channels: 0
08:36:40:ST3_smx:INFO: List of broken channels: []
08:36:40:ST3_smx:INFO: Total # of broken channels: 1
08:36:40:ST3_smx:INFO: List of broken channels: [88]
08:36:42:ST3_smx:INFO: chip: 19-4 34.556970 C 1171.483840 mV
08:36:42:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:36:42:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:36:42:ST3_smx:INFO: Electrons
08:36:42:ST3_smx:INFO: # loops 0
08:36:43:ST3_smx:INFO: # loops 1
08:36:45:ST3_smx:INFO: # loops 2
08:36:46:ST3_smx:INFO: # loops 3
08:36:48:ST3_smx:INFO: # loops 4
08:36:50:ST3_smx:INFO: Total # of broken channels: 3
08:36:50:ST3_smx:INFO: List of broken channels: [61, 76, 126]
08:36:50:ST3_smx:INFO: Total # of broken channels: 4
08:36:50:ST3_smx:INFO: List of broken channels: [61, 74, 76, 126]
08:36:51:ST3_smx:INFO: chip: 26-5 15.590880 C 1236.187875 mV
08:36:51:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:36:51:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:36:51:ST3_smx:INFO: Electrons
08:36:51:ST3_smx:INFO: # loops 0
08:36:53:ST3_smx:INFO: # loops 1
08:36:55:ST3_smx:INFO: # loops 2
08:36:56:ST3_smx:INFO: # loops 3
08:36:58:ST3_smx:INFO: # loops 4
08:36:59:ST3_smx:INFO: Total # of broken channels: 0
08:36:59:ST3_smx:INFO: List of broken channels: []
08:36:59:ST3_smx:INFO: Total # of broken channels: 0
08:36:59:ST3_smx:INFO: List of broken channels: []
08:37:01:ST3_smx:INFO: chip: 17-6 37.726682 C 1165.571835 mV
08:37:01:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:37:01:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:37:01:ST3_smx:INFO: Electrons
08:37:01:ST3_smx:INFO: # loops 0
08:37:03:ST3_smx:INFO: # loops 1
08:37:04:ST3_smx:INFO: # loops 2
08:37:06:ST3_smx:INFO: # loops 3
08:37:08:ST3_smx:INFO: # loops 4
08:37:09:ST3_smx:INFO: Total # of broken channels: 0
08:37:09:ST3_smx:INFO: List of broken channels: []
08:37:09:ST3_smx:INFO: Total # of broken channels: 0
08:37:09:ST3_smx:INFO: List of broken channels: []
08:37:11:ST3_smx:INFO: chip: 24-7 37.726682 C 1165.571835 mV
08:37:11:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:37:11:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:37:11:ST3_smx:INFO: Electrons
08:37:11:ST3_smx:INFO: # loops 0
08:37:13:ST3_smx:INFO: # loops 1
08:37:14:ST3_smx:INFO: # loops 2
08:37:16:ST3_smx:INFO: # loops 3
08:37:17:ST3_smx:INFO: # loops 4
08:37:19:ST3_smx:INFO: Total # of broken channels: 0
08:37:19:ST3_smx:INFO: List of broken channels: []
08:37:19:ST3_smx:INFO: Total # of broken channels: 1
08:37:19:ST3_smx:INFO: List of broken channels: [124]
08:37:19:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
08:37:20:febtest:INFO: 23-00 | XA-000-08-002-002-006-092-00 | 47.3 | 1141.9
08:37:20:febtest:INFO: 30-01 | XA-000-08-002-000-007-005-06 | 21.9 | 1242.0
08:37:20:febtest:INFO: 21-02 | XA-000-08-002-002-008-174-15 | 34.6 | 1195.1
08:37:20:febtest:INFO: 28-03 | XA-000-08-002-000-007-025-01 | 31.4 | 1206.9
08:37:20:febtest:INFO: 19-04 | XA-000-08-002-002-006-068-07 | 37.7 | 1189.2
08:37:21:febtest:INFO: 26-05 | XA-000-08-002-002-006-074-07 | 15.6 | 1259.6
08:37:21:febtest:INFO: 17-06 | XA-000-08-002-002-006-075-07 | 40.9 | 1177.4
08:37:21:febtest:INFO: 24-07 | XA-000-08-002-002-006-098-09 | 40.9 | 1183.3
############################################################
# S U M M A R Y #
############################################################
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-Sensor
TEST_DATE : 24_06_05-08_35_28
OPERATOR : Alois Alzheimer
SITE : GSI | SETUP : GSI_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 2158| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_B
------------------------------------------------------------
SENSOR_ID: 23094
MODULE_NAME: L4DL000161 M4DL0T3001613A2 124 C
MODULE_TYPE:
MODULE_LADDER:
MODULE_MODULE:
MODULE_SIZE: 0
MODULE_GRADE:
------------------------------------------------------------
VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '2.0090', '1.851', '2.0980']
VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '2.0320', '1.850', '2.5760']
VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.9710', '1.850', '0.5286']