12:46:39:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
12:46:39:ST3_Shared:INFO:	                         FEB-Sensor                         
12:46:39:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
12:46:56:ST3_ModuleSelector:INFO:	New Sensor ID: 2621
12:46:56:ST3_ModuleSelector:INFO:	New Sensor ID: 26214
12:46:59:ST3_ModuleSelector:INFO:	L7DL300122 M7DL3T2001222A2 124 B

12:46:59:ST3_ModuleSelector:INFO:	26214
12:46:59:febtest:INFO:	Testing FEB with SN 2171
12:47:00:smx_tester:INFO:	Scanning setup
12:47:00:elinks:INFO:	Disabling clock on downlink 0
12:47:00:elinks:INFO:	Disabling clock on downlink 1
12:47:00:elinks:INFO:	Disabling clock on downlink 2
12:47:00:elinks:INFO:	Disabling clock on downlink 3
12:47:00:elinks:INFO:	Disabling clock on downlink 4
12:47:00:setup_element:INFO:	Checking SOS, encoding_mode: SOS
12:47:00:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
12:47:00:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
12:47:00:elinks:INFO:	Disabling clock on downlink 0
12:47:00:elinks:INFO:	Disabling clock on downlink 1
12:47:00:elinks:INFO:	Disabling clock on downlink 2
12:47:00:elinks:INFO:	Disabling clock on downlink 3
12:47:00:elinks:INFO:	Disabling clock on downlink 4
12:47:00:setup_element:INFO:	Checking SOS, encoding_mode: SOS
12:47:00:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
12:47:00:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
12:47:00:elinks:INFO:	Disabling clock on downlink 0
12:47:00:elinks:INFO:	Disabling clock on downlink 1
12:47:01:elinks:INFO:	Disabling clock on downlink 2
12:47:01:elinks:INFO:	Disabling clock on downlink 3
12:47:01:elinks:INFO:	Disabling clock on downlink 4
12:47:01:setup_element:INFO:	Checking SOS, encoding_mode: SOS
12:47:01:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
12:47:01:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 16
12:47:01:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 17
12:47:01:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 18
12:47:01:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 19
12:47:01:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 20
12:47:01:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 21
12:47:01:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 22
12:47:01:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 23
12:47:01:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 24
12:47:01:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 25
12:47:01:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 26
12:47:01:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 27
12:47:01:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 28
12:47:01:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 29
12:47:01:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 30
12:47:01:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 31
12:47:01:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
12:47:01:elinks:INFO:	Disabling clock on downlink 0
12:47:01:elinks:INFO:	Disabling clock on downlink 1
12:47:01:elinks:INFO:	Disabling clock on downlink 2
12:47:01:elinks:INFO:	Disabling clock on downlink 3
12:47:01:elinks:INFO:	Disabling clock on downlink 4
12:47:01:setup_element:INFO:	Checking SOS, encoding_mode: SOS
12:47:01:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
12:47:01:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
12:47:01:elinks:INFO:	Disabling clock on downlink 0
12:47:01:elinks:INFO:	Disabling clock on downlink 1
12:47:01:elinks:INFO:	Disabling clock on downlink 2
12:47:01:elinks:INFO:	Disabling clock on downlink 3
12:47:01:elinks:INFO:	Disabling clock on downlink 4
12:47:01:setup_element:INFO:	Checking SOS, encoding_mode: SOS
12:47:01:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [4]
12:47:01:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
12:47:01:setup_element:INFO:	Scanning clock phase
12:47:01:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
12:47:01:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
12:47:01:setup_element:INFO:	Clock phase scan results for group 0, downlink 2
12:47:01:setup_element:INFO:	Eye window for uplink 16: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
12:47:01:setup_element:INFO:	Eye window for uplink 17: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
12:47:01:setup_element:INFO:	Eye window for uplink 18: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
12:47:01:setup_element:INFO:	Eye window for uplink 19: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
12:47:01:setup_element:INFO:	Eye window for uplink 20: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
12:47:01:setup_element:INFO:	Eye window for uplink 21: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
12:47:01:setup_element:INFO:	Eye window for uplink 22: ________________________________________________________________________________
Clock Delay: 40
12:47:01:setup_element:INFO:	Eye window for uplink 23: ________________________________________________________________________________
Clock Delay: 40
12:47:01:setup_element:INFO:	Eye window for uplink 24: _____________________________________________________________________XXXXXXXXX__
Clock Delay: 33
12:47:01:setup_element:INFO:	Eye window for uplink 25: _____________________________________________________________________XXXXXXXXX__
Clock Delay: 33
12:47:01:setup_element:INFO:	Eye window for uplink 26: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
12:47:01:setup_element:INFO:	Eye window for uplink 27: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
12:47:01:setup_element:INFO:	Eye window for uplink 28: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
12:47:01:setup_element:INFO:	Eye window for uplink 29: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
12:47:01:setup_element:INFO:	Eye window for uplink 30: _______________________________________________________________________XXXXXXXXX
Clock Delay: 35
12:47:01:setup_element:INFO:	Eye window for uplink 31: _______________________________________________________________________XXXXXXXXX
Clock Delay: 35
12:47:01:setup_element:INFO:	Setting the clock phase to 33 for group 0, downlink 2
12:47:01:setup_element:INFO:	Scanning data phases
12:47:01:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
12:47:02:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
12:47:07:setup_element:INFO:	Data phase scan results for group 0, downlink 2
12:47:07:setup_element:INFO:	Eye window for uplink 16: XXX___________________________________XX
Data delay found: 20
12:47:07:setup_element:INFO:	Eye window for uplink 17: XX__________________________________XXXX
Data delay found: 18
12:47:07:setup_element:INFO:	Eye window for uplink 18: X__________________________________XXXXX
Data delay found: 17
12:47:07:setup_element:INFO:	Eye window for uplink 19: _________________________________XXXXX__
Data delay found: 15
12:47:07:setup_element:INFO:	Eye window for uplink 20: X_____________________________________XX
Data delay found: 19
12:47:07:setup_element:INFO:	Eye window for uplink 21: X___________________________________XXXX
Data delay found: 18
12:47:07:setup_element:INFO:	Eye window for uplink 22: XXX__________________________________XXX
Data delay found: 19
12:47:07:setup_element:INFO:	Eye window for uplink 23: XXXXXX_____________________________XXXXX
Data delay found: 20
12:47:07:setup_element:INFO:	Eye window for uplink 24: _________XXXXXX_________________________
Data delay found: 31
12:47:07:setup_element:INFO:	Eye window for uplink 25: __________XXXXXXX_______________________
Data delay found: 33
12:47:07:setup_element:INFO:	Eye window for uplink 26: _________XXXXX__________________________
Data delay found: 31
12:47:07:setup_element:INFO:	Eye window for uplink 27: ____________XXXXXX______________________
Data delay found: 34
12:47:07:setup_element:INFO:	Eye window for uplink 28: __________________XXXX__________________
Data delay found: 39
12:47:07:setup_element:INFO:	Eye window for uplink 29: ____________________XXXXX_______________
Data delay found: 2
12:47:07:setup_element:INFO:	Eye window for uplink 30: ___________________XXXXXX_______________
Data delay found: 1
12:47:07:setup_element:INFO:	Eye window for uplink 31: __________________XXXXXXX_______________
Data delay found: 1
12:47:07:setup_element:INFO:	Setting the data phase to 20 for uplink 16
12:47:07:setup_element:INFO:	Setting the data phase to 18 for uplink 17
12:47:07:setup_element:INFO:	Setting the data phase to 17 for uplink 18
12:47:07:setup_element:INFO:	Setting the data phase to 15 for uplink 19
12:47:07:setup_element:INFO:	Setting the data phase to 19 for uplink 20
12:47:07:setup_element:INFO:	Setting the data phase to 18 for uplink 21
12:47:07:setup_element:INFO:	Setting the data phase to 19 for uplink 22
12:47:07:setup_element:INFO:	Setting the data phase to 20 for uplink 23
12:47:07:setup_element:INFO:	Setting the data phase to 31 for uplink 24
12:47:07:setup_element:INFO:	Setting the data phase to 33 for uplink 25
12:47:07:setup_element:INFO:	Setting the data phase to 31 for uplink 26
12:47:07:setup_element:INFO:	Setting the data phase to 34 for uplink 27
12:47:07:setup_element:INFO:	Setting the data phase to 39 for uplink 28
12:47:07:setup_element:INFO:	Setting the data phase to 2 for uplink 29
12:47:07:setup_element:INFO:	Setting the data phase to 1 for uplink 30
12:47:07:setup_element:INFO:	Setting the data phase to 1 for uplink 31
12:47:07:ST3_emu:ERROR:	[
Setup Element:
  Group: 0
  Downlink: 2
  Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
  ASICs Map: None
  Clock Phase Characteristic:
    Optimal Phase: 33
    Window Length: 68
    Eye Windows:
      Uplink 16: ______________________________________________________________________XXXXXXXX__
      Uplink 17: ______________________________________________________________________XXXXXXXX__
      Uplink 18: ____________________________________________________________________XXXXXXXX____
      Uplink 19: ____________________________________________________________________XXXXXXXX____
      Uplink 20: _____________________________________________________________________XXXXXXXX___
      Uplink 21: _____________________________________________________________________XXXXXXXX___
      Uplink 22: ________________________________________________________________________________
      Uplink 23: ________________________________________________________________________________
      Uplink 24: _____________________________________________________________________XXXXXXXXX__
      Uplink 25: _____________________________________________________________________XXXXXXXXX__
      Uplink 26: _____________________________________________________________________XXXXXXXX___
      Uplink 27: _____________________________________________________________________XXXXXXXX___
      Uplink 28: _______________________________________________________________________XXXXXXX__
      Uplink 29: _______________________________________________________________________XXXXXXX__
      Uplink 30: _______________________________________________________________________XXXXXXXXX
      Uplink 31: _______________________________________________________________________XXXXXXXXX
  Data phase characteristics:
    Uplink 16:
      Optimal Phase: 20
      Window Length: 35
      Eye Window: XXX___________________________________XX
    Uplink 17:
      Optimal Phase: 18
      Window Length: 34
      Eye Window: XX__________________________________XXXX
    Uplink 18:
      Optimal Phase: 17
      Window Length: 34
      Eye Window: X__________________________________XXXXX
    Uplink 19:
      Optimal Phase: 15
      Window Length: 35
      Eye Window: _________________________________XXXXX__
    Uplink 20:
      Optimal Phase: 19
      Window Length: 37
      Eye Window: X_____________________________________XX
    Uplink 21:
      Optimal Phase: 18
      Window Length: 35
      Eye Window: X___________________________________XXXX
    Uplink 22:
      Optimal Phase: 19
      Window Length: 34
      Eye Window: XXX__________________________________XXX
    Uplink 23:
      Optimal Phase: 20
      Window Length: 29
      Eye Window: XXXXXX_____________________________XXXXX
    Uplink 24:
      Optimal Phase: 31
      Window Length: 34
      Eye Window: _________XXXXXX_________________________
    Uplink 25:
      Optimal Phase: 33
      Window Length: 33
      Eye Window: __________XXXXXXX_______________________
    Uplink 26:
      Optimal Phase: 31
      Window Length: 35
      Eye Window: _________XXXXX__________________________
    Uplink 27:
      Optimal Phase: 34
      Window Length: 34
      Eye Window: ____________XXXXXX______________________
    Uplink 28:
      Optimal Phase: 39
      Window Length: 36
      Eye Window: __________________XXXX__________________
    Uplink 29:
      Optimal Phase: 2
      Window Length: 35
      Eye Window: ____________________XXXXX_______________
    Uplink 30:
      Optimal Phase: 1
      Window Length: 34
      Eye Window: ___________________XXXXXX_______________
    Uplink 31:
      Optimal Phase: 1
      Window Length: 33
      Eye Window: __________________XXXXXXX_______________
]
12:47:07:setup_element:INFO:	Beginning SMX ASICs map scan
12:47:07:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
12:47:07:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
12:47:07:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
12:47:07:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
12:47:07:uplink:INFO:	Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
12:47:07:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 0, uplink 23
12:47:07:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 1, uplink 22
12:47:07:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 0, uplink 30
12:47:07:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 1, uplink 31
12:47:07:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 0, uplink 21
12:47:07:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 1, uplink 20
12:47:08:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 0, uplink 28
12:47:08:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 1, uplink 29
12:47:08:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 0, uplink 19
12:47:08:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 1, uplink 18
12:47:08:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 0, uplink 26
12:47:08:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 1, uplink 27
12:47:08:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 0, uplink 17
12:47:08:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 1, uplink 16
12:47:08:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 0, uplink 24
12:47:08:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 1, uplink 25
12:47:10:ST3_emu:ERROR:	
Setup Element:
  Group: 0
  Downlink: 2
  Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
  ASICs Map:
    ASIC address 0x0: (ASIC uplink, uplink): (0, 23), (1, 22)
    ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
    ASIC address 0x2: (ASIC uplink, uplink): (0, 21), (1, 20)
    ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
    ASIC address 0x4: (ASIC uplink, uplink): (0, 19), (1, 18)
    ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
    ASIC address 0x6: (ASIC uplink, uplink): (0, 17), (1, 16)
    ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
  Clock Phase Characteristic:
    Optimal Phase: 33
    Window Length: 68
    Eye Windows:
      Uplink 16: ______________________________________________________________________XXXXXXXX__
      Uplink 17: ______________________________________________________________________XXXXXXXX__
      Uplink 18: ____________________________________________________________________XXXXXXXX____
      Uplink 19: ____________________________________________________________________XXXXXXXX____
      Uplink 20: _____________________________________________________________________XXXXXXXX___
      Uplink 21: _____________________________________________________________________XXXXXXXX___
      Uplink 22: ________________________________________________________________________________
      Uplink 23: ________________________________________________________________________________
      Uplink 24: _____________________________________________________________________XXXXXXXXX__
      Uplink 25: _____________________________________________________________________XXXXXXXXX__
      Uplink 26: _____________________________________________________________________XXXXXXXX___
      Uplink 27: _____________________________________________________________________XXXXXXXX___
      Uplink 28: _______________________________________________________________________XXXXXXX__
      Uplink 29: _______________________________________________________________________XXXXXXX__
      Uplink 30: _______________________________________________________________________XXXXXXXXX
      Uplink 31: _______________________________________________________________________XXXXXXXXX
  Data phase characteristics:
    Uplink 16:
      Optimal Phase: 20
      Window Length: 35
      Eye Window: XXX___________________________________XX
    Uplink 17:
      Optimal Phase: 18
      Window Length: 34
      Eye Window: XX__________________________________XXXX
    Uplink 18:
      Optimal Phase: 17
      Window Length: 34
      Eye Window: X__________________________________XXXXX
    Uplink 19:
      Optimal Phase: 15
      Window Length: 35
      Eye Window: _________________________________XXXXX__
    Uplink 20:
      Optimal Phase: 19
      Window Length: 37
      Eye Window: X_____________________________________XX
    Uplink 21:
      Optimal Phase: 18
      Window Length: 35
      Eye Window: X___________________________________XXXX
    Uplink 22:
      Optimal Phase: 19
      Window Length: 34
      Eye Window: XXX__________________________________XXX
    Uplink 23:
      Optimal Phase: 20
      Window Length: 29
      Eye Window: XXXXXX_____________________________XXXXX
    Uplink 24:
      Optimal Phase: 31
      Window Length: 34
      Eye Window: _________XXXXXX_________________________
    Uplink 25:
      Optimal Phase: 33
      Window Length: 33
      Eye Window: __________XXXXXXX_______________________
    Uplink 26:
      Optimal Phase: 31
      Window Length: 35
      Eye Window: _________XXXXX__________________________
    Uplink 27:
      Optimal Phase: 34
      Window Length: 34
      Eye Window: ____________XXXXXX______________________
    Uplink 28:
      Optimal Phase: 39
      Window Length: 36
      Eye Window: __________________XXXX__________________
    Uplink 29:
      Optimal Phase: 2
      Window Length: 35
      Eye Window: ____________________XXXXX_______________
    Uplink 30:
      Optimal Phase: 1
      Window Length: 34
      Eye Window: ___________________XXXXXX_______________
    Uplink 31:
      Optimal Phase: 1
      Window Length: 33
      Eye Window: __________________XXXXXXX_______________

12:47:10:setup_element:INFO:	Performing Elink synchronization
12:47:10:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
12:47:10:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
12:47:10:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
12:47:10:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
12:47:10:setup_element:INFO:	Writing SMX Elink masks for group 0, downlink 2
12:47:10:uplink:INFO:	Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
12:47:10:ST3_emu:INFO:	Number of chips: 8
addr  |  upli  |  dwnli  |  grp |  uplinks | uplinks_map
   0  |   [0]   |  2  |  0  |     [23]     |  [(0, 23), (1, 22)]
   1  |   [0]   |  2  |  0  |     [30]     |  [(0, 30), (1, 31)]
   2  |   [0]   |  2  |  0  |     [21]     |  [(0, 21), (1, 20)]
   3  |   [0]   |  2  |  0  |     [28]     |  [(0, 28), (1, 29)]
   4  |   [0]   |  2  |  0  |     [19]     |  [(0, 19), (1, 18)]
   5  |   [0]   |  2  |  0  |     [26]     |  [(0, 26), (1, 27)]
   6  |   [0]   |  2  |  0  |     [17]     |  [(0, 17), (1, 16)]
   7  |   [0]   |  2  |  0  |     [24]     |  [(0, 24), (1, 25)]
12:47:11:febtest:INFO:	Init all SMX (CSA): 30
12:47:25:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
12:47:25:febtest:INFO:	23-00 | XA-000-08-002-002-008-138-01 |  25.1 | 1159.7
12:47:25:febtest:INFO:	30-01 | XA-000-08-002-002-008-141-01 |  31.4 | 1147.8
12:47:26:febtest:INFO:	21-02 | XA-000-08-002-002-008-122-07 |  21.9 | 1189.2
12:47:26:febtest:INFO:	28-03 | XA-000-08-002-002-008-140-01 |  28.2 | 1147.8
12:47:26:febtest:INFO:	19-04 | XA-000-08-002-002-008-120-07 |  28.2 | 1165.6
12:47:26:febtest:INFO:	26-05 | XA-000-08-002-002-008-136-01 |  25.1 | 1153.7
12:47:26:febtest:INFO:	17-06 | XA-000-08-002-002-008-121-07 |  31.4 | 1159.7
12:47:27:febtest:INFO:	24-07 | XA-000-08-002-002-008-137-01 |  28.2 | 1147.8
12:47:28:febtest:INFO:	Set all CSA to ZERO
FEB type: B FEB_A: 0 FEB_B: 1
12:47:30:ST3_smx:INFO:	chip: 23-0 	 28.225000 C 	 1171.483840 mV
12:47:30:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
12:47:30:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
12:47:30:ST3_smx:INFO:		Electrons
12:47:30:ST3_smx:INFO:	# loops 0
12:47:31:ST3_smx:INFO:	# loops 1
12:47:33:ST3_smx:INFO:	# loops 2
12:47:35:ST3_smx:INFO:	# loops 3
12:47:36:ST3_smx:INFO:	# loops 4
12:47:38:ST3_smx:INFO:	Total # of broken channels: 0
12:47:38:ST3_smx:INFO:	List of broken channels: []
12:47:38:ST3_smx:INFO:	Total # of broken channels: 0
12:47:38:ST3_smx:INFO:	List of broken channels: []
12:47:40:ST3_smx:INFO:	chip: 30-1 	 31.389742 C 	 1159.654860 mV
12:47:40:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
12:47:40:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
12:47:40:ST3_smx:INFO:		Electrons
12:47:40:ST3_smx:INFO:	# loops 0
12:47:41:ST3_smx:INFO:	# loops 1
12:47:43:ST3_smx:INFO:	# loops 2
12:47:45:ST3_smx:INFO:	# loops 3
12:47:46:ST3_smx:INFO:	# loops 4
12:47:48:ST3_smx:INFO:	Total # of broken channels: 0
12:47:48:ST3_smx:INFO:	List of broken channels: []
12:47:48:ST3_smx:INFO:	Total # of broken channels: 0
12:47:48:ST3_smx:INFO:	List of broken channels: []
12:47:50:ST3_smx:INFO:	chip: 21-2 	 21.902970 C 	 1200.969315 mV
12:47:50:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
12:47:50:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
12:47:50:ST3_smx:INFO:		Electrons
12:47:50:ST3_smx:INFO:	# loops 0
12:47:52:ST3_smx:INFO:	# loops 1
12:47:53:ST3_smx:INFO:	# loops 2
12:47:55:ST3_smx:INFO:	# loops 3
12:47:56:ST3_smx:INFO:	# loops 4
12:47:58:ST3_smx:INFO:	Total # of broken channels: 0
12:47:58:ST3_smx:INFO:	List of broken channels: []
12:47:58:ST3_smx:INFO:	Total # of broken channels: 0
12:47:58:ST3_smx:INFO:	List of broken channels: []
12:48:00:ST3_smx:INFO:	chip: 28-3 	 31.389742 C 	 1159.654860 mV
12:48:00:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
12:48:00:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
12:48:00:ST3_smx:INFO:		Electrons
12:48:00:ST3_smx:INFO:	# loops 0
12:48:02:ST3_smx:INFO:	# loops 1
12:48:03:ST3_smx:INFO:	# loops 2
12:48:05:ST3_smx:INFO:	# loops 3
12:48:07:ST3_smx:INFO:	# loops 4
12:48:08:ST3_smx:INFO:	Total # of broken channels: 0
12:48:08:ST3_smx:INFO:	List of broken channels: []
12:48:08:ST3_smx:INFO:	Total # of broken channels: 0
12:48:08:ST3_smx:INFO:	List of broken channels: []
12:48:10:ST3_smx:INFO:	chip: 19-4 	 28.225000 C 	 1171.483840 mV
12:48:10:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
12:48:10:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
12:48:10:ST3_smx:INFO:		Electrons
12:48:10:ST3_smx:INFO:	# loops 0
12:48:12:ST3_smx:INFO:	# loops 1
12:48:13:ST3_smx:INFO:	# loops 2
12:48:15:ST3_smx:INFO:	# loops 3
12:48:17:ST3_smx:INFO:	# loops 4
12:48:18:ST3_smx:INFO:	Total # of broken channels: 0
12:48:18:ST3_smx:INFO:	List of broken channels: []
12:48:18:ST3_smx:INFO:	Total # of broken channels: 1
12:48:18:ST3_smx:INFO:	List of broken channels: [67]
12:48:20:ST3_smx:INFO:	chip: 26-5 	 25.062742 C 	 1165.571835 mV
12:48:20:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
12:48:20:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
12:48:20:ST3_smx:INFO:		Electrons
12:48:20:ST3_smx:INFO:	# loops 0
12:48:22:ST3_smx:INFO:	# loops 1
12:48:23:ST3_smx:INFO:	# loops 2
12:48:25:ST3_smx:INFO:	# loops 3
12:48:27:ST3_smx:INFO:	# loops 4
12:48:28:ST3_smx:INFO:	Total # of broken channels: 0
12:48:28:ST3_smx:INFO:	List of broken channels: []
12:48:28:ST3_smx:INFO:	Total # of broken channels: 0
12:48:28:ST3_smx:INFO:	List of broken channels: []
12:48:30:ST3_smx:INFO:	chip: 17-6 	 34.556970 C 	 1165.571835 mV
12:48:30:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
12:48:30:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
12:48:30:ST3_smx:INFO:		Electrons
12:48:30:ST3_smx:INFO:	# loops 0
12:48:32:ST3_smx:INFO:	# loops 1
12:48:33:ST3_smx:INFO:	# loops 2
12:48:35:ST3_smx:INFO:	# loops 3
12:48:37:ST3_smx:INFO:	# loops 4
12:48:38:ST3_smx:INFO:	Total # of broken channels: 0
12:48:38:ST3_smx:INFO:	List of broken channels: []
12:48:38:ST3_smx:INFO:	Total # of broken channels: 0
12:48:38:ST3_smx:INFO:	List of broken channels: []
12:48:40:ST3_smx:INFO:	chip: 24-7 	 31.389742 C 	 1153.732915 mV
12:48:40:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
12:48:40:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
12:48:40:ST3_smx:INFO:		Electrons
12:48:40:ST3_smx:INFO:	# loops 0
12:48:42:ST3_smx:INFO:	# loops 1
12:48:43:ST3_smx:INFO:	# loops 2
12:48:45:ST3_smx:INFO:	# loops 3
12:48:46:ST3_smx:INFO:	# loops 4
12:48:48:ST3_smx:INFO:	Total # of broken channels: 0
12:48:48:ST3_smx:INFO:	List of broken channels: []
12:48:48:ST3_smx:INFO:	Total # of broken channels: 0
12:48:48:ST3_smx:INFO:	List of broken channels: []
12:48:48:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
12:48:49:febtest:INFO:	23-00 | XA-000-08-002-002-008-138-01 |  31.4 | 1189.2
12:48:49:febtest:INFO:	30-01 | XA-000-08-002-002-008-141-01 |  34.6 | 1183.3
12:48:49:febtest:INFO:	21-02 | XA-000-08-002-002-008-122-07 |  25.1 | 1218.6
12:48:49:febtest:INFO:	28-03 | XA-000-08-002-002-008-140-01 |  31.4 | 1183.3
12:48:50:febtest:INFO:	19-04 | XA-000-08-002-002-008-120-07 |  31.4 | 1189.2
12:48:50:febtest:INFO:	26-05 | XA-000-08-002-002-008-136-01 |  28.2 | 1183.3
12:48:50:febtest:INFO:	17-06 | XA-000-08-002-002-008-121-07 |  34.6 | 1183.3
12:48:50:febtest:INFO:	24-07 | XA-000-08-002-002-008-137-01 |  31.4 | 1171.5
############################################################
#                   S U M M A R Y                          #
############################################################
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

############################################################
#                   S U M M A R Y                          #
############################################################
TEST_NAME : FEB-Sensor
TEST_DATE : 24_05_29-12_46_39
OPERATOR  : Alois Alzheimer
SITE : GSI | SETUP : GSI_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 2171| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_B
------------------------------------------------------------
SENSOR_ID:	26214
MODULE_NAME:	L7DL300122 M7DL3T2001222A2 124 B

MODULE_TYPE:	
MODULE_LADDER:	
MODULE_MODULE:	
MODULE_SIZE:	0
MODULE_GRADE:	
------------------------------------------------------------
VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '2.0040', '1.852', '2.1120']
VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '2.0510', '1.849', '2.5760']
VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.9740', '1.850', '0.5207']