
FEB_2174 28.05.24 13:13:46
TextEdit.txt
13:13:46:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo 13:13:46:ST3_Shared:INFO: FEB-Microcable 13:13:46:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo 13:13:46:febtest:INFO: Testing FEB with SN 2174 13:13:48:smx_tester:INFO: Scanning setup 13:13:48:elinks:INFO: Disabling clock on downlink 0 13:13:48:elinks:INFO: Disabling clock on downlink 1 13:13:48:elinks:INFO: Disabling clock on downlink 2 13:13:48:elinks:INFO: Disabling clock on downlink 3 13:13:48:elinks:INFO: Disabling clock on downlink 4 13:13:48:setup_element:INFO: Checking SOS, encoding_mode: SOS 13:13:48:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0] 13:13:48:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection 13:13:48:elinks:INFO: Disabling clock on downlink 0 13:13:48:elinks:INFO: Disabling clock on downlink 1 13:13:48:elinks:INFO: Disabling clock on downlink 2 13:13:48:elinks:INFO: Disabling clock on downlink 3 13:13:48:elinks:INFO: Disabling clock on downlink 4 13:13:48:setup_element:INFO: Checking SOS, encoding_mode: SOS 13:13:48:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1] 13:13:48:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection 13:13:48:elinks:INFO: Disabling clock on downlink 0 13:13:48:elinks:INFO: Disabling clock on downlink 1 13:13:48:elinks:INFO: Disabling clock on downlink 2 13:13:48:elinks:INFO: Disabling clock on downlink 3 13:13:48:elinks:INFO: Disabling clock on downlink 4 13:13:48:setup_element:INFO: Checking SOS, encoding_mode: SOS 13:13:48:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2] 13:13:48:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 16 13:13:48:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 17 13:13:48:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 18 13:13:48:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 19 13:13:48:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 20 13:13:48:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 21 13:13:48:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 22 13:13:48:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 23 13:13:48:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24 13:13:48:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25 13:13:48:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26 13:13:48:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27 13:13:48:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28 13:13:48:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29 13:13:48:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30 13:13:48:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31 13:13:48:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection 13:13:48:elinks:INFO: Disabling clock on downlink 0 13:13:48:elinks:INFO: Disabling clock on downlink 1 13:13:48:elinks:INFO: Disabling clock on downlink 2 13:13:48:elinks:INFO: Disabling clock on downlink 3 13:13:48:elinks:INFO: Disabling clock on downlink 4 13:13:48:setup_element:INFO: Checking SOS, encoding_mode: SOS 13:13:48:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3] 13:13:48:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection 13:13:48:elinks:INFO: Disabling clock on downlink 0 13:13:48:elinks:INFO: Disabling clock on downlink 1 13:13:48:elinks:INFO: Disabling clock on downlink 2 13:13:49:elinks:INFO: Disabling clock on downlink 3 13:13:49:elinks:INFO: Disabling clock on downlink 4 13:13:49:setup_element:INFO: Checking SOS, encoding_mode: SOS 13:13:49:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4] 13:13:49:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection 13:13:49:setup_element:INFO: Scanning clock phase 13:13:49:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2] 13:13:49:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2] 13:13:49:setup_element:INFO: Clock phase scan results for group 0, downlink 2 13:13:49:setup_element:INFO: Eye window for uplink 16: _____________________________________________________________________XXXXXXXX___ Clock Delay: 32 13:13:49:setup_element:INFO: Eye window for uplink 17: _____________________________________________________________________XXXXXXXX___ Clock Delay: 32 13:13:49:setup_element:INFO: Eye window for uplink 18: ______________________________________________________________________XXXXXXX___ Clock Delay: 33 13:13:49:setup_element:INFO: Eye window for uplink 19: ______________________________________________________________________XXXXXXX___ Clock Delay: 33 13:13:49:setup_element:INFO: Eye window for uplink 20: _____________________________________________________________________XXXXXXXX___ Clock Delay: 32 13:13:49:setup_element:INFO: Eye window for uplink 21: _____________________________________________________________________XXXXXXXX___ Clock Delay: 32 13:13:49:setup_element:INFO: Eye window for uplink 22: ____________________________________________________________________XXXXXXX_____ Clock Delay: 31 13:13:49:setup_element:INFO: Eye window for uplink 23: ____________________________________________________________________XXXXXXX_____ Clock Delay: 31 13:13:49:setup_element:INFO: Eye window for uplink 24: ___________________________________________________________________XXXXXXXX_____ Clock Delay: 30 13:13:49:setup_element:INFO: Eye window for uplink 25: ___________________________________________________________________XXXXXXXX_____ Clock Delay: 30 13:13:49:setup_element:INFO: Eye window for uplink 26: ___________________________________________________________________XXXXXXXX_____ Clock Delay: 30 13:13:49:setup_element:INFO: Eye window for uplink 27: ___________________________________________________________________XXXXXXXX_____ Clock Delay: 30 13:13:49:setup_element:INFO: Eye window for uplink 28: ________________________________________________________________________________ Clock Delay: 40 13:13:49:setup_element:INFO: Eye window for uplink 29: ________________________________________________________________________________ Clock Delay: 40 13:13:49:setup_element:INFO: Eye window for uplink 30: ____________________________________________________________________XXXXXXXX____ Clock Delay: 31 13:13:49:setup_element:INFO: Eye window for uplink 31: ____________________________________________________________________XXXXXXXX____ Clock Delay: 31 13:13:49:setup_element:INFO: Setting the clock phase to 31 for group 0, downlink 2 13:13:49:setup_element:INFO: Scanning data phases 13:13:49:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2] 13:13:49:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2] 13:13:55:setup_element:INFO: Data phase scan results for group 0, downlink 2 13:13:55:setup_element:INFO: Eye window for uplink 16: XXXX__________________________________XX Data delay found: 20 13:13:55:setup_element:INFO: Eye window for uplink 17: XX__________________________________XXXX Data delay found: 18 13:13:55:setup_element:INFO: Eye window for uplink 18: XXXXX_________________________________XX Data delay found: 21 13:13:55:setup_element:INFO: Eye window for uplink 19: XXX_________________________________XXXX Data delay found: 19 13:13:55:setup_element:INFO: Eye window for uplink 20: XXX___________________________________XX Data delay found: 20 13:13:55:setup_element:INFO: Eye window for uplink 21: XX__________________________________XXXX Data delay found: 18 13:13:55:setup_element:INFO: Eye window for uplink 22: XX__________________________________XXXX Data delay found: 18 13:13:55:setup_element:INFO: Eye window for uplink 23: XXXXX_____________________________XXXXXX Data delay found: 19 13:13:55:setup_element:INFO: Eye window for uplink 24: ______XXXXX_____________________________ Data delay found: 28 13:13:55:setup_element:INFO: Eye window for uplink 25: _______XXXXXX___________________________ Data delay found: 29 13:13:55:setup_element:INFO: Eye window for uplink 26: _______XXXXX____________________________ Data delay found: 29 13:13:55:setup_element:INFO: Eye window for uplink 27: __________XXXXXX________________________ Data delay found: 32 13:13:55:setup_element:INFO: Eye window for uplink 28: _________________XXXXXX_________________ Data delay found: 39 13:13:55:setup_element:INFO: Eye window for uplink 29: ___________________XXXXXXX______________ Data delay found: 2 13:13:55:setup_element:INFO: Eye window for uplink 30: _______________XXXXXX___________________ Data delay found: 37 13:13:55:setup_element:INFO: Eye window for uplink 31: _______________XXXXXX___________________ Data delay found: 37 13:13:55:setup_element:INFO: Setting the data phase to 20 for uplink 16 13:13:55:setup_element:INFO: Setting the data phase to 18 for uplink 17 13:13:55:setup_element:INFO: Setting the data phase to 21 for uplink 18 13:13:55:setup_element:INFO: Setting the data phase to 19 for uplink 19 13:13:55:setup_element:INFO: Setting the data phase to 20 for uplink 20 13:13:55:setup_element:INFO: Setting the data phase to 18 for uplink 21 13:13:55:setup_element:INFO: Setting the data phase to 18 for uplink 22 13:13:55:setup_element:INFO: Setting the data phase to 19 for uplink 23 13:13:55:setup_element:INFO: Setting the data phase to 28 for uplink 24 13:13:55:setup_element:INFO: Setting the data phase to 29 for uplink 25 13:13:55:setup_element:INFO: Setting the data phase to 29 for uplink 26 13:13:55:setup_element:INFO: Setting the data phase to 32 for uplink 27 13:13:55:setup_element:INFO: Setting the data phase to 39 for uplink 28 13:13:55:setup_element:INFO: Setting the data phase to 2 for uplink 29 13:13:55:setup_element:INFO: Setting the data phase to 37 for uplink 30 13:13:55:setup_element:INFO: Setting the data phase to 37 for uplink 31 13:13:55:ST3_emu:ERROR: [ Setup Element: Group: 0 Downlink: 2 Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31] ASICs Map: None Clock Phase Characteristic: Optimal Phase: 31 Window Length: 70 Eye Windows: Uplink 16: _____________________________________________________________________XXXXXXXX___ Uplink 17: _____________________________________________________________________XXXXXXXX___ Uplink 18: ______________________________________________________________________XXXXXXX___ Uplink 19: ______________________________________________________________________XXXXXXX___ Uplink 20: _____________________________________________________________________XXXXXXXX___ Uplink 21: _____________________________________________________________________XXXXXXXX___ Uplink 22: ____________________________________________________________________XXXXXXX_____ Uplink 23: ____________________________________________________________________XXXXXXX_____ Uplink 24: ___________________________________________________________________XXXXXXXX_____ Uplink 25: ___________________________________________________________________XXXXXXXX_____ Uplink 26: ___________________________________________________________________XXXXXXXX_____ Uplink 27: ___________________________________________________________________XXXXXXXX_____ Uplink 28: ________________________________________________________________________________ Uplink 29: ________________________________________________________________________________ Uplink 30: ____________________________________________________________________XXXXXXXX____ Uplink 31: ____________________________________________________________________XXXXXXXX____ Data phase characteristics: Uplink 16: Optimal Phase: 20 Window Length: 34 Eye Window: XXXX__________________________________XX Uplink 17: Optimal Phase: 18 Window Length: 34 Eye Window: XX__________________________________XXXX Uplink 18: Optimal Phase: 21 Window Length: 33 Eye Window: XXXXX_________________________________XX Uplink 19: Optimal Phase: 19 Window Length: 33 Eye Window: XXX_________________________________XXXX Uplink 20: Optimal Phase: 20 Window Length: 35 Eye Window: XXX___________________________________XX Uplink 21: Optimal Phase: 18 Window Length: 34 Eye Window: XX__________________________________XXXX Uplink 22: Optimal Phase: 18 Window Length: 34 Eye Window: XX__________________________________XXXX Uplink 23: Optimal Phase: 19 Window Length: 29 Eye Window: XXXXX_____________________________XXXXXX Uplink 24: Optimal Phase: 28 Window Length: 35 Eye Window: ______XXXXX_____________________________ Uplink 25: Optimal Phase: 29 Window Length: 34 Eye Window: _______XXXXXX___________________________ Uplink 26: Optimal Phase: 29 Window Length: 35 Eye Window: _______XXXXX____________________________ Uplink 27: Optimal Phase: 32 Window Length: 34 Eye Window: __________XXXXXX________________________ Uplink 28: Optimal Phase: 39 Window Length: 34 Eye Window: _________________XXXXXX_________________ Uplink 29: Optimal Phase: 2 Window Length: 33 Eye Window: ___________________XXXXXXX______________ Uplink 30: Optimal Phase: 37 Window Length: 34 Eye Window: _______________XXXXXX___________________ Uplink 31: Optimal Phase: 37 Window Length: 34 Eye Window: _______________XXXXXX___________________ ] 13:13:55:setup_element:INFO: Beginning SMX ASICs map scan 13:13:55:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2] 13:13:55:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2] 13:13:55:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2] 13:13:55:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2] 13:13:55:uplink:INFO: Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31] 13:13:55:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 23 13:13:55:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 22 13:13:55:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 30 13:13:55:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 31 13:13:55:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 21 13:13:55:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 20 13:13:55:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28 13:13:55:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 29 13:13:56:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 19 13:13:56:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 18 13:13:56:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26 13:13:56:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 27 13:13:56:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 17 13:13:56:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 16 13:13:56:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 24 13:13:56:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 25 13:13:57:ST3_emu:ERROR: Setup Element: Group: 0 Downlink: 2 Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31] ASICs Map: ASIC address 0x0: (ASIC uplink, uplink): (0, 23), (1, 22) ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31) ASIC address 0x2: (ASIC uplink, uplink): (0, 21), (1, 20) ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29) ASIC address 0x4: (ASIC uplink, uplink): (0, 19), (1, 18) ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27) ASIC address 0x6: (ASIC uplink, uplink): (0, 17), (1, 16) ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25) Clock Phase Characteristic: Optimal Phase: 31 Window Length: 70 Eye Windows: Uplink 16: _____________________________________________________________________XXXXXXXX___ Uplink 17: _____________________________________________________________________XXXXXXXX___ Uplink 18: ______________________________________________________________________XXXXXXX___ Uplink 19: ______________________________________________________________________XXXXXXX___ Uplink 20: _____________________________________________________________________XXXXXXXX___ Uplink 21: _____________________________________________________________________XXXXXXXX___ Uplink 22: ____________________________________________________________________XXXXXXX_____ Uplink 23: ____________________________________________________________________XXXXXXX_____ Uplink 24: ___________________________________________________________________XXXXXXXX_____ Uplink 25: ___________________________________________________________________XXXXXXXX_____ Uplink 26: ___________________________________________________________________XXXXXXXX_____ Uplink 27: ___________________________________________________________________XXXXXXXX_____ Uplink 28: ________________________________________________________________________________ Uplink 29: ________________________________________________________________________________ Uplink 30: ____________________________________________________________________XXXXXXXX____ Uplink 31: ____________________________________________________________________XXXXXXXX____ Data phase characteristics: Uplink 16: Optimal Phase: 20 Window Length: 34 Eye Window: XXXX__________________________________XX Uplink 17: Optimal Phase: 18 Window Length: 34 Eye Window: XX__________________________________XXXX Uplink 18: Optimal Phase: 21 Window Length: 33 Eye Window: XXXXX_________________________________XX Uplink 19: Optimal Phase: 19 Window Length: 33 Eye Window: XXX_________________________________XXXX Uplink 20: Optimal Phase: 20 Window Length: 35 Eye Window: XXX___________________________________XX Uplink 21: Optimal Phase: 18 Window Length: 34 Eye Window: XX__________________________________XXXX Uplink 22: Optimal Phase: 18 Window Length: 34 Eye Window: XX__________________________________XXXX Uplink 23: Optimal Phase: 19 Window Length: 29 Eye Window: XXXXX_____________________________XXXXXX Uplink 24: Optimal Phase: 28 Window Length: 35 Eye Window: ______XXXXX_____________________________ Uplink 25: Optimal Phase: 29 Window Length: 34 Eye Window: _______XXXXXX___________________________ Uplink 26: Optimal Phase: 29 Window Length: 35 Eye Window: _______XXXXX____________________________ Uplink 27: Optimal Phase: 32 Window Length: 34 Eye Window: __________XXXXXX________________________ Uplink 28: Optimal Phase: 39 Window Length: 34 Eye Window: _________________XXXXXX_________________ Uplink 29: Optimal Phase: 2 Window Length: 33 Eye Window: ___________________XXXXXXX______________ Uplink 30: Optimal Phase: 37 Window Length: 34 Eye Window: _______________XXXXXX___________________ Uplink 31: Optimal Phase: 37 Window Length: 34 Eye Window: _______________XXXXXX___________________ 13:13:57:setup_element:INFO: Performing Elink synchronization 13:13:57:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2] 13:13:57:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2] 13:13:57:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2] 13:13:57:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2] 13:13:57:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2 13:13:57:uplink:INFO: Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31] 13:13:58:ST3_emu:INFO: Number of chips: 8 addr | upli | dwnli | grp | uplinks | uplinks_map 0 | [0] | 2 | 0 | [23] | [(0, 23), (1, 22)] 1 | [0] | 2 | 0 | [30] | [(0, 30), (1, 31)] 2 | [0] | 2 | 0 | [21] | [(0, 21), (1, 20)] 3 | [0] | 2 | 0 | [28] | [(0, 28), (1, 29)] 4 | [0] | 2 | 0 | [19] | [(0, 19), (1, 18)] 5 | [0] | 2 | 0 | [26] | [(0, 26), (1, 27)] 6 | [0] | 2 | 0 | [17] | [(0, 17), (1, 16)] 7 | [0] | 2 | 0 | [24] | [(0, 24), (1, 25)] 13:13:58:febtest:INFO: Init all SMX (CSA): 30 13:14:13:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_ 13:14:13:febtest:INFO: 23-00 | XA-000-08-002-002-006-097-09 | 37.7 | 1159.7 13:14:13:febtest:INFO: 30-01 | XA-000-08-002-002-006-172-06 | 40.9 | 1147.8 13:14:13:febtest:INFO: 21-02 | XA-000-08-002-002-006-077-07 | 50.4 | 1130.0 13:14:13:febtest:INFO: 28-03 | XA-000-08-002-002-006-170-06 | 47.3 | 1124.0 13:14:14:febtest:INFO: 19-04 | XA-000-08-002-002-006-063-11 | 56.8 | 1094.2 13:14:14:febtest:INFO: 26-05 | XA-000-08-002-002-006-117-14 | 40.9 | 1141.9 13:14:14:febtest:INFO: 17-06 | XA-000-08-002-002-006-070-07 | 40.9 | 1147.8 13:14:14:febtest:INFO: 24-07 | XA-000-08-002-002-006-188-01 | 37.7 | 1153.7 13:14:15:febtest:INFO: Set all CSA to ZERO FEB type: B FEB_A: 0 FEB_B: 1 13:14:17:ST3_smx:INFO: chip: 23-0 40.898880 C 1171.483840 mV 13:14:17:ST3_discr_histo:WARNING: Not enough entries for fit!!! 13:14:17:ST3_discr_histo:WARNING: Not enough entries for fit!!! 13:14:17:ST3_smx:INFO: Electrons 13:14:17:ST3_smx:INFO: # loops 0 13:14:19:ST3_smx:INFO: # loops 1 13:14:21:ST3_smx:INFO: # loops 2 13:14:22:ST3_smx:INFO: Total # of broken channels: 0 13:14:22:ST3_smx:INFO: List of broken channels: [] 13:14:22:ST3_smx:INFO: Total # of broken channels: 0 13:14:22:ST3_smx:INFO: List of broken channels: [] 13:14:24:ST3_smx:INFO: chip: 30-1 40.898880 C 1159.654860 mV 13:14:24:ST3_discr_histo:WARNING: Not enough entries for fit!!! 13:14:24:ST3_discr_histo:WARNING: Not enough entries for fit!!! 13:14:24:ST3_smx:INFO: Electrons 13:14:24:ST3_smx:INFO: # loops 0 13:14:26:ST3_smx:INFO: # loops 1 13:14:27:ST3_smx:INFO: # loops 2 13:14:29:ST3_smx:INFO: Total # of broken channels: 0 13:14:29:ST3_smx:INFO: List of broken channels: [] 13:14:29:ST3_smx:INFO: Total # of broken channels: 0 13:14:29:ST3_smx:INFO: List of broken channels: [] 13:14:31:ST3_smx:INFO: chip: 21-2 53.612520 C 1141.874115 mV 13:14:31:ST3_discr_histo:WARNING: Not enough entries for fit!!! 13:14:31:ST3_discr_histo:WARNING: Not enough entries for fit!!! 13:14:31:ST3_smx:INFO: Electrons 13:14:31:ST3_smx:INFO: # loops 0 13:14:32:ST3_smx:INFO: # loops 1 13:14:34:ST3_smx:INFO: # loops 2 13:14:36:ST3_smx:INFO: Total # of broken channels: 0 13:14:36:ST3_smx:INFO: List of broken channels: [] 13:14:36:ST3_smx:INFO: Total # of broken channels: 0 13:14:36:ST3_smx:INFO: List of broken channels: [] 13:14:37:ST3_smx:INFO: chip: 28-3 47.250730 C 1135.937260 mV 13:14:37:ST3_discr_histo:WARNING: Not enough entries for fit!!! 13:14:37:ST3_discr_histo:WARNING: Not enough entries for fit!!! 13:14:37:ST3_smx:INFO: Electrons 13:14:37:ST3_smx:INFO: # loops 0 13:14:39:ST3_smx:INFO: # loops 1 13:14:41:ST3_smx:INFO: # loops 2 13:14:42:ST3_smx:INFO: Total # of broken channels: 1 13:14:42:ST3_smx:INFO: List of broken channels: [49] 13:14:42:ST3_smx:INFO: Total # of broken channels: 1 13:14:42:ST3_smx:INFO: List of broken channels: [49] 13:14:44:ST3_smx:INFO: chip: 19-4 56.797143 C 1106.178435 mV 13:14:44:ST3_discr_histo:WARNING: Not enough entries for fit!!! 13:14:44:ST3_discr_histo:WARNING: Not enough entries for fit!!! 13:14:44:ST3_smx:INFO: Electrons 13:14:44:ST3_smx:INFO: # loops 0 13:14:46:ST3_smx:INFO: # loops 1 13:14:47:ST3_smx:INFO: # loops 2 13:14:49:ST3_smx:INFO: Total # of broken channels: 0 13:14:49:ST3_smx:INFO: List of broken channels: [] 13:14:49:ST3_smx:INFO: Total # of broken channels: 0 13:14:49:ST3_smx:INFO: List of broken channels: [] 13:14:51:ST3_smx:INFO: chip: 26-5 40.898880 C 1153.732915 mV 13:14:51:ST3_discr_histo:WARNING: Not enough entries for fit!!! 13:14:51:ST3_discr_histo:WARNING: Not enough entries for fit!!! 13:14:51:ST3_smx:INFO: Electrons 13:14:51:ST3_smx:INFO: # loops 0 13:14:53:ST3_smx:INFO: # loops 1 13:14:54:ST3_smx:INFO: # loops 2 13:14:56:ST3_smx:INFO: Total # of broken channels: 0 13:14:56:ST3_smx:INFO: List of broken channels: [] 13:14:56:ST3_smx:INFO: Total # of broken channels: 32 13:14:56:ST3_smx:INFO: List of broken channels: [63, 65, 69, 71, 73, 75, 77, 79, 81, 83, 85, 87, 89, 91, 93, 95, 97, 99, 101, 103, 105, 107, 109, 111, 113, 115, 117, 119, 121, 123, 125, 127] 13:14:58:ST3_smx:INFO: chip: 17-6 40.898880 C 1153.732915 mV 13:14:58:ST3_discr_histo:WARNING: Not enough entries for fit!!! 13:14:58:ST3_discr_histo:WARNING: Not enough entries for fit!!! 13:14:58:ST3_smx:INFO: Electrons 13:14:58:ST3_smx:INFO: # loops 0 13:14:59:ST3_smx:INFO: # loops 1 13:15:01:ST3_smx:INFO: # loops 2 13:15:02:ST3_smx:INFO: Total # of broken channels: 0 13:15:02:ST3_smx:INFO: List of broken channels: [] 13:15:02:ST3_smx:INFO: Total # of broken channels: 0 13:15:03:ST3_smx:INFO: List of broken channels: [] 13:15:04:ST3_smx:INFO: chip: 24-7 37.726682 C 1165.571835 mV 13:15:04:ST3_discr_histo:WARNING: Not enough entries for fit!!! 13:15:04:ST3_discr_histo:WARNING: Not enough entries for fit!!! 13:15:04:ST3_smx:INFO: Electrons 13:15:04:ST3_smx:INFO: # loops 0 13:15:06:ST3_smx:INFO: # loops 1 13:15:08:ST3_smx:INFO: # loops 2 13:15:09:ST3_smx:INFO: Total # of broken channels: 0 13:15:09:ST3_smx:INFO: List of broken channels: [] 13:15:09:ST3_smx:INFO: Total # of broken channels: 0 13:15:09:ST3_smx:INFO: List of broken channels: [] 13:15:10:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_ 13:15:10:febtest:INFO: 23-00 | XA-000-08-002-002-006-097-09 | 40.9 | 1195.1 13:15:10:febtest:INFO: 30-01 | XA-000-08-002-002-006-172-06 | 44.1 | 1177.4 13:15:10:febtest:INFO: 21-02 | XA-000-08-002-002-006-077-07 | 50.4 | 1159.7 13:15:10:febtest:INFO: 28-03 | XA-000-08-002-002-006-170-06 | 47.3 | 1153.7 13:15:11:febtest:INFO: 19-04 | XA-000-08-002-002-006-063-11 | 60.0 | 1130.0 13:15:11:febtest:INFO: 26-05 | XA-000-08-002-002-006-117-14 | 40.9 | 1171.5 13:15:11:febtest:INFO: 17-06 | XA-000-08-002-002-006-070-07 | 44.1 | 1171.5 13:15:11:febtest:INFO: 24-07 | XA-000-08-002-002-006-188-01 | 40.9 | 1183.3 ############################################################ # S U M M A R Y # ############################################################ {'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31} =============================== {'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31} =============================== {'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31} =============================== {'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31} =============================== {'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31} =============================== {'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31} =============================== {'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31} =============================== {'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31} =============================== ############################################################ # S U M M A R Y # ############################################################ TEST_NAME : FEB-Microcable TEST_DATE : 24_05_28-13_13_46 OPERATOR : Oleksandr S.; SITE : GSI | SETUP : GSI_TEST_SETUP_1 ------------------------------------------------------------ | FEB_SN : 2174| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_B ------------------------------------------------------------ ------------------------------------------------------------ VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.5760', '1.851', '2.6600'] VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '2.0180', '1.850', '2.5920'] VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.9900', '1.850', '0.5297']