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FEB_2175 04.06.24 08:18:31
Info
08:18:31:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
08:18:31:ST3_Shared:INFO: FEB-Sensor
08:18:31:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
08:18:49:ST3_ModuleSelector:INFO: L7DL300122 M7DL3B0001220B2 42 A
08:18:49:ST3_ModuleSelector:INFO: 07222
08:18:49:febtest:INFO: Testing FEB with SN 2175
08:18:51:smx_tester:INFO: Scanning setup
08:18:51:elinks:INFO: Disabling clock on downlink 0
08:18:51:elinks:INFO: Disabling clock on downlink 1
08:18:51:elinks:INFO: Disabling clock on downlink 2
08:18:51:elinks:INFO: Disabling clock on downlink 3
08:18:51:elinks:INFO: Disabling clock on downlink 4
08:18:51:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:18:51:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
08:18:51:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:18:51:elinks:INFO: Disabling clock on downlink 0
08:18:51:elinks:INFO: Disabling clock on downlink 1
08:18:51:elinks:INFO: Disabling clock on downlink 2
08:18:51:elinks:INFO: Disabling clock on downlink 3
08:18:51:elinks:INFO: Disabling clock on downlink 4
08:18:51:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:18:51:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
08:18:51:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:18:51:elinks:INFO: Disabling clock on downlink 0
08:18:51:elinks:INFO: Disabling clock on downlink 1
08:18:51:elinks:INFO: Disabling clock on downlink 2
08:18:51:elinks:INFO: Disabling clock on downlink 3
08:18:51:elinks:INFO: Disabling clock on downlink 4
08:18:51:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:18:51:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
08:18:51:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 16
08:18:51:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 17
08:18:51:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 18
08:18:51:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 19
08:18:51:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 20
08:18:51:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 21
08:18:51:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 22
08:18:51:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 23
08:18:51:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24
08:18:51:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25
08:18:51:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26
08:18:51:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27
08:18:51:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28
08:18:51:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29
08:18:51:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30
08:18:51:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31
08:18:51:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:18:51:elinks:INFO: Disabling clock on downlink 0
08:18:51:elinks:INFO: Disabling clock on downlink 1
08:18:51:elinks:INFO: Disabling clock on downlink 2
08:18:51:elinks:INFO: Disabling clock on downlink 3
08:18:51:elinks:INFO: Disabling clock on downlink 4
08:18:51:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:18:51:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
08:18:51:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:18:51:elinks:INFO: Disabling clock on downlink 0
08:18:51:elinks:INFO: Disabling clock on downlink 1
08:18:51:elinks:INFO: Disabling clock on downlink 2
08:18:51:elinks:INFO: Disabling clock on downlink 3
08:18:51:elinks:INFO: Disabling clock on downlink 4
08:18:51:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:18:51:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
08:18:51:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:18:51:setup_element:INFO: Scanning clock phase
08:18:51:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
08:18:51:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
08:18:52:setup_element:INFO: Clock phase scan results for group 0, downlink 2
08:18:52:setup_element:INFO: Eye window for uplink 16: _____________________________________________________________________XXXXXXX____
Clock Delay: 32
08:18:52:setup_element:INFO: Eye window for uplink 17: _____________________________________________________________________XXXXXXX____
Clock Delay: 32
08:18:52:setup_element:INFO: Eye window for uplink 18: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
08:18:52:setup_element:INFO: Eye window for uplink 19: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
08:18:52:setup_element:INFO: Eye window for uplink 20: _____________________________________________________________________XXXXXXXXX__
Clock Delay: 33
08:18:52:setup_element:INFO: Eye window for uplink 21: _____________________________________________________________________XXXXXXXXX__
Clock Delay: 33
08:18:52:setup_element:INFO: Eye window for uplink 22: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
08:18:52:setup_element:INFO: Eye window for uplink 23: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
08:18:52:setup_element:INFO: Eye window for uplink 24: ___________________________________________________________________XXXXXXXXX____
Clock Delay: 31
08:18:52:setup_element:INFO: Eye window for uplink 25: ___________________________________________________________________XXXXXXXXX____
Clock Delay: 31
08:18:52:setup_element:INFO: Eye window for uplink 26: ________________________________________________________________________________
Clock Delay: 40
08:18:52:setup_element:INFO: Eye window for uplink 27: ________________________________________________________________________________
Clock Delay: 40
08:18:52:setup_element:INFO: Eye window for uplink 28: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
08:18:52:setup_element:INFO: Eye window for uplink 29: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
08:18:52:setup_element:INFO: Eye window for uplink 30: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
08:18:52:setup_element:INFO: Eye window for uplink 31: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
08:18:52:setup_element:INFO: Setting the clock phase to 32 for group 0, downlink 2
08:18:52:setup_element:INFO: Scanning data phases
08:18:52:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
08:18:52:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
08:18:57:setup_element:INFO: Data phase scan results for group 0, downlink 2
08:18:57:setup_element:INFO: Eye window for uplink 16: XX__________________________________XXXX
Data delay found: 18
08:18:57:setup_element:INFO: Eye window for uplink 17: ___________________________________XXXXX
Data delay found: 17
08:18:57:setup_element:INFO: Eye window for uplink 18: X__________________________________XXXXX
Data delay found: 17
08:18:57:setup_element:INFO: Eye window for uplink 19: _________________________________XXXXX__
Data delay found: 15
08:18:57:setup_element:INFO: Eye window for uplink 20: XX___________________________________XXX
Data delay found: 19
08:18:57:setup_element:INFO: Eye window for uplink 21: XX__________________________________XXXX
Data delay found: 18
08:18:57:setup_element:INFO: Eye window for uplink 22: X__________________________________XXXXX
Data delay found: 17
08:18:57:setup_element:INFO: Eye window for uplink 23: XXXX_____________________________XXXXXXX
Data delay found: 18
08:18:57:setup_element:INFO: Eye window for uplink 24: ______XXXXX_____________________________
Data delay found: 28
08:18:57:setup_element:INFO: Eye window for uplink 25: ________XXXXX___________________________
Data delay found: 30
08:18:57:setup_element:INFO: Eye window for uplink 26: ________XXXXX___________________________
Data delay found: 30
08:18:57:setup_element:INFO: Eye window for uplink 27: ___________XXXXXX_______________________
Data delay found: 33
08:18:57:setup_element:INFO: Eye window for uplink 28: ______________XXXXX_____________________
Data delay found: 36
08:18:57:setup_element:INFO: Eye window for uplink 29: ________________XXXXXX__________________
Data delay found: 38
08:18:57:setup_element:INFO: Eye window for uplink 30: _______________XXXXXX___________________
Data delay found: 37
08:18:57:setup_element:INFO: Eye window for uplink 31: _______________XXXXXXX__________________
Data delay found: 38
08:18:57:setup_element:INFO: Setting the data phase to 18 for uplink 16
08:18:57:setup_element:INFO: Setting the data phase to 17 for uplink 17
08:18:57:setup_element:INFO: Setting the data phase to 17 for uplink 18
08:18:57:setup_element:INFO: Setting the data phase to 15 for uplink 19
08:18:57:setup_element:INFO: Setting the data phase to 19 for uplink 20
08:18:57:setup_element:INFO: Setting the data phase to 18 for uplink 21
08:18:57:setup_element:INFO: Setting the data phase to 17 for uplink 22
08:18:57:setup_element:INFO: Setting the data phase to 18 for uplink 23
08:18:57:setup_element:INFO: Setting the data phase to 28 for uplink 24
08:18:57:setup_element:INFO: Setting the data phase to 30 for uplink 25
08:18:57:setup_element:INFO: Setting the data phase to 30 for uplink 26
08:18:57:setup_element:INFO: Setting the data phase to 33 for uplink 27
08:18:57:setup_element:INFO: Setting the data phase to 36 for uplink 28
08:18:57:setup_element:INFO: Setting the data phase to 38 for uplink 29
08:18:57:setup_element:INFO: Setting the data phase to 37 for uplink 30
08:18:57:setup_element:INFO: Setting the data phase to 38 for uplink 31
08:18:57:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 32
Window Length: 69
Eye Windows:
Uplink 16: _____________________________________________________________________XXXXXXX____
Uplink 17: _____________________________________________________________________XXXXXXX____
Uplink 18: ____________________________________________________________________XXXXXXXX____
Uplink 19: ____________________________________________________________________XXXXXXXX____
Uplink 20: _____________________________________________________________________XXXXXXXXX__
Uplink 21: _____________________________________________________________________XXXXXXXXX__
Uplink 22: ____________________________________________________________________XXXXXXXX____
Uplink 23: ____________________________________________________________________XXXXXXXX____
Uplink 24: ___________________________________________________________________XXXXXXXXX____
Uplink 25: ___________________________________________________________________XXXXXXXXX____
Uplink 26: ________________________________________________________________________________
Uplink 27: ________________________________________________________________________________
Uplink 28: _____________________________________________________________________XXXXXXXX___
Uplink 29: _____________________________________________________________________XXXXXXXX___
Uplink 30: ______________________________________________________________________XXXXXXXX__
Uplink 31: ______________________________________________________________________XXXXXXXX__
Data phase characteristics:
Uplink 16:
Optimal Phase: 18
Window Length: 34
Eye Window: XX__________________________________XXXX
Uplink 17:
Optimal Phase: 17
Window Length: 35
Eye Window: ___________________________________XXXXX
Uplink 18:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXXX
Uplink 19:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
Uplink 20:
Optimal Phase: 19
Window Length: 35
Eye Window: XX___________________________________XXX
Uplink 21:
Optimal Phase: 18
Window Length: 34
Eye Window: XX__________________________________XXXX
Uplink 22:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXXX
Uplink 23:
Optimal Phase: 18
Window Length: 29
Eye Window: XXXX_____________________________XXXXXXX
Uplink 24:
Optimal Phase: 28
Window Length: 35
Eye Window: ______XXXXX_____________________________
Uplink 25:
Optimal Phase: 30
Window Length: 35
Eye Window: ________XXXXX___________________________
Uplink 26:
Optimal Phase: 30
Window Length: 35
Eye Window: ________XXXXX___________________________
Uplink 27:
Optimal Phase: 33
Window Length: 34
Eye Window: ___________XXXXXX_______________________
Uplink 28:
Optimal Phase: 36
Window Length: 35
Eye Window: ______________XXXXX_____________________
Uplink 29:
Optimal Phase: 38
Window Length: 34
Eye Window: ________________XXXXXX__________________
Uplink 30:
Optimal Phase: 37
Window Length: 34
Eye Window: _______________XXXXXX___________________
Uplink 31:
Optimal Phase: 38
Window Length: 33
Eye Window: _______________XXXXXXX__________________
]
08:18:57:setup_element:INFO: Beginning SMX ASICs map scan
08:18:57:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
08:18:57:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
08:18:57:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
08:18:57:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
08:18:57:uplink:INFO: Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
08:18:57:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 23
08:18:57:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 22
08:18:57:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 30
08:18:57:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 31
08:18:58:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 21
08:18:58:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 20
08:18:58:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28
08:18:58:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 29
08:18:58:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 19
08:18:58:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 18
08:18:58:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26
08:18:58:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 27
08:18:58:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 17
08:18:58:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 16
08:18:58:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 24
08:18:59:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 25
08:19:00:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 23), (1, 22)
ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
ASIC address 0x2: (ASIC uplink, uplink): (0, 21), (1, 20)
ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
ASIC address 0x4: (ASIC uplink, uplink): (0, 19), (1, 18)
ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
ASIC address 0x6: (ASIC uplink, uplink): (0, 17), (1, 16)
ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
Clock Phase Characteristic:
Optimal Phase: 32
Window Length: 69
Eye Windows:
Uplink 16: _____________________________________________________________________XXXXXXX____
Uplink 17: _____________________________________________________________________XXXXXXX____
Uplink 18: ____________________________________________________________________XXXXXXXX____
Uplink 19: ____________________________________________________________________XXXXXXXX____
Uplink 20: _____________________________________________________________________XXXXXXXXX__
Uplink 21: _____________________________________________________________________XXXXXXXXX__
Uplink 22: ____________________________________________________________________XXXXXXXX____
Uplink 23: ____________________________________________________________________XXXXXXXX____
Uplink 24: ___________________________________________________________________XXXXXXXXX____
Uplink 25: ___________________________________________________________________XXXXXXXXX____
Uplink 26: ________________________________________________________________________________
Uplink 27: ________________________________________________________________________________
Uplink 28: _____________________________________________________________________XXXXXXXX___
Uplink 29: _____________________________________________________________________XXXXXXXX___
Uplink 30: ______________________________________________________________________XXXXXXXX__
Uplink 31: ______________________________________________________________________XXXXXXXX__
Data phase characteristics:
Uplink 16:
Optimal Phase: 18
Window Length: 34
Eye Window: XX__________________________________XXXX
Uplink 17:
Optimal Phase: 17
Window Length: 35
Eye Window: ___________________________________XXXXX
Uplink 18:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXXX
Uplink 19:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
Uplink 20:
Optimal Phase: 19
Window Length: 35
Eye Window: XX___________________________________XXX
Uplink 21:
Optimal Phase: 18
Window Length: 34
Eye Window: XX__________________________________XXXX
Uplink 22:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXXX
Uplink 23:
Optimal Phase: 18
Window Length: 29
Eye Window: XXXX_____________________________XXXXXXX
Uplink 24:
Optimal Phase: 28
Window Length: 35
Eye Window: ______XXXXX_____________________________
Uplink 25:
Optimal Phase: 30
Window Length: 35
Eye Window: ________XXXXX___________________________
Uplink 26:
Optimal Phase: 30
Window Length: 35
Eye Window: ________XXXXX___________________________
Uplink 27:
Optimal Phase: 33
Window Length: 34
Eye Window: ___________XXXXXX_______________________
Uplink 28:
Optimal Phase: 36
Window Length: 35
Eye Window: ______________XXXXX_____________________
Uplink 29:
Optimal Phase: 38
Window Length: 34
Eye Window: ________________XXXXXX__________________
Uplink 30:
Optimal Phase: 37
Window Length: 34
Eye Window: _______________XXXXXX___________________
Uplink 31:
Optimal Phase: 38
Window Length: 33
Eye Window: _______________XXXXXXX__________________
08:19:00:setup_element:INFO: Performing Elink synchronization
08:19:00:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
08:19:00:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
08:19:00:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
08:19:00:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
08:19:00:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2
08:19:00:uplink:INFO: Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
08:19:00:ST3_emu:INFO: Number of chips: 8
addr | upli | dwnli | grp | uplinks | uplinks_map
0 | [0] | 2 | 0 | [23] | [(0, 23), (1, 22)]
1 | [0] | 2 | 0 | [30] | [(0, 30), (1, 31)]
2 | [0] | 2 | 0 | [21] | [(0, 21), (1, 20)]
3 | [0] | 2 | 0 | [28] | [(0, 28), (1, 29)]
4 | [0] | 2 | 0 | [19] | [(0, 19), (1, 18)]
5 | [0] | 2 | 0 | [26] | [(0, 26), (1, 27)]
6 | [0] | 2 | 0 | [17] | [(0, 17), (1, 16)]
7 | [0] | 2 | 0 | [24] | [(0, 24), (1, 25)]
08:19:01:febtest:INFO: Init all SMX (CSA): 30
08:19:16:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
08:19:16:febtest:INFO: 23-00 | XA-000-08-002-000-007-178-05 | 37.7 | 1153.7
08:19:16:febtest:INFO: 30-01 | XA-000-08-002-000-007-213-14 | 37.7 | 1153.7
08:19:17:febtest:INFO: 21-02 | XA-000-08-002-001-006-013-03 | 37.7 | 1165.6
08:19:17:febtest:INFO: 28-03 | XA-000-08-002-000-007-207-09 | 50.4 | 1112.1
08:19:17:febtest:INFO: 19-04 | XA-000-08-002-000-007-209-14 | 34.6 | 1177.4
08:19:17:febtest:INFO: 26-05 | XA-000-08-002-000-007-205-09 | 44.1 | 1130.0
08:19:17:febtest:INFO: 17-06 | XA-000-08-002-000-007-189-05 | 47.3 | 1130.0
08:19:18:febtest:INFO: 24-07 | XA-000-08-002-000-007-183-05 | 44.1 | 1124.0
08:19:19:febtest:INFO: Set all CSA to ZERO
FEB type: B FEB_A: 0 FEB_B: 1
08:19:21:ST3_smx:INFO: chip: 23-0 37.726682 C 1165.571835 mV
08:19:21:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:19:21:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:19:21:ST3_smx:INFO: Electrons
08:19:21:ST3_smx:INFO: # loops 0
08:19:22:ST3_smx:INFO: # loops 1
08:19:24:ST3_smx:INFO: # loops 2
08:19:26:ST3_smx:INFO: # loops 3
08:19:28:ST3_smx:INFO: # loops 4
08:19:29:ST3_smx:INFO: Total # of broken channels: 0
08:19:29:ST3_smx:INFO: List of broken channels: []
08:19:29:ST3_smx:INFO: Total # of broken channels: 0
08:19:29:ST3_smx:INFO: List of broken channels: []
08:19:31:ST3_smx:INFO: chip: 30-1 37.726682 C 1165.571835 mV
08:19:31:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:19:31:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:19:31:ST3_smx:INFO: Electrons
08:19:31:ST3_smx:INFO: # loops 0
08:19:33:ST3_smx:INFO: # loops 1
08:19:35:ST3_smx:INFO: # loops 2
08:19:36:ST3_smx:INFO: # loops 3
08:19:38:ST3_smx:INFO: # loops 4
08:19:40:ST3_smx:INFO: Total # of broken channels: 0
08:19:40:ST3_smx:INFO: List of broken channels: []
08:19:40:ST3_smx:INFO: Total # of broken channels: 0
08:19:40:ST3_smx:INFO: List of broken channels: []
08:19:42:ST3_smx:INFO: chip: 21-2 37.726682 C 1171.483840 mV
08:19:42:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:19:42:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:19:42:ST3_smx:INFO: Electrons
08:19:42:ST3_smx:INFO: # loops 0
08:19:44:ST3_smx:INFO: # loops 1
08:19:45:ST3_smx:INFO: # loops 2
08:19:47:ST3_smx:INFO: # loops 3
08:19:49:ST3_smx:INFO: # loops 4
08:19:51:ST3_smx:INFO: Total # of broken channels: 0
08:19:51:ST3_smx:INFO: List of broken channels: []
08:19:51:ST3_smx:INFO: Total # of broken channels: 0
08:19:51:ST3_smx:INFO: List of broken channels: []
08:19:52:ST3_smx:INFO: chip: 28-3 50.430383 C 1124.048640 mV
08:19:52:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:19:52:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:19:52:ST3_smx:INFO: Electrons
08:19:52:ST3_smx:INFO: # loops 0
08:19:54:ST3_smx:INFO: # loops 1
08:19:56:ST3_smx:INFO: # loops 2
08:19:57:ST3_smx:INFO: # loops 3
08:19:59:ST3_smx:INFO: # loops 4
08:20:01:ST3_smx:INFO: Total # of broken channels: 0
08:20:01:ST3_smx:INFO: List of broken channels: []
08:20:01:ST3_smx:INFO: Total # of broken channels: 0
08:20:01:ST3_smx:INFO: List of broken channels: []
08:20:03:ST3_smx:INFO: chip: 19-4 34.556970 C 1183.292940 mV
08:20:03:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:20:03:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:20:03:ST3_smx:INFO: Electrons
08:20:03:ST3_smx:INFO: # loops 0
08:20:04:ST3_smx:INFO: # loops 1
08:20:06:ST3_smx:INFO: # loops 2
08:20:08:ST3_smx:INFO: # loops 3
08:20:10:ST3_smx:INFO: # loops 4
08:20:11:ST3_smx:INFO: Total # of broken channels: 0
08:20:11:ST3_smx:INFO: List of broken channels: []
08:20:11:ST3_smx:INFO: Total # of broken channels: 4
08:20:11:ST3_smx:INFO: List of broken channels: [99, 101, 103, 113]
08:20:13:ST3_smx:INFO: chip: 26-5 44.073563 C 1141.874115 mV
08:20:13:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:20:13:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:20:13:ST3_smx:INFO: Electrons
08:20:13:ST3_smx:INFO: # loops 0
08:20:15:ST3_smx:INFO: # loops 1
08:20:16:ST3_smx:INFO: # loops 2
08:20:18:ST3_smx:INFO: # loops 3
08:20:20:ST3_smx:INFO: # loops 4
08:20:22:ST3_smx:INFO: Total # of broken channels: 0
08:20:22:ST3_smx:INFO: List of broken channels: []
08:20:22:ST3_smx:INFO: Total # of broken channels: 0
08:20:22:ST3_smx:INFO: List of broken channels: []
08:20:23:ST3_smx:INFO: chip: 17-6 50.430383 C 1135.937260 mV
08:20:23:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:20:23:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:20:24:ST3_smx:INFO: Electrons
08:20:24:ST3_smx:INFO: # loops 0
08:20:25:ST3_smx:INFO: # loops 1
08:20:27:ST3_smx:INFO: # loops 2
08:20:29:ST3_smx:INFO: # loops 3
08:20:31:ST3_smx:INFO: # loops 4
08:20:32:ST3_smx:INFO: Total # of broken channels: 0
08:20:32:ST3_smx:INFO: List of broken channels: []
08:20:32:ST3_smx:INFO: Total # of broken channels: 0
08:20:32:ST3_smx:INFO: List of broken channels: []
08:20:34:ST3_smx:INFO: chip: 24-7 47.250730 C 1135.937260 mV
08:20:34:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:20:34:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:20:34:ST3_smx:INFO: Electrons
08:20:34:ST3_smx:INFO: # loops 0
08:20:36:ST3_smx:INFO: # loops 1
08:20:37:ST3_smx:INFO: # loops 2
08:20:39:ST3_smx:INFO: # loops 3
08:20:41:ST3_smx:INFO: # loops 4
08:20:43:ST3_smx:INFO: Total # of broken channels: 0
08:20:43:ST3_smx:INFO: List of broken channels: []
08:20:43:ST3_smx:INFO: Total # of broken channels: 0
08:20:43:ST3_smx:INFO: List of broken channels: []
08:20:43:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
08:20:43:febtest:INFO: 23-00 | XA-000-08-002-000-007-178-05 | 40.9 | 1189.2
08:20:43:febtest:INFO: 30-01 | XA-000-08-002-000-007-213-14 | 40.9 | 1189.2
08:20:44:febtest:INFO: 21-02 | XA-000-08-002-001-006-013-03 | 40.9 | 1195.1
08:20:44:febtest:INFO: 28-03 | XA-000-08-002-000-007-207-09 | 50.4 | 1141.9
08:20:44:febtest:INFO: 19-04 | XA-000-08-002-000-007-209-14 | 37.7 | 1206.9
08:20:44:febtest:INFO: 26-05 | XA-000-08-002-000-007-205-09 | 47.3 | 1159.7
08:20:44:febtest:INFO: 17-06 | XA-000-08-002-000-007-189-05 | 50.4 | 1153.7
08:20:45:febtest:INFO: 24-07 | XA-000-08-002-000-007-183-05 | 47.3 | 1147.8
############################################################
# S U M M A R Y #
############################################################
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-Sensor
TEST_DATE : 24_06_04-08_18_31
OPERATOR : Oleksandr S.;
SITE : GSI | SETUP : GSI_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 2175| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_B
------------------------------------------------------------
SENSOR_ID: 07222
MODULE_NAME: L7DL300122 M7DL3B0001220B2 42 A
MODULE_TYPE:
MODULE_LADDER: L7DL300122
MODULE_MODULE: M7DL3B0001220B2
MODULE_SIZE: 42
MODULE_GRADE: A
------------------------------------------------------------
VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.5790', '1.852', '2.4620']
VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '2.0590', '1.850', '2.5630']
VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '2.0110', '1.850', '0.5346']