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FEB_2184 04.06.24 14:05:06
Info
14:05:06:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:05:06:ST3_Shared:INFO: FEB-Microcable
14:05:06:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:05:06:febtest:INFO: Testing FEB with SN 2184
14:05:07:smx_tester:INFO: Scanning setup
14:05:07:elinks:INFO: Disabling clock on downlink 0
14:05:07:elinks:INFO: Disabling clock on downlink 1
14:05:07:elinks:INFO: Disabling clock on downlink 2
14:05:07:elinks:INFO: Disabling clock on downlink 3
14:05:07:elinks:INFO: Disabling clock on downlink 4
14:05:07:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:05:07:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
14:05:07:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:05:07:elinks:INFO: Disabling clock on downlink 0
14:05:07:elinks:INFO: Disabling clock on downlink 1
14:05:07:elinks:INFO: Disabling clock on downlink 2
14:05:07:elinks:INFO: Disabling clock on downlink 3
14:05:07:elinks:INFO: Disabling clock on downlink 4
14:05:07:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:05:07:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
14:05:07:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:05:07:elinks:INFO: Disabling clock on downlink 0
14:05:07:elinks:INFO: Disabling clock on downlink 1
14:05:07:elinks:INFO: Disabling clock on downlink 2
14:05:07:elinks:INFO: Disabling clock on downlink 3
14:05:07:elinks:INFO: Disabling clock on downlink 4
14:05:08:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:05:08:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
14:05:08:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24
14:05:08:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25
14:05:08:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26
14:05:08:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27
14:05:08:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28
14:05:08:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29
14:05:08:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30
14:05:08:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31
14:05:08:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:05:08:elinks:INFO: Disabling clock on downlink 0
14:05:08:elinks:INFO: Disabling clock on downlink 1
14:05:08:elinks:INFO: Disabling clock on downlink 2
14:05:08:elinks:INFO: Disabling clock on downlink 3
14:05:08:elinks:INFO: Disabling clock on downlink 4
14:05:08:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:05:08:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
14:05:08:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:05:08:elinks:INFO: Disabling clock on downlink 0
14:05:08:elinks:INFO: Disabling clock on downlink 1
14:05:08:elinks:INFO: Disabling clock on downlink 2
14:05:08:elinks:INFO: Disabling clock on downlink 3
14:05:08:elinks:INFO: Disabling clock on downlink 4
14:05:08:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:05:08:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
14:05:08:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:05:08:setup_element:INFO: Scanning clock phase
14:05:08:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
14:05:08:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
14:05:08:setup_element:INFO: Clock phase scan results for group 0, downlink 2
14:05:08:setup_element:INFO: Eye window for uplink 24: __________________________________________________________________XXXXXXXX______
Clock Delay: 29
14:05:08:setup_element:INFO: Eye window for uplink 25: __________________________________________________________________XXXXXXXX______
Clock Delay: 29
14:05:08:setup_element:INFO: Eye window for uplink 26: __________________________________________________________________XXXXXXXX______
Clock Delay: 29
14:05:08:setup_element:INFO: Eye window for uplink 27: __________________________________________________________________XXXXXXXX______
Clock Delay: 29
14:05:08:setup_element:INFO: Eye window for uplink 28: ___________________________________________________________________XXXXXXX______
Clock Delay: 30
14:05:08:setup_element:INFO: Eye window for uplink 29: ___________________________________________________________________XXXXXXX______
Clock Delay: 30
14:05:08:setup_element:INFO: Eye window for uplink 30: ___________________________________________________________________XXXXXXX______
Clock Delay: 30
14:05:08:setup_element:INFO: Eye window for uplink 31: ___________________________________________________________________XXXXXXX______
Clock Delay: 30
14:05:08:setup_element:INFO: Setting the clock phase to 29 for group 0, downlink 2
14:05:08:setup_element:INFO: Scanning data phases
14:05:08:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
14:05:08:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
14:05:14:setup_element:INFO: Data phase scan results for group 0, downlink 2
14:05:14:setup_element:INFO: Eye window for uplink 24: ________XXXXX___________________________
Data delay found: 30
14:05:14:setup_element:INFO: Eye window for uplink 25: __________XXXXX_________________________
Data delay found: 32
14:05:14:setup_element:INFO: Eye window for uplink 26: _________XXXXX__________________________
Data delay found: 31
14:05:14:setup_element:INFO: Eye window for uplink 27: ____________XXXXX_______________________
Data delay found: 34
14:05:14:setup_element:INFO: Eye window for uplink 28: ___________XXXXXX_______________________
Data delay found: 33
14:05:14:setup_element:INFO: Eye window for uplink 29: ______________XXXXX_____________________
Data delay found: 36
14:05:14:setup_element:INFO: Eye window for uplink 30: _____________XXXXXX_____________________
Data delay found: 35
14:05:14:setup_element:INFO: Eye window for uplink 31: _____________XXXXXX_____________________
Data delay found: 35
14:05:14:setup_element:INFO: Setting the data phase to 30 for uplink 24
14:05:14:setup_element:INFO: Setting the data phase to 32 for uplink 25
14:05:14:setup_element:INFO: Setting the data phase to 31 for uplink 26
14:05:14:setup_element:INFO: Setting the data phase to 34 for uplink 27
14:05:14:setup_element:INFO: Setting the data phase to 33 for uplink 28
14:05:14:setup_element:INFO: Setting the data phase to 36 for uplink 29
14:05:14:setup_element:INFO: Setting the data phase to 35 for uplink 30
14:05:14:setup_element:INFO: Setting the data phase to 35 for uplink 31
14:05:14:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 2
Uplinks: [24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 29
Window Length: 72
Eye Windows:
Uplink 24: __________________________________________________________________XXXXXXXX______
Uplink 25: __________________________________________________________________XXXXXXXX______
Uplink 26: __________________________________________________________________XXXXXXXX______
Uplink 27: __________________________________________________________________XXXXXXXX______
Uplink 28: ___________________________________________________________________XXXXXXX______
Uplink 29: ___________________________________________________________________XXXXXXX______
Uplink 30: ___________________________________________________________________XXXXXXX______
Uplink 31: ___________________________________________________________________XXXXXXX______
Data phase characteristics:
Uplink 24:
Optimal Phase: 30
Window Length: 35
Eye Window: ________XXXXX___________________________
Uplink 25:
Optimal Phase: 32
Window Length: 35
Eye Window: __________XXXXX_________________________
Uplink 26:
Optimal Phase: 31
Window Length: 35
Eye Window: _________XXXXX__________________________
Uplink 27:
Optimal Phase: 34
Window Length: 35
Eye Window: ____________XXXXX_______________________
Uplink 28:
Optimal Phase: 33
Window Length: 34
Eye Window: ___________XXXXXX_______________________
Uplink 29:
Optimal Phase: 36
Window Length: 35
Eye Window: ______________XXXXX_____________________
Uplink 30:
Optimal Phase: 35
Window Length: 34
Eye Window: _____________XXXXXX_____________________
Uplink 31:
Optimal Phase: 35
Window Length: 34
Eye Window: _____________XXXXXX_____________________
]
14:05:14:setup_element:INFO: Beginning SMX ASICs map scan
14:05:14:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
14:05:14:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
14:05:14:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
14:05:14:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
14:05:14:uplink:INFO: Setting uplinks mask [24, 25, 26, 27, 28, 29, 30, 31]
14:05:14:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 30
14:05:14:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 31
14:05:14:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28
14:05:14:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 29
14:05:15:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26
14:05:15:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 27
14:05:15:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 24
14:05:15:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 25
14:05:16:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 2
Uplinks: [24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map:
ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
Clock Phase Characteristic:
Optimal Phase: 29
Window Length: 72
Eye Windows:
Uplink 24: __________________________________________________________________XXXXXXXX______
Uplink 25: __________________________________________________________________XXXXXXXX______
Uplink 26: __________________________________________________________________XXXXXXXX______
Uplink 27: __________________________________________________________________XXXXXXXX______
Uplink 28: ___________________________________________________________________XXXXXXX______
Uplink 29: ___________________________________________________________________XXXXXXX______
Uplink 30: ___________________________________________________________________XXXXXXX______
Uplink 31: ___________________________________________________________________XXXXXXX______
Data phase characteristics:
Uplink 24:
Optimal Phase: 30
Window Length: 35
Eye Window: ________XXXXX___________________________
Uplink 25:
Optimal Phase: 32
Window Length: 35
Eye Window: __________XXXXX_________________________
Uplink 26:
Optimal Phase: 31
Window Length: 35
Eye Window: _________XXXXX__________________________
Uplink 27:
Optimal Phase: 34
Window Length: 35
Eye Window: ____________XXXXX_______________________
Uplink 28:
Optimal Phase: 33
Window Length: 34
Eye Window: ___________XXXXXX_______________________
Uplink 29:
Optimal Phase: 36
Window Length: 35
Eye Window: ______________XXXXX_____________________
Uplink 30:
Optimal Phase: 35
Window Length: 34
Eye Window: _____________XXXXXX_____________________
Uplink 31:
Optimal Phase: 35
Window Length: 34
Eye Window: _____________XXXXXX_____________________
14:05:16:setup_element:INFO: Performing Elink synchronization
14:05:16:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
14:05:16:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
14:05:16:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
14:05:16:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
14:05:16:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2
14:05:16:uplink:INFO: Enabling uplinks [24, 25, 26, 27, 28, 29, 30, 31]
14:05:17:ST3_emu:INFO: Number of chips: 4
addr | upli | dwnli | grp | uplinks | uplinks_map
1 | [0] | 2 | 0 | [30] | [(0, 30), (1, 31)]
3 | [0] | 2 | 0 | [28] | [(0, 28), (1, 29)]
5 | [0] | 2 | 0 | [26] | [(0, 26), (1, 27)]
7 | [0] | 2 | 0 | [24] | [(0, 24), (1, 25)]
14:05:17:febtest:INFO: Init all SMX (CSA): 30
14:05:24:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:05:24:febtest:INFO: 30-01 | XA-000-08-002-002-006-103-09 | 47.3 | 1124.0
14:05:25:febtest:INFO: 28-03 | XA-000-08-002-002-006-112-14 | 34.6 | 1165.6
14:05:25:febtest:INFO: 26-05 | XA-000-08-002-002-006-109-09 | 37.7 | 1147.8
14:05:25:febtest:INFO: 24-07 | XA-000-08-002-002-006-105-09 | 40.9 | 1135.9
14:05:26:febtest:INFO: Set all CSA to ZERO
FEB type: B FEB_A: 0 FEB_B: 1
14:05:28:ST3_smx:INFO: chip: 30-1 47.250730 C 1141.874115 mV
14:05:28:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:05:28:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:05:28:ST3_smx:INFO: Electrons
14:05:28:ST3_smx:INFO: # loops 0
14:05:30:ST3_smx:INFO: # loops 1
14:05:31:ST3_smx:INFO: # loops 2
14:05:33:ST3_smx:INFO: Total # of broken channels: 0
14:05:33:ST3_smx:INFO: List of broken channels: []
14:05:33:ST3_smx:INFO: Total # of broken channels: 0
14:05:33:ST3_smx:INFO: List of broken channels: []
14:05:35:ST3_smx:INFO: chip: 28-3 34.556970 C 1177.390875 mV
14:05:35:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:05:35:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:05:35:ST3_smx:INFO: Electrons
14:05:35:ST3_smx:INFO: # loops 0
14:05:36:ST3_smx:INFO: # loops 1
14:05:38:ST3_smx:INFO: # loops 2
14:05:39:ST3_smx:INFO: Total # of broken channels: 0
14:05:39:ST3_smx:INFO: List of broken channels: []
14:05:39:ST3_smx:INFO: Total # of broken channels: 0
14:05:39:ST3_smx:INFO: List of broken channels: []
14:05:41:ST3_smx:INFO: chip: 26-5 37.726682 C 1159.654860 mV
14:05:41:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:05:41:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:05:41:ST3_smx:INFO: Electrons
14:05:41:ST3_smx:INFO: # loops 0
14:05:43:ST3_smx:INFO: # loops 1
14:05:44:ST3_smx:INFO: # loops 2
14:05:46:ST3_smx:INFO: Total # of broken channels: 0
14:05:46:ST3_smx:INFO: List of broken channels: []
14:05:46:ST3_smx:INFO: Total # of broken channels: 0
14:05:46:ST3_smx:INFO: List of broken channels: []
14:05:48:ST3_smx:INFO: chip: 24-7 40.898880 C 1147.806000 mV
14:05:48:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:05:48:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:05:48:ST3_smx:INFO: Electrons
14:05:48:ST3_smx:INFO: # loops 0
14:05:49:ST3_smx:INFO: # loops 1
14:05:51:ST3_smx:INFO: # loops 2
14:05:52:ST3_smx:INFO: Total # of broken channels: 0
14:05:52:ST3_smx:INFO: List of broken channels: []
14:05:52:ST3_smx:INFO: Total # of broken channels: 0
14:05:52:ST3_smx:INFO: List of broken channels: []
14:05:53:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:05:53:febtest:INFO: 30-01 | XA-000-08-002-002-006-103-09 | 47.3 | 1165.6
14:05:53:febtest:INFO: 28-03 | XA-000-08-002-002-006-112-14 | 34.6 | 1201.0
14:05:53:febtest:INFO: 26-05 | XA-000-08-002-002-006-109-09 | 37.7 | 1177.4
14:05:53:febtest:INFO: 24-07 | XA-000-08-002-002-006-105-09 | 44.1 | 1165.6
############################################################
# S U M M A R Y #
############################################################
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-Microcable
TEST_DATE : 24_06_04-14_05_06
OPERATOR : Oleksandr S.;
SITE : GSI | SETUP : GSI_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 2184| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_B
------------------------------------------------------------
------------------------------------------------------------
VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '0.7934', '1.853', '1.1420']
VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '0.9929', '1.850', '1.3020']
VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '0.9835', '1.850', '0.2681']