FEB_2244    12.09.24 10:45:52

TextEdit.txt
            10:45:52:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
10:45:52:ST3_Shared:INFO:	                       FEB-Microcable                       
10:45:52:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
10:45:52:febtest:INFO:	Testing FEB with SN 2244
10:45:54:smx_tester:INFO:	Scanning setup
10:45:54:elinks:INFO:	Disabling clock on downlink 0
10:45:54:elinks:INFO:	Disabling clock on downlink 1
10:45:54:elinks:INFO:	Disabling clock on downlink 2
10:45:54:elinks:INFO:	Disabling clock on downlink 3
10:45:54:elinks:INFO:	Disabling clock on downlink 4
10:45:54:setup_element:INFO:	Checking SOS, encoding_mode: SOS
10:45:54:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
10:45:54:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
10:45:54:elinks:INFO:	Disabling clock on downlink 0
10:45:54:elinks:INFO:	Disabling clock on downlink 1
10:45:54:elinks:INFO:	Disabling clock on downlink 2
10:45:54:elinks:INFO:	Disabling clock on downlink 3
10:45:54:elinks:INFO:	Disabling clock on downlink 4
10:45:54:setup_element:INFO:	Checking SOS, encoding_mode: SOS
10:45:54:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
10:45:54:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
10:45:54:elinks:INFO:	Disabling clock on downlink 0
10:45:54:elinks:INFO:	Disabling clock on downlink 1
10:45:54:elinks:INFO:	Disabling clock on downlink 2
10:45:54:elinks:INFO:	Disabling clock on downlink 3
10:45:54:elinks:INFO:	Disabling clock on downlink 4
10:45:54:setup_element:INFO:	Checking SOS, encoding_mode: SOS
10:45:54:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
10:45:54:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 16
10:45:54:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 17
10:45:54:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 18
10:45:54:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 19
10:45:54:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 20
10:45:54:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 21
10:45:54:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 22
10:45:54:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 23
10:45:54:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 24
10:45:54:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 25
10:45:54:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 26
10:45:54:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 27
10:45:54:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 28
10:45:54:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 29
10:45:54:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 30
10:45:54:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 31
10:45:54:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
10:45:54:elinks:INFO:	Disabling clock on downlink 0
10:45:54:elinks:INFO:	Disabling clock on downlink 1
10:45:54:elinks:INFO:	Disabling clock on downlink 2
10:45:54:elinks:INFO:	Disabling clock on downlink 3
10:45:54:elinks:INFO:	Disabling clock on downlink 4
10:45:54:setup_element:INFO:	Checking SOS, encoding_mode: SOS
10:45:54:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
10:45:54:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
10:45:54:elinks:INFO:	Disabling clock on downlink 0
10:45:54:elinks:INFO:	Disabling clock on downlink 1
10:45:54:elinks:INFO:	Disabling clock on downlink 2
10:45:54:elinks:INFO:	Disabling clock on downlink 3
10:45:54:elinks:INFO:	Disabling clock on downlink 4
10:45:54:setup_element:INFO:	Checking SOS, encoding_mode: SOS
10:45:54:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [4]
10:45:54:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
10:45:54:setup_element:INFO:	Scanning clock phase
10:45:54:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
10:45:54:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
10:45:55:setup_element:INFO:	Clock phase scan results for group 0, downlink 2
10:45:55:setup_element:INFO:	Eye window for uplink 16: __________________________________________________________________XXXXXXX_______
Clock Delay: 29
10:45:55:setup_element:INFO:	Eye window for uplink 17: __________________________________________________________________XXXXXXX_______
Clock Delay: 29
10:45:55:setup_element:INFO:	Eye window for uplink 18: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
10:45:55:setup_element:INFO:	Eye window for uplink 19: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
10:45:55:setup_element:INFO:	Eye window for uplink 20: ________________________________________________________________________________
Clock Delay: 40
10:45:55:setup_element:INFO:	Eye window for uplink 21: ________________________________________________________________________________
Clock Delay: 40
10:45:55:setup_element:INFO:	Eye window for uplink 22: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
10:45:55:setup_element:INFO:	Eye window for uplink 23: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
10:45:55:setup_element:INFO:	Eye window for uplink 24: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
10:45:55:setup_element:INFO:	Eye window for uplink 25: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
10:45:55:setup_element:INFO:	Eye window for uplink 26: ________________________________________________________________________________
Clock Delay: 40
10:45:55:setup_element:INFO:	Eye window for uplink 27: ________________________________________________________________________________
Clock Delay: 40
10:45:55:setup_element:INFO:	Eye window for uplink 28: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
10:45:55:setup_element:INFO:	Eye window for uplink 29: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
10:45:55:setup_element:INFO:	Eye window for uplink 30: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
10:45:55:setup_element:INFO:	Eye window for uplink 31: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
10:45:55:setup_element:INFO:	Setting the clock phase to 31 for group 0, downlink 2
10:45:55:setup_element:INFO:	Scanning data phases
10:45:55:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
10:45:55:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
10:46:00:setup_element:INFO:	Data phase scan results for group 0, downlink 2
10:46:00:setup_element:INFO:	Eye window for uplink 16: ______________________________XXXXX_____
Data delay found: 12
10:46:00:setup_element:INFO:	Eye window for uplink 17: ____________________________XXXXXX______
Data delay found: 10
10:46:00:setup_element:INFO:	Eye window for uplink 18: __________________________________XXXXX_
Data delay found: 16
10:46:00:setup_element:INFO:	Eye window for uplink 19: ________________________________XXXXX___
Data delay found: 14
10:46:00:setup_element:INFO:	Eye window for uplink 20: XXX___________________________________XX
Data delay found: 20
10:46:00:setup_element:INFO:	Eye window for uplink 21: XX__________________________________XXXX
Data delay found: 18
10:46:00:setup_element:INFO:	Eye window for uplink 22: XX_________________________________XXXXX
Data delay found: 18
10:46:00:setup_element:INFO:	Eye window for uplink 23: XXXXX____________________________XXXXXXX
Data delay found: 18
10:46:00:setup_element:INFO:	Eye window for uplink 24: _________XXXXX__________________________
Data delay found: 31
10:46:00:setup_element:INFO:	Eye window for uplink 25: ___________XXXXX________________________
Data delay found: 33
10:46:00:setup_element:INFO:	Eye window for uplink 26: __________XXXXX_________________________
Data delay found: 32
10:46:00:setup_element:INFO:	Eye window for uplink 27: _____________XXXXXX_____________________
Data delay found: 35
10:46:00:setup_element:INFO:	Eye window for uplink 28: __________________XXXX__________________
Data delay found: 39
10:46:00:setup_element:INFO:	Eye window for uplink 29: ____________________XXXXXX______________
Data delay found: 2
10:46:00:setup_element:INFO:	Eye window for uplink 30: _________________XXXXXX_________________
Data delay found: 39
10:46:00:setup_element:INFO:	Eye window for uplink 31: _________________XXXXXXX________________
Data delay found: 0
10:46:00:setup_element:INFO:	Setting the data phase to 12 for uplink 16
10:46:00:setup_element:INFO:	Setting the data phase to 10 for uplink 17
10:46:00:setup_element:INFO:	Setting the data phase to 16 for uplink 18
10:46:00:setup_element:INFO:	Setting the data phase to 14 for uplink 19
10:46:00:setup_element:INFO:	Setting the data phase to 20 for uplink 20
10:46:00:setup_element:INFO:	Setting the data phase to 18 for uplink 21
10:46:00:setup_element:INFO:	Setting the data phase to 18 for uplink 22
10:46:00:setup_element:INFO:	Setting the data phase to 18 for uplink 23
10:46:00:setup_element:INFO:	Setting the data phase to 31 for uplink 24
10:46:00:setup_element:INFO:	Setting the data phase to 33 for uplink 25
10:46:00:setup_element:INFO:	Setting the data phase to 32 for uplink 26
10:46:00:setup_element:INFO:	Setting the data phase to 35 for uplink 27
10:46:00:setup_element:INFO:	Setting the data phase to 39 for uplink 28
10:46:00:setup_element:INFO:	Setting the data phase to 2 for uplink 29
10:46:00:setup_element:INFO:	Setting the data phase to 39 for uplink 30
10:46:00:setup_element:INFO:	Setting the data phase to 0 for uplink 31
10:46:00:setup_element:INFO:	Beginning SMX ASICs map scan
10:46:00:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
10:46:00:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
10:46:00:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
10:46:00:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
10:46:00:uplink:INFO:	Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
10:46:00:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 0, uplink 23
10:46:00:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 1, uplink 22
10:46:01:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 0, uplink 30
10:46:01:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 1, uplink 31
10:46:01:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 0, uplink 21
10:46:01:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 1, uplink 20
10:46:01:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 0, uplink 28
10:46:01:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 1, uplink 29
10:46:01:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 0, uplink 19
10:46:01:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 1, uplink 18
10:46:01:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 0, uplink 26
10:46:01:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 1, uplink 27
10:46:02:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 0, uplink 17
10:46:02:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 1, uplink 16
10:46:02:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 0, uplink 24
10:46:02:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 1, uplink 25
10:46:03:setup_element:INFO:	Performing Elink synchronization
10:46:03:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
10:46:03:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
10:46:03:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
10:46:03:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
10:46:03:setup_element:INFO:	Writing SMX Elink masks for group 0, downlink 2
10:46:03:uplink:INFO:	Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
 0   | [0]  |   2   |  0  |  [23]   |    2    | [(0, 23), (1, 22)]
 1   | [0]  |   2   |  0  |  [30]   |    2    | [(0, 30), (1, 31)]
 2   | [0]  |   2   |  0  |  [21]   |    2    | [(0, 21), (1, 20)]
 3   | [0]  |   2   |  0  |  [28]   |    2    | [(0, 28), (1, 29)]
 4   | [0]  |   2   |  0  |  [19]   |    2    | [(0, 19), (1, 18)]
 5   | [0]  |   2   |  0  |  [26]   |    2    | [(0, 26), (1, 27)]
 6   | [0]  |   2   |  0  |  [17]   |    2    | [(0, 17), (1, 16)]
 7   | [0]  |   2   |  0  |  [24]   |    2    | [(0, 24), (1, 25)]
|_________________________________________________________________________|
10:46:04:ST3_emu_feb:DEBUG:	Chip address:  	0x0
10:46:04:ST3_emu_feb:DEBUG:	Chip address:  	0x1
10:46:04:ST3_emu_feb:DEBUG:	Chip address:  	0x2
10:46:04:ST3_emu_feb:DEBUG:	Chip address:  	0x3
10:46:04:ST3_emu_feb:DEBUG:	Chip address:  	0x4
10:46:04:ST3_emu_feb:DEBUG:	Chip address:  	0x5
10:46:04:ST3_emu_feb:DEBUG:	Chip address:  	0x6
10:46:04:ST3_emu_feb:DEBUG:	Chip address:  	0x7
10:46:04:febtest:INFO:	Init all SMX (CSA): 30
10:46:18:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
10:46:18:febtest:INFO:	23-00 | XA-000-08-002-003-007-103-12 |  34.6 | 1165.6
10:46:18:febtest:INFO:	30-01 | XA-000-09-004-003-013-011-02 |  31.4 | 1159.7
10:46:18:febtest:INFO:	21-02 | XA-000-09-004-003-015-011-01 |  28.2 | 1177.4
10:46:19:febtest:INFO:	28-03 | XA-000-09-004-003-017-010-04 |  25.1 | 1177.4
10:46:19:febtest:INFO:	19-04 | XA-000-08-002-003-007-100-12 |  44.1 | 1135.9
10:46:19:febtest:INFO:	26-05 | XA-000-09-004-003-018-012-10 |  28.2 | 1171.5
10:46:19:febtest:INFO:	17-06 | XA-098-08-002-003-007-021-08 |  63.2 | 1094.2
10:46:20:febtest:INFO:	24-07 | XA-000-09-004-003-014-011-12 |  31.4 | 1159.7
10:46:21:febtest:INFO:	Set all CSA to ZERO
FEB type: B FEB_A: 0 FEB_B: 1
10:46:23:ST3_smx:INFO:	chip: 23-0 	 34.556970 C 	 1177.390875 mV
10:46:23:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
10:46:23:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
10:46:23:ST3_smx:INFO:		Electrons
10:46:23:ST3_smx:INFO:	# loops 0
10:46:24:ST3_smx:INFO:	# loops 1
10:46:26:ST3_smx:INFO:	# loops 2
10:46:28:ST3_smx:INFO:	Total # of broken channels: 0
10:46:28:ST3_smx:INFO:	List of broken channels: []
10:46:28:ST3_smx:INFO:	Total # of broken channels: 9
10:46:28:ST3_smx:INFO:	List of broken channels: [49, 51, 67, 89, 93, 101, 109, 113, 121]
10:46:29:ST3_smx:INFO:	chip: 30-1 	 31.389742 C 	 1171.483840 mV
10:46:29:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
10:46:29:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
10:46:29:ST3_smx:INFO:		Electrons
10:46:29:ST3_smx:INFO:	# loops 0
10:46:31:ST3_smx:INFO:	# loops 1
10:46:32:ST3_smx:INFO:	# loops 2
10:46:34:ST3_smx:INFO:	Total # of broken channels: 0
10:46:34:ST3_smx:INFO:	List of broken channels: []
10:46:34:ST3_smx:INFO:	Total # of broken channels: 0
10:46:34:ST3_smx:INFO:	List of broken channels: []
10:46:36:ST3_smx:INFO:	chip: 21-2 	 28.225000 C 	 1189.190035 mV
10:46:36:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
10:46:36:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
10:46:36:ST3_smx:INFO:		Electrons
10:46:36:ST3_smx:INFO:	# loops 0
10:46:38:ST3_smx:INFO:	# loops 1
10:46:39:ST3_smx:INFO:	# loops 2
10:46:41:ST3_smx:INFO:	Total # of broken channels: 0
10:46:41:ST3_smx:INFO:	List of broken channels: []
10:46:41:ST3_smx:INFO:	Total # of broken channels: 4
10:46:41:ST3_smx:INFO:	List of broken channels: [5, 9, 103, 107]
10:46:42:ST3_smx:INFO:	chip: 28-3 	 25.062742 C 	 1189.190035 mV
10:46:42:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
10:46:42:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
10:46:42:ST3_smx:INFO:		Electrons
10:46:42:ST3_smx:INFO:	# loops 0
10:46:44:ST3_smx:INFO:	# loops 1
10:46:45:ST3_smx:INFO:	# loops 2
10:46:47:ST3_smx:INFO:	Total # of broken channels: 0
10:46:47:ST3_smx:INFO:	List of broken channels: []
10:46:47:ST3_smx:INFO:	Total # of broken channels: 1
10:46:47:ST3_smx:INFO:	List of broken channels: [124]
10:46:49:ST3_smx:INFO:	chip: 19-4 	 47.250730 C 	 1147.806000 mV
10:46:49:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
10:46:49:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
10:46:49:ST3_smx:INFO:		Electrons
10:46:49:ST3_smx:INFO:	# loops 0
10:46:50:ST3_smx:INFO:	# loops 1
10:46:52:ST3_smx:INFO:	# loops 2
10:46:54:ST3_smx:INFO:	Total # of broken channels: 0
10:46:54:ST3_smx:INFO:	List of broken channels: []
10:46:54:ST3_smx:INFO:	Total # of broken channels: 21
10:46:54:ST3_smx:INFO:	List of broken channels: [0, 2, 4, 6, 8, 53, 55, 57, 59, 61, 63, 67, 69, 73, 75, 77, 79, 83, 85, 113, 115]
10:46:55:ST3_smx:INFO:	chip: 26-5 	 28.225000 C 	 1183.292940 mV
10:46:55:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
10:46:55:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
10:46:55:ST3_smx:INFO:		Electrons
10:46:55:ST3_smx:INFO:	# loops 0
10:46:57:ST3_smx:INFO:	# loops 1
10:46:58:ST3_smx:INFO:	# loops 2
10:47:00:ST3_smx:INFO:	Total # of broken channels: 0
10:47:00:ST3_smx:INFO:	List of broken channels: []
10:47:00:ST3_smx:INFO:	Total # of broken channels: 21
10:47:00:ST3_smx:INFO:	List of broken channels: [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38, 40]
10:47:02:ST3_smx:INFO:	chip: 17-6 	 63.173842 C 	 1106.178435 mV
10:47:02:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
10:47:02:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
10:47:02:ST3_smx:INFO:		Electrons
10:47:02:ST3_smx:INFO:	# loops 0
10:47:03:ST3_smx:INFO:	# loops 1
10:47:05:ST3_smx:INFO:	# loops 2
10:47:07:ST3_smx:INFO:	Total # of broken channels: 0
10:47:07:ST3_smx:INFO:	List of broken channels: []
10:47:07:ST3_smx:INFO:	Total # of broken channels: 0
10:47:07:ST3_smx:INFO:	List of broken channels: []
10:47:08:ST3_smx:INFO:	chip: 24-7 	 34.556970 C 	 1165.571835 mV
10:47:08:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
10:47:08:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
10:47:08:ST3_smx:INFO:		Electrons
10:47:08:ST3_smx:INFO:	# loops 0
10:47:10:ST3_smx:INFO:	# loops 1
10:47:12:ST3_smx:INFO:	# loops 2
10:47:13:ST3_smx:INFO:	Total # of broken channels: 1
10:47:13:ST3_smx:INFO:	List of broken channels: [17]
10:47:13:ST3_smx:INFO:	Total # of broken channels: 2
10:47:13:ST3_smx:INFO:	List of broken channels: [124, 126]
10:47:13:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
10:47:14:febtest:INFO:	23-00 | XA-000-08-002-003-007-103-12 |  34.6 | 1195.1
10:47:14:febtest:INFO:	30-01 | XA-000-09-004-003-013-011-02 |  31.4 | 1195.1
10:47:14:febtest:INFO:	21-02 | XA-000-09-004-003-015-011-01 |  28.2 | 1212.7
10:47:14:febtest:INFO:	28-03 | XA-000-09-004-003-017-010-04 |  25.1 | 1206.9
10:47:15:febtest:INFO:	19-04 | XA-000-08-002-003-007-100-12 |  47.3 | 1171.5
10:47:15:febtest:INFO:	26-05 | XA-000-09-004-003-018-012-10 |  31.4 | 1201.0
10:47:15:febtest:INFO:	17-06 | XA-098-08-002-003-007-021-08 |  66.4 | 1124.0
10:47:15:febtest:INFO:	24-07 | XA-000-09-004-003-014-011-12 |  34.6 | 1183.3
############################################################
#                   S U M M A R Y                          #
############################################################
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

############################################################
#                   S U M M A R Y                          #
############################################################
TEST_NAME : FEB-Microcable
TEST_DATE : 24_09_12-10_45_52
OPERATOR  : Oleksandr S.; 
SITE : GSI | SETUP : GSI_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 2244| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_B
------------------------------------------------------------
------------------------------------------------------------
VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.5090', '1.848', '2.5020']
VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '2.0100', '1.850', '2.5590']
VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.9690', '1.850', '0.5225']