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FEB_2261 07.11.24 11:30:17
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11:30:17:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
11:30:17:ST3_Shared:INFO: FEB-Sensor
11:30:17:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
11:30:22:ST3_ModuleSelector:DEBUG: M3DR2B2000122A2
11:30:22:ST3_ModuleSelector:DEBUG: L3DR200012
11:30:22:ST3_ModuleSelector:DEBUG: 08282
11:30:22:ST3_ModuleSelector:DEBUG: 62x42
11:30:22:ST3_ModuleSelector:DEBUG: A
11:30:22:ST3_ModuleSelector:DEBUG: M3DR2B2000122A2
11:30:22:ST3_ModuleSelector:DEBUG: L3DR200012
11:30:22:ST3_ModuleSelector:DEBUG: 08282
11:30:22:ST3_ModuleSelector:DEBUG: 62x42
11:30:22:ST3_ModuleSelector:DEBUG: A
11:30:44:ST3_ModuleSelector:INFO: M3DR2B2000122A2
11:30:44:ST3_ModuleSelector:INFO: 08282
11:30:44:febtest:INFO: Testing FEB with SN 2261
11:30:46:smx_tester:INFO: Scanning setup
11:30:46:elinks:INFO: Disabling clock on downlink 0
11:30:46:elinks:INFO: Disabling clock on downlink 1
11:30:46:elinks:INFO: Disabling clock on downlink 2
11:30:46:elinks:INFO: Disabling clock on downlink 3
11:30:46:elinks:INFO: Disabling clock on downlink 4
11:30:46:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:30:46:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
11:30:46:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:30:46:elinks:INFO: Disabling clock on downlink 0
11:30:46:elinks:INFO: Disabling clock on downlink 1
11:30:46:elinks:INFO: Disabling clock on downlink 2
11:30:46:elinks:INFO: Disabling clock on downlink 3
11:30:46:elinks:INFO: Disabling clock on downlink 4
11:30:46:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:30:46:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
11:30:46:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:30:46:elinks:INFO: Disabling clock on downlink 0
11:30:46:elinks:INFO: Disabling clock on downlink 1
11:30:46:elinks:INFO: Disabling clock on downlink 2
11:30:46:elinks:INFO: Disabling clock on downlink 3
11:30:46:elinks:INFO: Disabling clock on downlink 4
11:30:46:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:30:46:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
11:30:46:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 16
11:30:46:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 17
11:30:46:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 18
11:30:46:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 19
11:30:46:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 20
11:30:46:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 21
11:30:46:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 22
11:30:46:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 23
11:30:46:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24
11:30:46:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25
11:30:46:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26
11:30:46:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27
11:30:46:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28
11:30:46:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29
11:30:46:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30
11:30:46:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31
11:30:46:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:30:46:elinks:INFO: Disabling clock on downlink 0
11:30:46:elinks:INFO: Disabling clock on downlink 1
11:30:46:elinks:INFO: Disabling clock on downlink 2
11:30:46:elinks:INFO: Disabling clock on downlink 3
11:30:46:elinks:INFO: Disabling clock on downlink 4
11:30:46:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:30:46:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
11:30:46:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:30:46:elinks:INFO: Disabling clock on downlink 0
11:30:46:elinks:INFO: Disabling clock on downlink 1
11:30:46:elinks:INFO: Disabling clock on downlink 2
11:30:46:elinks:INFO: Disabling clock on downlink 3
11:30:47:elinks:INFO: Disabling clock on downlink 4
11:30:47:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:30:47:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
11:30:47:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
==============================================OOO==============================================
11:30:47:setup_element:INFO: Scanning clock phase
11:30:47:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
11:30:47:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
11:30:47:setup_element:INFO: Clock phase scan results for group 0, downlink 2
11:30:47:setup_element:INFO: Eye window for uplink 16: ______________________________________________________________________XXXXXXX___
Clock Delay: 33
11:30:47:setup_element:INFO: Eye window for uplink 17: ______________________________________________________________________XXXXXXX___
Clock Delay: 33
11:30:47:setup_element:INFO: Eye window for uplink 18: ______________________________________________________________________XXXXXXX___
Clock Delay: 33
11:30:47:setup_element:INFO: Eye window for uplink 19: ______________________________________________________________________XXXXXXX___
Clock Delay: 33
11:30:47:setup_element:INFO: Eye window for uplink 20: ________________________________________________________________________________
Clock Delay: 40
11:30:47:setup_element:INFO: Eye window for uplink 21: ________________________________________________________________________________
Clock Delay: 40
11:30:47:setup_element:INFO: Eye window for uplink 22: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
11:30:47:setup_element:INFO: Eye window for uplink 23: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
11:30:47:setup_element:INFO: Eye window for uplink 24: ______________________________________________________________________XXXXXXX___
Clock Delay: 33
11:30:47:setup_element:INFO: Eye window for uplink 25: ______________________________________________________________________XXXXXXX___
Clock Delay: 33
11:30:47:setup_element:INFO: Eye window for uplink 26: _____________________________________________________________________XXXXXXXXX__
Clock Delay: 33
11:30:47:setup_element:INFO: Eye window for uplink 27: _____________________________________________________________________XXXXXXXXX__
Clock Delay: 33
11:30:47:setup_element:INFO: Eye window for uplink 28: ________________________________________________________________________________
Clock Delay: 40
11:30:47:setup_element:INFO: Eye window for uplink 29: ________________________________________________________________________________
Clock Delay: 40
11:30:47:setup_element:INFO: Eye window for uplink 30: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
11:30:47:setup_element:INFO: Eye window for uplink 31: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
11:30:47:setup_element:INFO: Setting the clock phase to 33 for group 0, downlink 2
==============================================OOO==============================================
11:30:47:setup_element:INFO: Scanning data phases
11:30:47:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
11:30:47:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
11:30:53:setup_element:INFO: Data phase scan results for group 0, downlink 2
11:30:53:setup_element:INFO: Eye window for uplink 16: XX__________________________________XXXX
Data delay found: 18
11:30:53:setup_element:INFO: Eye window for uplink 17: __________________________________XXXXX_
Data delay found: 16
11:30:53:setup_element:INFO: Eye window for uplink 18: X_________________________________XXXXXX
Data delay found: 17
11:30:53:setup_element:INFO: Eye window for uplink 19: ________________________________XXXXXX__
Data delay found: 14
11:30:53:setup_element:INFO: Eye window for uplink 20: XX___________________________________XXX
Data delay found: 19
11:30:53:setup_element:INFO: Eye window for uplink 21: X__________________________________XXXXX
Data delay found: 17
11:30:53:setup_element:INFO: Eye window for uplink 22: X__________________________________XXXX_
Data delay found: 17
11:30:53:setup_element:INFO: Eye window for uplink 23: XXXX____________________________XXXXXXXX
Data delay found: 17
11:30:53:setup_element:INFO: Eye window for uplink 24: _______XXXXXXX__________________________
Data delay found: 30
11:30:53:setup_element:INFO: Eye window for uplink 25: __________XXXXXX________________________
Data delay found: 32
11:30:53:setup_element:INFO: Eye window for uplink 26: ___________XXXXX_______________XXXXXXXXX
Data delay found: 23
11:30:53:setup_element:INFO: Eye window for uplink 27: _______________XXXX____________XXXXXXXXX
Data delay found: 7
11:30:53:setup_element:INFO: Eye window for uplink 28: ________________XXXXXX__________________
Data delay found: 38
11:30:53:setup_element:INFO: Eye window for uplink 29: __________________XXXXXXX_______________
Data delay found: 1
11:30:53:setup_element:INFO: Eye window for uplink 30: _________________XXXXXX_________________
Data delay found: 39
11:30:53:setup_element:INFO: Eye window for uplink 31: _________________XXXXXXX________________
Data delay found: 0
11:30:53:setup_element:INFO: Setting the data phase to 18 for uplink 16
11:30:53:setup_element:INFO: Setting the data phase to 16 for uplink 17
11:30:53:setup_element:INFO: Setting the data phase to 17 for uplink 18
11:30:53:setup_element:INFO: Setting the data phase to 14 for uplink 19
11:30:53:setup_element:INFO: Setting the data phase to 19 for uplink 20
11:30:53:setup_element:INFO: Setting the data phase to 17 for uplink 21
11:30:53:setup_element:INFO: Setting the data phase to 17 for uplink 22
11:30:53:setup_element:INFO: Setting the data phase to 17 for uplink 23
11:30:53:setup_element:INFO: Setting the data phase to 30 for uplink 24
11:30:53:setup_element:INFO: Setting the data phase to 32 for uplink 25
11:30:53:setup_element:INFO: Setting the data phase to 23 for uplink 26
11:30:53:setup_element:INFO: Setting the data phase to 7 for uplink 27
11:30:53:setup_element:INFO: Setting the data phase to 38 for uplink 28
11:30:53:setup_element:INFO: Setting the data phase to 1 for uplink 29
11:30:53:setup_element:INFO: Setting the data phase to 39 for uplink 30
11:30:53:setup_element:INFO: Setting the data phase to 0 for uplink 31
==============================================OOO==============================================
11:30:53:setup_element:INFO: Beginning SMX ASICs map scan
11:30:53:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
11:30:53:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
11:30:53:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
11:30:53:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
11:30:53:uplink:INFO: Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
11:30:53:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 23
11:30:53:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 22
11:30:53:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 30
11:30:53:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 31
11:30:53:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 21
11:30:53:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 20
11:30:53:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28
11:30:53:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 29
11:30:54:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 19
11:30:54:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 18
11:30:54:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26
11:30:54:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 27
11:30:54:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 17
11:30:54:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 16
11:30:54:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 24
11:30:54:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 25
11:30:55:ST3_emu:INFO:
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 23), (1, 22)
ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
ASIC address 0x2: (ASIC uplink, uplink): (0, 21), (1, 20)
ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
ASIC address 0x4: (ASIC uplink, uplink): (0, 19), (1, 18)
ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
ASIC address 0x6: (ASIC uplink, uplink): (0, 17), (1, 16)
ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
Clock Phase Characteristic:
Optimal Phase: 33
Window Length: 69
Eye Windows:
Uplink 16: ______________________________________________________________________XXXXXXX___
Uplink 17: ______________________________________________________________________XXXXXXX___
Uplink 18: ______________________________________________________________________XXXXXXX___
Uplink 19: ______________________________________________________________________XXXXXXX___
Uplink 20: ________________________________________________________________________________
Uplink 21: ________________________________________________________________________________
Uplink 22: ____________________________________________________________________XXXXXXXX____
Uplink 23: ____________________________________________________________________XXXXXXXX____
Uplink 24: ______________________________________________________________________XXXXXXX___
Uplink 25: ______________________________________________________________________XXXXXXX___
Uplink 26: _____________________________________________________________________XXXXXXXXX__
Uplink 27: _____________________________________________________________________XXXXXXXXX__
Uplink 28: ________________________________________________________________________________
Uplink 29: ________________________________________________________________________________
Uplink 30: _______________________________________________________________________XXXXXXXX_
Uplink 31: _______________________________________________________________________XXXXXXXX_
Data phase characteristics:
Uplink 16:
Optimal Phase: 18
Window Length: 34
Eye Window: XX__________________________________XXXX
Uplink 17:
Optimal Phase: 16
Window Length: 35
Eye Window: __________________________________XXXXX_
Uplink 18:
Optimal Phase: 17
Window Length: 33
Eye Window: X_________________________________XXXXXX
Uplink 19:
Optimal Phase: 14
Window Length: 34
Eye Window: ________________________________XXXXXX__
Uplink 20:
Optimal Phase: 19
Window Length: 35
Eye Window: XX___________________________________XXX
Uplink 21:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXXX
Uplink 22:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXX_
Uplink 23:
Optimal Phase: 17
Window Length: 28
Eye Window: XXXX____________________________XXXXXXXX
Uplink 24:
Optimal Phase: 30
Window Length: 33
Eye Window: _______XXXXXXX__________________________
Uplink 25:
Optimal Phase: 32
Window Length: 34
Eye Window: __________XXXXXX________________________
Uplink 26:
Optimal Phase: 23
Window Length: 15
Eye Window: ___________XXXXX_______________XXXXXXXXX
Uplink 27:
Optimal Phase: 7
Window Length: 15
Eye Window: _______________XXXX____________XXXXXXXXX
Uplink 28:
Optimal Phase: 38
Window Length: 34
Eye Window: ________________XXXXXX__________________
Uplink 29:
Optimal Phase: 1
Window Length: 33
Eye Window: __________________XXXXXXX_______________
Uplink 30:
Optimal Phase: 39
Window Length: 34
Eye Window: _________________XXXXXX_________________
Uplink 31:
Optimal Phase: 0
Window Length: 33
Eye Window: _________________XXXXXXX________________
==============================================OOO==============================================
11:30:55:setup_element:INFO: Performing Elink synchronization
11:30:55:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
11:30:55:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
11:30:55:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
11:30:55:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
==============================================OOO==============================================
11:30:55:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2
11:30:55:uplink:INFO: Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
==============================================OOO==============================================
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
0 | [0] | 2 | 0 | [23] | 2 | [(0, 23), (1, 22)]
1 | [0] | 2 | 0 | [30] | 2 | [(0, 30), (1, 31)]
2 | [0] | 2 | 0 | [21] | 2 | [(0, 21), (1, 20)]
3 | [0] | 2 | 0 | [28] | 2 | [(0, 28), (1, 29)]
4 | [0] | 2 | 0 | [19] | 2 | [(0, 19), (1, 18)]
5 | [0] | 2 | 0 | [26] | 2 | [(0, 26), (1, 27)]
6 | [0] | 2 | 0 | [17] | 2 | [(0, 17), (1, 16)]
7 | [0] | 2 | 0 | [24] | 2 | [(0, 24), (1, 25)]
|_________________________________________________________________________|
11:30:56:febtest:INFO: Init all SMX (CSA): 30
11:31:11:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
11:31:11:febtest:INFO: 23-00 | XA-000-09-004-004-016-018-04 | 34.6 | 1165.6
11:31:11:febtest:INFO: 30-01 | XA-000-09-004-004-016-011-03 | 47.3 | 1130.0
11:31:11:febtest:INFO: 21-02 | XA-000-09-004-004-016-013-03 | 47.3 | 1118.1
11:31:12:febtest:INFO: 28-03 | XA-000-09-004-004-017-020-09 | 25.1 | 1206.9
11:31:12:febtest:INFO: 19-04 | XA-000-09-004-004-016-012-03 | 34.6 | 1171.5
11:31:12:febtest:INFO: 26-05 | XA-000-09-004-004-017-019-09 | 31.4 | 1195.1
11:31:12:febtest:INFO: 17-06 | XA-000-09-004-004-017-012-14 | 37.7 | 1159.7
11:31:12:febtest:INFO: 24-07 | XA-000-09-004-004-018-012-00 | 44.1 | 1141.9
11:31:13:febtest:INFO: Set all CSA to ZERO
FEB type: B FEB_A: 0 FEB_B: 1
11:31:16:ST3_smx:INFO: chip: 23-0 34.556970 C 1177.390875 mV
11:31:16:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:31:16:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:31:16:ST3_smx:INFO: Electrons
11:31:16:ST3_smx:INFO: # loops 0
11:31:17:ST3_smx:INFO: # loops 1
11:31:19:ST3_smx:INFO: # loops 2
11:31:20:ST3_smx:INFO: # loops 3
11:31:22:ST3_smx:INFO: # loops 4
11:31:24:ST3_smx:INFO: Total # of broken channels: 0
11:31:24:ST3_smx:INFO: List of broken channels: []
11:31:24:ST3_smx:INFO: Total # of broken channels: 0
11:31:24:ST3_smx:INFO: List of broken channels: []
11:31:25:ST3_smx:INFO: chip: 30-1 47.250730 C 1141.874115 mV
11:31:25:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:31:25:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:31:25:ST3_smx:INFO: Electrons
11:31:25:ST3_smx:INFO: # loops 0
11:31:27:ST3_smx:INFO: # loops 1
11:31:29:ST3_smx:INFO: # loops 2
11:31:30:ST3_smx:INFO: # loops 3
11:31:32:ST3_smx:INFO: # loops 4
11:31:34:ST3_smx:INFO: Total # of broken channels: 0
11:31:34:ST3_smx:INFO: List of broken channels: []
11:31:34:ST3_smx:INFO: Total # of broken channels: 1
11:31:34:ST3_smx:INFO: List of broken channels: [0]
11:31:35:ST3_smx:INFO: chip: 21-2 50.430383 C 1129.995435 mV
11:31:35:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:31:35:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:31:35:ST3_smx:INFO: Electrons
11:31:35:ST3_smx:INFO: # loops 0
11:31:37:ST3_smx:INFO: # loops 1
11:31:39:ST3_smx:INFO: # loops 2
11:31:41:ST3_smx:INFO: # loops 3
11:31:42:ST3_smx:INFO: # loops 4
11:31:44:ST3_smx:INFO: Total # of broken channels: 4
11:31:44:ST3_smx:INFO: List of broken channels: [112, 114, 116, 120]
11:31:44:ST3_smx:INFO: Total # of broken channels: 4
11:31:44:ST3_smx:INFO: List of broken channels: [112, 114, 116, 120]
11:31:46:ST3_smx:INFO: chip: 28-3 25.062742 C 1218.600960 mV
11:31:46:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:31:46:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:31:46:ST3_smx:INFO: Electrons
11:31:46:ST3_smx:INFO: # loops 0
11:31:47:ST3_smx:INFO: # loops 1
11:31:49:ST3_smx:INFO: # loops 2
11:31:51:ST3_smx:INFO: # loops 3
11:31:52:ST3_smx:INFO: # loops 4
11:31:54:ST3_smx:INFO: Total # of broken channels: 0
11:31:54:ST3_smx:INFO: List of broken channels: []
11:31:54:ST3_smx:INFO: Total # of broken channels: 1
11:31:54:ST3_smx:INFO: List of broken channels: [0]
11:31:56:ST3_smx:INFO: chip: 19-4 34.556970 C 1177.390875 mV
11:31:56:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:31:56:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:31:56:ST3_smx:INFO: Electrons
11:31:56:ST3_smx:INFO: # loops 0
11:31:57:ST3_smx:INFO: # loops 1
11:31:59:ST3_smx:INFO: # loops 2
11:32:01:ST3_smx:INFO: # loops 3
11:32:02:ST3_smx:INFO: # loops 4
11:32:04:ST3_smx:INFO: Total # of broken channels: 0
11:32:04:ST3_smx:INFO: List of broken channels: []
11:32:04:ST3_smx:INFO: Total # of broken channels: 0
11:32:04:ST3_smx:INFO: List of broken channels: []
11:32:06:ST3_smx:INFO: chip: 26-5 28.225000 C 1212.728715 mV
11:32:06:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:32:06:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:32:06:ST3_smx:INFO: Electrons
11:32:06:ST3_smx:INFO: # loops 0
11:32:07:ST3_smx:INFO: # loops 1
11:32:09:ST3_smx:INFO: # loops 2
11:32:11:ST3_smx:INFO: # loops 3
11:32:12:ST3_smx:INFO: # loops 4
11:32:14:ST3_smx:INFO: Total # of broken channels: 0
11:32:14:ST3_smx:INFO: List of broken channels: []
11:32:14:ST3_smx:INFO: Total # of broken channels: 0
11:32:14:ST3_smx:INFO: List of broken channels: []
11:32:16:ST3_smx:INFO: chip: 17-6 40.898880 C 1165.571835 mV
11:32:16:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:32:16:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:32:16:ST3_smx:INFO: Electrons
11:32:16:ST3_smx:INFO: # loops 0
11:32:17:ST3_smx:INFO: # loops 1
11:32:19:ST3_smx:INFO: # loops 2
11:32:21:ST3_smx:INFO: # loops 3
11:32:22:ST3_smx:INFO: # loops 4
11:32:24:ST3_smx:INFO: Total # of broken channels: 1
11:32:24:ST3_smx:INFO: List of broken channels: [124]
11:32:24:ST3_smx:INFO: Total # of broken channels: 1
11:32:24:ST3_smx:INFO: List of broken channels: [124]
11:32:26:ST3_smx:INFO: chip: 24-7 47.250730 C 1147.806000 mV
11:32:26:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:32:26:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:32:26:ST3_smx:INFO: Electrons
11:32:26:ST3_smx:INFO: # loops 0
11:32:27:ST3_smx:INFO: # loops 1
11:32:29:ST3_smx:INFO: # loops 2
11:32:31:ST3_smx:INFO: # loops 3
11:32:32:ST3_smx:INFO: # loops 4
11:32:34:ST3_smx:INFO: Total # of broken channels: 0
11:32:34:ST3_smx:INFO: List of broken channels: []
11:32:34:ST3_smx:INFO: Total # of broken channels: 0
11:32:34:ST3_smx:INFO: List of broken channels: []
11:32:34:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
11:32:34:febtest:INFO: 23-00 | XA-000-09-004-004-016-018-04 | 37.7 | 1201.0
11:32:35:febtest:INFO: 30-01 | XA-000-09-004-004-016-011-03 | 47.3 | 1165.6
11:32:35:febtest:INFO: 21-02 | XA-000-09-004-004-016-013-03 | 50.4 | 1147.8
11:32:35:febtest:INFO: 28-03 | XA-000-09-004-004-017-020-09 | 25.1 | 1247.9
11:32:35:febtest:INFO: 19-04 | XA-000-09-004-004-016-012-03 | 37.7 | 1201.0
11:32:36:febtest:INFO: 26-05 | XA-000-09-004-004-017-019-09 | 28.2 | 1247.9
11:32:36:febtest:INFO: 17-06 | XA-000-09-004-004-017-012-14 | 40.9 | 1183.3
11:32:36:febtest:INFO: 24-07 | XA-000-09-004-004-018-012-00 | 47.3 | 1165.6
############################################################
# S U M M A R Y #
############################################################
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-Sensor
TEST_DATE : 24_11_07-11_30_17
OPERATOR : Oleksandr S.;
SITE : GSI | SETUP : GSI_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 2261| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_B
------------------------------------------------------------
SENSOR_NAME: 08282 | SIZE: 62x42 | GRADE: A
MODULE_NAME: M3DR2B2000122A2
LADDER_NAME: L3DR200012
------------------------------------------------------------
VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.451', '1.4610', '1.848', '1.7270']
VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '2.0260', '1.850', '2.5580']
VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.9790', '1.850', '0.5277']