09:24:42:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
09:24:42:ST3_Shared:INFO:	                         FEB-Sensor                         
09:24:42:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
09:24:49:ST3_ModuleSelector:DEBUG:	
09:24:49:ST3_ModuleSelector:DEBUG:	
09:24:49:ST3_ModuleSelector:DEBUG:	
09:24:49:ST3_ModuleSelector:DEBUG:	
09:24:49:ST3_ModuleSelector:DEBUG:	Unknown
09:24:55:ST3_ModuleSelector:DEBUG:	M3DR4T0000130B2
09:24:55:ST3_ModuleSelector:DEBUG:	L3DR400013
09:24:55:ST3_ModuleSelector:DEBUG:	03192
09:24:55:ST3_ModuleSelector:DEBUG:	62x42
09:24:55:ST3_ModuleSelector:DEBUG:	C
09:24:55:ST3_ModuleSelector:DEBUG:	M3DR4T0000130B2
09:24:55:ST3_ModuleSelector:DEBUG:	L3DR400013
09:24:55:ST3_ModuleSelector:DEBUG:	03192
09:24:55:ST3_ModuleSelector:DEBUG:	62x42
09:24:55:ST3_ModuleSelector:DEBUG:	C
09:25:01:ST3_ModuleSelector:INFO:	M3DR4T0000130B2
09:25:01:ST3_ModuleSelector:INFO:	03192
09:25:01:febtest:INFO:	Testing FEB with SN 2277
09:25:02:smx_tester:INFO:	Scanning setup
09:25:02:elinks:INFO:	Disabling clock on downlink 0
09:25:02:elinks:INFO:	Disabling clock on downlink 1
09:25:02:elinks:INFO:	Disabling clock on downlink 2
09:25:02:elinks:INFO:	Disabling clock on downlink 3
09:25:03:elinks:INFO:	Disabling clock on downlink 4
09:25:03:setup_element:INFO:	Checking SOS, encoding_mode: SOS
09:25:03:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
09:25:03:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
09:25:03:elinks:INFO:	Disabling clock on downlink 0
09:25:03:elinks:INFO:	Disabling clock on downlink 1
09:25:03:elinks:INFO:	Disabling clock on downlink 2
09:25:03:elinks:INFO:	Disabling clock on downlink 3
09:25:03:elinks:INFO:	Disabling clock on downlink 4
09:25:03:setup_element:INFO:	Checking SOS, encoding_mode: SOS
09:25:03:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
09:25:03:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
09:25:03:elinks:INFO:	Disabling clock on downlink 0
09:25:03:elinks:INFO:	Disabling clock on downlink 1
09:25:03:elinks:INFO:	Disabling clock on downlink 2
09:25:03:elinks:INFO:	Disabling clock on downlink 3
09:25:03:elinks:INFO:	Disabling clock on downlink 4
09:25:03:setup_element:INFO:	Checking SOS, encoding_mode: SOS
09:25:03:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
09:25:03:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 16
09:25:03:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 17
09:25:03:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 18
09:25:03:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 19
09:25:03:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 20
09:25:03:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 21
09:25:03:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 22
09:25:03:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 23
09:25:03:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 24
09:25:03:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 25
09:25:03:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 26
09:25:03:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 27
09:25:03:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 28
09:25:03:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 29
09:25:03:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 30
09:25:03:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 31
09:25:03:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
09:25:03:elinks:INFO:	Disabling clock on downlink 0
09:25:03:elinks:INFO:	Disabling clock on downlink 1
09:25:03:elinks:INFO:	Disabling clock on downlink 2
09:25:03:elinks:INFO:	Disabling clock on downlink 3
09:25:03:elinks:INFO:	Disabling clock on downlink 4
09:25:03:setup_element:INFO:	Checking SOS, encoding_mode: SOS
09:25:03:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
09:25:03:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
09:25:03:elinks:INFO:	Disabling clock on downlink 0
09:25:03:elinks:INFO:	Disabling clock on downlink 1
09:25:03:elinks:INFO:	Disabling clock on downlink 2
09:25:03:elinks:INFO:	Disabling clock on downlink 3
09:25:03:elinks:INFO:	Disabling clock on downlink 4
09:25:03:setup_element:INFO:	Checking SOS, encoding_mode: SOS
09:25:03:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [4]
09:25:03:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
==============================================OOO==============================================
09:25:03:setup_element:INFO:	Scanning clock phase
09:25:03:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
09:25:03:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
09:25:04:setup_element:INFO:	Clock phase scan results for group 0, downlink 2
09:25:04:setup_element:INFO:	Eye window for uplink 16: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
09:25:04:setup_element:INFO:	Eye window for uplink 17: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
09:25:04:setup_element:INFO:	Eye window for uplink 18: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
09:25:04:setup_element:INFO:	Eye window for uplink 19: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
09:25:04:setup_element:INFO:	Eye window for uplink 20: _____________________________________________________________________XXXXXXXXX__
Clock Delay: 33
09:25:04:setup_element:INFO:	Eye window for uplink 21: _____________________________________________________________________XXXXXXXXX__
Clock Delay: 33
09:25:04:setup_element:INFO:	Eye window for uplink 22: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
09:25:04:setup_element:INFO:	Eye window for uplink 23: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
09:25:04:setup_element:INFO:	Eye window for uplink 24: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
09:25:04:setup_element:INFO:	Eye window for uplink 25: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
09:25:04:setup_element:INFO:	Eye window for uplink 26: ____________________________________________________________________XXXXXXXXX___
Clock Delay: 32
09:25:04:setup_element:INFO:	Eye window for uplink 27: ____________________________________________________________________XXXXXXXXX___
Clock Delay: 32
09:25:04:setup_element:INFO:	Eye window for uplink 28: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
09:25:04:setup_element:INFO:	Eye window for uplink 29: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
09:25:04:setup_element:INFO:	Eye window for uplink 30: _____________________________________________________________________X__________
Clock Delay: 29
09:25:04:setup_element:INFO:	Eye window for uplink 31: _____________________________________________________________________X__________
Clock Delay: 29
09:25:04:setup_element:INFO:	Setting the clock phase to 33 for group 0, downlink 2
==============================================OOO==============================================
09:25:04:setup_element:INFO:	Scanning data phases
09:25:04:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
09:25:04:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
09:25:09:setup_element:INFO:	Data phase scan results for group 0, downlink 2
09:25:09:setup_element:INFO:	Eye window for uplink 16: XX__________________________________XXXX
Data delay found: 18
09:25:09:setup_element:INFO:	Eye window for uplink 17: __________________________________XXXXX_
Data delay found: 16
09:25:09:setup_element:INFO:	Eye window for uplink 18: XXX__________________________________XXX
Data delay found: 19
09:25:09:setup_element:INFO:	Eye window for uplink 19: X_________________________________XXXXXX
Data delay found: 17
09:25:09:setup_element:INFO:	Eye window for uplink 20: XX___________________________________XXX
Data delay found: 19
09:25:09:setup_element:INFO:	Eye window for uplink 21: X__________________________________XXXXX
Data delay found: 17
09:25:09:setup_element:INFO:	Eye window for uplink 22: XXXXX__________________________________X
Data delay found: 21
09:25:09:setup_element:INFO:	Eye window for uplink 23: XXXXXXX______________________________XXX
Data delay found: 21
09:25:09:setup_element:INFO:	Eye window for uplink 24: _________XXXXX__________________________
Data delay found: 31
09:25:09:setup_element:INFO:	Eye window for uplink 25: ___________XXXXX________________________
Data delay found: 33
09:25:09:setup_element:INFO:	Eye window for uplink 26: __________XXXX____________XXXXXXXXXXXXXX
Data delay found: 19
09:25:09:setup_element:INFO:	Eye window for uplink 27: _____________XXXXX________XXXXXXXXXXXXXX
Data delay found: 6
09:25:09:setup_element:INFO:	Eye window for uplink 28: ______________XXXXXXX___________________
Data delay found: 37
09:25:09:setup_element:INFO:	Eye window for uplink 29: ________________XXXXXXX_________________
Data delay found: 39
09:25:09:setup_element:INFO:	Eye window for uplink 30: ________________XXXXXX__________________
Data delay found: 38
09:25:09:setup_element:INFO:	Eye window for uplink 31: ________________XXXXXX__________________
Data delay found: 38
09:25:09:setup_element:INFO:	Setting the data phase to 18 for uplink 16
09:25:09:setup_element:INFO:	Setting the data phase to 16 for uplink 17
09:25:09:setup_element:INFO:	Setting the data phase to 19 for uplink 18
09:25:09:setup_element:INFO:	Setting the data phase to 17 for uplink 19
09:25:09:setup_element:INFO:	Setting the data phase to 19 for uplink 20
09:25:09:setup_element:INFO:	Setting the data phase to 17 for uplink 21
09:25:09:setup_element:INFO:	Setting the data phase to 21 for uplink 22
09:25:09:setup_element:INFO:	Setting the data phase to 21 for uplink 23
09:25:09:setup_element:INFO:	Setting the data phase to 31 for uplink 24
09:25:09:setup_element:INFO:	Setting the data phase to 33 for uplink 25
09:25:09:setup_element:INFO:	Setting the data phase to 19 for uplink 26
09:25:09:setup_element:INFO:	Setting the data phase to 6 for uplink 27
09:25:09:setup_element:INFO:	Setting the data phase to 37 for uplink 28
09:25:09:setup_element:INFO:	Setting the data phase to 39 for uplink 29
09:25:09:setup_element:INFO:	Setting the data phase to 38 for uplink 30
09:25:09:setup_element:INFO:	Setting the data phase to 38 for uplink 31
==============================================OOO==============================================
09:25:09:setup_element:INFO:	Beginning SMX ASICs map scan
09:25:09:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
09:25:09:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
09:25:09:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
09:25:09:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
09:25:09:uplink:INFO:	Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
09:25:09:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 0, uplink 23
09:25:09:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 1, uplink 22
09:25:09:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 0, uplink 30
09:25:10:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 1, uplink 31
09:25:10:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 0, uplink 21
09:25:10:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 1, uplink 20
09:25:10:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 0, uplink 28
09:25:10:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 1, uplink 29
09:25:10:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 0, uplink 19
09:25:10:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 1, uplink 18
09:25:10:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 0, uplink 26
09:25:10:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 1, uplink 27
09:25:10:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 0, uplink 17
09:25:10:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 1, uplink 16
09:25:11:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 0, uplink 24
09:25:11:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 1, uplink 25
09:25:12:ST3_emu:INFO:	
Setup Element:
  Group: 0
  Downlink: 2
  Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
  ASICs Map:
    ASIC address 0x0: (ASIC uplink, uplink): (0, 23), (1, 22)
    ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
    ASIC address 0x2: (ASIC uplink, uplink): (0, 21), (1, 20)
    ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
    ASIC address 0x4: (ASIC uplink, uplink): (0, 19), (1, 18)
    ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
    ASIC address 0x6: (ASIC uplink, uplink): (0, 17), (1, 16)
    ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
  Clock Phase Characteristic:
    Optimal Phase: 33
    Window Length: 69
    Eye Windows:
      Uplink 16: _____________________________________________________________________XXXXXXXX___
      Uplink 17: _____________________________________________________________________XXXXXXXX___
      Uplink 18: _____________________________________________________________________XXXXXXXX___
      Uplink 19: _____________________________________________________________________XXXXXXXX___
      Uplink 20: _____________________________________________________________________XXXXXXXXX__
      Uplink 21: _____________________________________________________________________XXXXXXXXX__
      Uplink 22: _____________________________________________________________________XXXXXXXX___
      Uplink 23: _____________________________________________________________________XXXXXXXX___
      Uplink 24: _____________________________________________________________________XXXXXXXX___
      Uplink 25: _____________________________________________________________________XXXXXXXX___
      Uplink 26: ____________________________________________________________________XXXXXXXXX___
      Uplink 27: ____________________________________________________________________XXXXXXXXX___
      Uplink 28: _______________________________________________________________________XXXXXXXX_
      Uplink 29: _______________________________________________________________________XXXXXXXX_
      Uplink 30: _____________________________________________________________________X__________
      Uplink 31: _____________________________________________________________________X__________
  Data phase characteristics:
    Uplink 16:
      Optimal Phase: 18
      Window Length: 34
      Eye Window: XX__________________________________XXXX
    Uplink 17:
      Optimal Phase: 16
      Window Length: 35
      Eye Window: __________________________________XXXXX_
    Uplink 18:
      Optimal Phase: 19
      Window Length: 34
      Eye Window: XXX__________________________________XXX
    Uplink 19:
      Optimal Phase: 17
      Window Length: 33
      Eye Window: X_________________________________XXXXXX
    Uplink 20:
      Optimal Phase: 19
      Window Length: 35
      Eye Window: XX___________________________________XXX
    Uplink 21:
      Optimal Phase: 17
      Window Length: 34
      Eye Window: X__________________________________XXXXX
    Uplink 22:
      Optimal Phase: 21
      Window Length: 34
      Eye Window: XXXXX__________________________________X
    Uplink 23:
      Optimal Phase: 21
      Window Length: 30
      Eye Window: XXXXXXX______________________________XXX
    Uplink 24:
      Optimal Phase: 31
      Window Length: 35
      Eye Window: _________XXXXX__________________________
    Uplink 25:
      Optimal Phase: 33
      Window Length: 35
      Eye Window: ___________XXXXX________________________
    Uplink 26:
      Optimal Phase: 19
      Window Length: 12
      Eye Window: __________XXXX____________XXXXXXXXXXXXXX
    Uplink 27:
      Optimal Phase: 6
      Window Length: 13
      Eye Window: _____________XXXXX________XXXXXXXXXXXXXX
    Uplink 28:
      Optimal Phase: 37
      Window Length: 33
      Eye Window: ______________XXXXXXX___________________
    Uplink 29:
      Optimal Phase: 39
      Window Length: 33
      Eye Window: ________________XXXXXXX_________________
    Uplink 30:
      Optimal Phase: 38
      Window Length: 34
      Eye Window: ________________XXXXXX__________________
    Uplink 31:
      Optimal Phase: 38
      Window Length: 34
      Eye Window: ________________XXXXXX__________________

==============================================OOO==============================================
09:25:12:setup_element:INFO:	Performing Elink synchronization
09:25:12:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
09:25:12:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
09:25:12:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
09:25:12:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
==============================================OOO==============================================
09:25:12:setup_element:INFO:	Writing SMX Elink masks for group 0, downlink 2
09:25:12:uplink:INFO:	Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
==============================================OOO==============================================
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
 0   | [0]  |   2   |  0  |  [23]   |    2    | [(0, 23), (1, 22)]
 1   | [0]  |   2   |  0  |  [30]   |    2    | [(0, 30), (1, 31)]
 2   | [0]  |   2   |  0  |  [21]   |    2    | [(0, 21), (1, 20)]
 3   | [0]  |   2   |  0  |  [28]   |    2    | [(0, 28), (1, 29)]
 4   | [0]  |   2   |  0  |  [19]   |    2    | [(0, 19), (1, 18)]
 5   | [0]  |   2   |  0  |  [26]   |    2    | [(0, 26), (1, 27)]
 6   | [0]  |   2   |  0  |  [17]   |    2    | [(0, 17), (1, 16)]
 7   | [0]  |   2   |  0  |  [24]   |    2    | [(0, 24), (1, 25)]
|_________________________________________________________________________|
09:25:13:febtest:INFO:	Init all SMX (CSA): 30
09:25:27:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
09:25:28:febtest:INFO:	23-00 | XA-000-09-004-012-017-016-06 |  25.1 | 1165.6
09:25:28:febtest:INFO:	30-01 | XA-000-09-004-012-015-012-04 |  28.2 | 1153.7
09:25:28:febtest:INFO:	21-02 | XA-000-09-004-012-018-015-15 |  31.4 | 1130.0
09:25:28:febtest:INFO:	28-03 | XA-000-09-004-012-014-013-09 |  21.9 | 1177.4
09:25:29:febtest:INFO:	19-04 | XA-000-09-004-012-017-015-01 |  15.6 | 1206.9
09:25:29:febtest:INFO:	26-05 | XA-000-09-004-012-013-014-07 |  15.6 | 1195.1
09:25:29:febtest:INFO:	17-06 | XA-000-09-004-012-016-015-12 |  21.9 | 1189.2
09:25:29:febtest:INFO:	24-07 | XA-000-09-004-012-015-014-04 |  18.7 | 1195.1
09:25:30:febtest:INFO:	Set all CSA to ZERO
FEB type: B FEB_A: 0 FEB_B: 1
09:25:32:ST3_smx:INFO:	chip: 23-0 	 25.062742 C 	 1177.390875 mV
09:25:32:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
09:25:32:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
09:25:32:ST3_smx:INFO:		Electrons
09:25:32:ST3_smx:INFO:	# loops 0
09:25:34:ST3_smx:INFO:	# loops 1
09:25:36:ST3_smx:INFO:	# loops 2
09:25:37:ST3_smx:INFO:	# loops 3
09:25:39:ST3_smx:INFO:	# loops 4
09:25:41:ST3_smx:INFO:	Total # of broken channels: 0
09:25:41:ST3_smx:INFO:	List of broken channels: []
09:25:41:ST3_smx:INFO:	Total # of broken channels: 0
09:25:41:ST3_smx:INFO:	List of broken channels: []
09:25:43:ST3_smx:INFO:	chip: 30-1 	 28.225000 C 	 1165.571835 mV
09:25:43:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
09:25:43:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
09:25:43:ST3_smx:INFO:		Electrons
09:25:43:ST3_smx:INFO:	# loops 0
09:25:44:ST3_smx:INFO:	# loops 1
09:25:46:ST3_smx:INFO:	# loops 2
09:25:48:ST3_smx:INFO:	# loops 3
09:25:49:ST3_smx:INFO:	# loops 4
09:25:51:ST3_smx:INFO:	Total # of broken channels: 0
09:25:51:ST3_smx:INFO:	List of broken channels: []
09:25:51:ST3_smx:INFO:	Total # of broken channels: 16
09:25:51:ST3_smx:INFO:	List of broken channels: [8, 84, 86, 88, 90, 92, 94, 98, 106, 108, 110, 114, 116, 118, 120, 124]
09:25:53:ST3_smx:INFO:	chip: 21-2 	 34.556970 C 	 1141.874115 mV
09:25:53:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
09:25:53:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
09:25:53:ST3_smx:INFO:		Electrons
09:25:53:ST3_smx:INFO:	# loops 0
09:25:55:ST3_smx:INFO:	# loops 1
09:25:56:ST3_smx:INFO:	# loops 2
09:25:58:ST3_smx:INFO:	# loops 3
09:26:00:ST3_smx:INFO:	# loops 4
09:26:01:ST3_smx:INFO:	Total # of broken channels: 0
09:26:01:ST3_smx:INFO:	List of broken channels: []
09:26:01:ST3_smx:INFO:	Total # of broken channels: 0
09:26:01:ST3_smx:INFO:	List of broken channels: []
09:26:03:ST3_smx:INFO:	chip: 28-3 	 21.902970 C 	 1195.082160 mV
09:26:03:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
09:26:03:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
09:26:03:ST3_smx:INFO:		Electrons
09:26:03:ST3_smx:INFO:	# loops 0
09:26:05:ST3_smx:INFO:	# loops 1
09:26:06:ST3_smx:INFO:	# loops 2
09:26:08:ST3_smx:INFO:	# loops 3
09:26:10:ST3_smx:INFO:	# loops 4
09:26:11:ST3_smx:INFO:	Total # of broken channels: 0
09:26:11:ST3_smx:INFO:	List of broken channels: []
09:26:11:ST3_smx:INFO:	Total # of broken channels: 0
09:26:11:ST3_smx:INFO:	List of broken channels: []
09:26:13:ST3_smx:INFO:	chip: 19-4 	 18.745682 C 	 1224.468235 mV
09:26:13:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
09:26:13:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
09:26:13:ST3_smx:INFO:		Electrons
09:26:13:ST3_smx:INFO:	# loops 0
09:26:15:ST3_smx:INFO:	# loops 1
09:26:16:ST3_smx:INFO:	# loops 2
09:26:18:ST3_smx:INFO:	# loops 3
09:26:20:ST3_smx:INFO:	# loops 4
09:26:21:ST3_smx:INFO:	Total # of broken channels: 0
09:26:21:ST3_smx:INFO:	List of broken channels: []
09:26:21:ST3_smx:INFO:	Total # of broken channels: 0
09:26:21:ST3_smx:INFO:	List of broken channels: []
09:26:23:ST3_smx:INFO:	chip: 26-5 	 18.745682 C 	 1212.728715 mV
09:26:23:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
09:26:23:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
09:26:23:ST3_smx:INFO:		Electrons
09:26:23:ST3_smx:INFO:	# loops 0
09:26:25:ST3_smx:INFO:	# loops 1
09:26:27:ST3_smx:INFO:	# loops 2
09:26:28:ST3_smx:INFO:	# loops 3
09:26:30:ST3_smx:INFO:	# loops 4
09:26:32:ST3_smx:INFO:	Total # of broken channels: 0
09:26:32:ST3_smx:INFO:	List of broken channels: []
09:26:32:ST3_smx:INFO:	Total # of broken channels: 0
09:26:32:ST3_smx:INFO:	List of broken channels: []
09:26:33:ST3_smx:INFO:	chip: 17-6 	 25.062742 C 	 1200.969315 mV
09:26:33:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
09:26:33:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
09:26:33:ST3_smx:INFO:		Electrons
09:26:33:ST3_smx:INFO:	# loops 0
09:26:35:ST3_smx:INFO:	# loops 1
09:26:37:ST3_smx:INFO:	# loops 2
09:26:38:ST3_smx:INFO:	# loops 3
09:26:40:ST3_smx:INFO:	# loops 4
09:26:42:ST3_smx:INFO:	Total # of broken channels: 0
09:26:42:ST3_smx:INFO:	List of broken channels: []
09:26:42:ST3_smx:INFO:	Total # of broken channels: 1
09:26:42:ST3_smx:INFO:	List of broken channels: [53]
09:26:43:ST3_smx:INFO:	chip: 24-7 	 21.902970 C 	 1200.969315 mV
09:26:43:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
09:26:43:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
09:26:43:ST3_smx:INFO:		Electrons
09:26:43:ST3_smx:INFO:	# loops 0
09:26:45:ST3_smx:INFO:	# loops 1
09:26:47:ST3_smx:INFO:	# loops 2
09:26:48:ST3_smx:INFO:	# loops 3
09:26:50:ST3_smx:INFO:	# loops 4
09:26:52:ST3_smx:INFO:	Total # of broken channels: 0
09:26:52:ST3_smx:INFO:	List of broken channels: []
09:26:52:ST3_smx:INFO:	Total # of broken channels: 0
09:26:52:ST3_smx:INFO:	List of broken channels: []
09:26:52:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
09:26:52:febtest:INFO:	23-00 | XA-000-09-004-012-017-016-06 |  28.2 | 1195.1
09:26:52:febtest:INFO:	30-01 | XA-000-09-004-012-015-012-04 |  31.4 | 1189.2
09:26:53:febtest:INFO:	21-02 | XA-000-09-004-012-018-015-15 |  34.6 | 1165.6
09:26:53:febtest:INFO:	28-03 | XA-000-09-004-012-014-013-09 |  21.9 | 1212.7
09:26:53:febtest:INFO:	19-04 | XA-000-09-004-012-017-015-01 |  15.6 | 1311.9
09:26:53:febtest:INFO:	26-05 | XA-000-09-004-012-013-014-07 |  18.7 | 1230.3
09:26:54:febtest:INFO:	17-06 | XA-000-09-004-012-016-015-12 |  25.1 | 1218.6
09:26:54:febtest:INFO:	24-07 | XA-000-09-004-012-015-014-04 |  21.9 | 1218.6
############################################################
#                   S U M M A R Y                          #
############################################################
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

############################################################
#                   S U M M A R Y                          #
############################################################
TEST_NAME : FEB-Sensor
TEST_DATE : 24_11_14-09_24_42
OPERATOR  : Kerstin S.; 
SITE : GSI | SETUP : GSI_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 2277| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_B
------------------------------------------------------------
SENSOR_NAME: 03192 | SIZE: 62x42 | GRADE: C
MODULE_NAME: M3DR4T0000130B2
LADDER_NAME: L3DR400013
------------------------------------------------------------
VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.4680', '1.848', '2.3620']
VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '2.0430', '1.850', '2.6180']
VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.9800', '1.850', '0.5322']