09:34:55:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
09:34:55:ST3_Shared:INFO:	                         FEB-Sensor                         
09:34:55:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
09:34:57:ST3_Shared:INFO:	STS mode selected
09:35:00:ST3_ModuleSelector:DEBUG:	M3DR4T2000132B2
09:35:00:ST3_ModuleSelector:DEBUG:	L3DR400013
09:35:00:ST3_ModuleSelector:DEBUG:	05313
09:35:00:ST3_ModuleSelector:DEBUG:	62x62
09:35:00:ST3_ModuleSelector:DEBUG:	B
09:35:00:ST3_ModuleSelector:DEBUG:	M3DR4T2000132B2
09:35:00:ST3_ModuleSelector:DEBUG:	L3DR400013
09:35:00:ST3_ModuleSelector:DEBUG:	05313
09:35:00:ST3_ModuleSelector:DEBUG:	62x62
09:35:00:ST3_ModuleSelector:DEBUG:	B
09:35:06:ST3_ModuleSelector:INFO:	M3DR4T2000132B2
09:35:06:ST3_ModuleSelector:INFO:	05313
09:35:06:febtest:INFO:	Testing FEB with SN 2281
09:35:07:smx_tester:INFO:	Scanning setup
09:35:07:elinks:INFO:	Disabling clock on downlink 0
09:35:07:elinks:INFO:	Disabling clock on downlink 1
09:35:07:elinks:INFO:	Disabling clock on downlink 2
09:35:07:elinks:INFO:	Disabling clock on downlink 3
09:35:07:elinks:INFO:	Disabling clock on downlink 4
09:35:07:setup_element:INFO:	Checking SOS, encoding_mode: SOS
09:35:07:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
09:35:07:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
09:35:07:elinks:INFO:	Disabling clock on downlink 0
09:35:07:elinks:INFO:	Disabling clock on downlink 1
09:35:07:elinks:INFO:	Disabling clock on downlink 2
09:35:07:elinks:INFO:	Disabling clock on downlink 3
09:35:07:elinks:INFO:	Disabling clock on downlink 4
09:35:08:setup_element:INFO:	Checking SOS, encoding_mode: SOS
09:35:08:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
09:35:08:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
09:35:08:elinks:INFO:	Disabling clock on downlink 0
09:35:08:elinks:INFO:	Disabling clock on downlink 1
09:35:08:elinks:INFO:	Disabling clock on downlink 2
09:35:08:elinks:INFO:	Disabling clock on downlink 3
09:35:08:elinks:INFO:	Disabling clock on downlink 4
09:35:08:setup_element:INFO:	Checking SOS, encoding_mode: SOS
09:35:08:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
09:35:08:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 16
09:35:08:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 17
09:35:08:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 18
09:35:08:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 19
09:35:08:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 20
09:35:08:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 21
09:35:08:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 22
09:35:08:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 23
09:35:08:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 24
09:35:08:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 25
09:35:08:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 26
09:35:08:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 27
09:35:08:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 28
09:35:08:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 29
09:35:08:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 30
09:35:08:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 31
09:35:08:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
09:35:08:elinks:INFO:	Disabling clock on downlink 0
09:35:08:elinks:INFO:	Disabling clock on downlink 1
09:35:08:elinks:INFO:	Disabling clock on downlink 2
09:35:08:elinks:INFO:	Disabling clock on downlink 3
09:35:08:elinks:INFO:	Disabling clock on downlink 4
09:35:08:setup_element:INFO:	Checking SOS, encoding_mode: SOS
09:35:08:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
09:35:08:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
09:35:08:elinks:INFO:	Disabling clock on downlink 0
09:35:08:elinks:INFO:	Disabling clock on downlink 1
09:35:08:elinks:INFO:	Disabling clock on downlink 2
09:35:08:elinks:INFO:	Disabling clock on downlink 3
09:35:08:elinks:INFO:	Disabling clock on downlink 4
09:35:08:setup_element:INFO:	Checking SOS, encoding_mode: SOS
09:35:08:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [4]
09:35:08:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
==============================================OOO==============================================
09:35:08:setup_element:INFO:	Scanning clock phase
09:35:08:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
09:35:08:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
09:35:09:setup_element:INFO:	Clock phase scan results for group 0, downlink 2
09:35:09:setup_element:INFO:	Eye window for uplink 16: _____________________________________________________________________XXXXXXX____
Clock Delay: 32
09:35:09:setup_element:INFO:	Eye window for uplink 17: _____________________________________________________________________XXXXXXX____
Clock Delay: 32
09:35:09:setup_element:INFO:	Eye window for uplink 18: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
09:35:09:setup_element:INFO:	Eye window for uplink 19: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
09:35:09:setup_element:INFO:	Eye window for uplink 20: ________________________________________________________________________________
Clock Delay: 40
09:35:09:setup_element:INFO:	Eye window for uplink 21: ________________________________________________________________________________
Clock Delay: 40
09:35:09:setup_element:INFO:	Eye window for uplink 22: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
09:35:09:setup_element:INFO:	Eye window for uplink 23: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
09:35:09:setup_element:INFO:	Eye window for uplink 24: ____________________________________________________________________XXXXXXXXX___
Clock Delay: 32
09:35:09:setup_element:INFO:	Eye window for uplink 25: ____________________________________________________________________XXXXXXXXX___
Clock Delay: 32
09:35:09:setup_element:INFO:	Eye window for uplink 26: ____________________________________________________________________XXXXXXX_____
Clock Delay: 31
09:35:09:setup_element:INFO:	Eye window for uplink 27: ____________________________________________________________________XXXXXXX_____
Clock Delay: 31
09:35:09:setup_element:INFO:	Eye window for uplink 28: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
09:35:09:setup_element:INFO:	Eye window for uplink 29: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
09:35:09:setup_element:INFO:	Eye window for uplink 30: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
09:35:09:setup_element:INFO:	Eye window for uplink 31: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
09:35:09:setup_element:INFO:	Setting the clock phase to 32 for group 0, downlink 2
==============================================OOO==============================================
09:35:09:setup_element:INFO:	Scanning data phases
09:35:09:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
09:35:09:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
09:35:14:setup_element:INFO:	Data phase scan results for group 0, downlink 2
09:35:14:setup_element:INFO:	Eye window for uplink 16: X___________________________________XXXX
Data delay found: 18
09:35:14:setup_element:INFO:	Eye window for uplink 17: __________________________________XXXXX_
Data delay found: 16
09:35:14:setup_element:INFO:	Eye window for uplink 18: XXXXX_________________________________XX
Data delay found: 21
09:35:14:setup_element:INFO:	Eye window for uplink 19: XXXX________________________________XXXX
Data delay found: 19
09:35:14:setup_element:INFO:	Eye window for uplink 20: XXXX__________________________________XX
Data delay found: 20
09:35:14:setup_element:INFO:	Eye window for uplink 21: XXX__________________________________XXX
Data delay found: 19
09:35:14:setup_element:INFO:	Eye window for uplink 22: XXXX__________________________________XX
Data delay found: 20
09:35:14:setup_element:INFO:	Eye window for uplink 23: XXXXXXX____________________________XXXXX
Data delay found: 20
09:35:14:setup_element:INFO:	Eye window for uplink 24: _________XXXXX__________________________
Data delay found: 31
09:35:14:setup_element:INFO:	Eye window for uplink 25: ___________XXXXX________________________
Data delay found: 33
09:35:14:setup_element:INFO:	Eye window for uplink 26: _______XXXXX____________________________
Data delay found: 29
09:35:14:setup_element:INFO:	Eye window for uplink 27: ___________XXXXX________________________
Data delay found: 33
09:35:14:setup_element:INFO:	Eye window for uplink 28: _________________XXXXX__________________
Data delay found: 39
09:35:14:setup_element:INFO:	Eye window for uplink 29: ____________________XXXXX_______________
Data delay found: 2
09:35:14:setup_element:INFO:	Eye window for uplink 30: _______________XXXXXXX__________________
Data delay found: 38
09:35:14:setup_element:INFO:	Eye window for uplink 31: _______________XXXXXXXX_________________
Data delay found: 38
09:35:14:setup_element:INFO:	Setting the data phase to 18 for uplink 16
09:35:14:setup_element:INFO:	Setting the data phase to 16 for uplink 17
09:35:14:setup_element:INFO:	Setting the data phase to 21 for uplink 18
09:35:14:setup_element:INFO:	Setting the data phase to 19 for uplink 19
09:35:14:setup_element:INFO:	Setting the data phase to 20 for uplink 20
09:35:14:setup_element:INFO:	Setting the data phase to 19 for uplink 21
09:35:14:setup_element:INFO:	Setting the data phase to 20 for uplink 22
09:35:14:setup_element:INFO:	Setting the data phase to 20 for uplink 23
09:35:14:setup_element:INFO:	Setting the data phase to 31 for uplink 24
09:35:14:setup_element:INFO:	Setting the data phase to 33 for uplink 25
09:35:14:setup_element:INFO:	Setting the data phase to 29 for uplink 26
09:35:14:setup_element:INFO:	Setting the data phase to 33 for uplink 27
09:35:14:setup_element:INFO:	Setting the data phase to 39 for uplink 28
09:35:14:setup_element:INFO:	Setting the data phase to 2 for uplink 29
09:35:14:setup_element:INFO:	Setting the data phase to 38 for uplink 30
09:35:14:setup_element:INFO:	Setting the data phase to 38 for uplink 31
==============================================OOO==============================================
09:35:14:setup_element:INFO:	Beginning SMX ASICs map scan
09:35:14:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
09:35:14:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
09:35:14:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
09:35:14:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
09:35:14:uplink:INFO:	Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
09:35:14:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 0, uplink 23
09:35:14:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 1, uplink 22
09:35:14:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 0, uplink 30
09:35:14:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 1, uplink 31
09:35:15:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 0, uplink 21
09:35:15:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 1, uplink 20
09:35:15:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 0, uplink 28
09:35:15:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 1, uplink 29
09:35:15:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 0, uplink 19
09:35:15:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 1, uplink 18
09:35:15:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 0, uplink 26
09:35:15:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 1, uplink 27
09:35:15:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 0, uplink 17
09:35:15:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 1, uplink 16
09:35:15:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 0, uplink 24
09:35:16:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 1, uplink 25
09:35:17:ST3_emu:INFO:	
Setup Element:
  Group: 0
  Downlink: 2
  Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
  ASICs Map:
    ASIC address 0x0: (ASIC uplink, uplink): (0, 23), (1, 22)
    ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
    ASIC address 0x2: (ASIC uplink, uplink): (0, 21), (1, 20)
    ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
    ASIC address 0x4: (ASIC uplink, uplink): (0, 19), (1, 18)
    ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
    ASIC address 0x6: (ASIC uplink, uplink): (0, 17), (1, 16)
    ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
  Clock Phase Characteristic:
    Optimal Phase: 32
    Window Length: 70
    Eye Windows:
      Uplink 16: _____________________________________________________________________XXXXXXX____
      Uplink 17: _____________________________________________________________________XXXXXXX____
      Uplink 18: ______________________________________________________________________XXXXXXXX__
      Uplink 19: ______________________________________________________________________XXXXXXXX__
      Uplink 20: ________________________________________________________________________________
      Uplink 21: ________________________________________________________________________________
      Uplink 22: _____________________________________________________________________XXXXXXXX___
      Uplink 23: _____________________________________________________________________XXXXXXXX___
      Uplink 24: ____________________________________________________________________XXXXXXXXX___
      Uplink 25: ____________________________________________________________________XXXXXXXXX___
      Uplink 26: ____________________________________________________________________XXXXXXX_____
      Uplink 27: ____________________________________________________________________XXXXXXX_____
      Uplink 28: ______________________________________________________________________XXXXXXXX__
      Uplink 29: ______________________________________________________________________XXXXXXXX__
      Uplink 30: ______________________________________________________________________XXXXXXXX__
      Uplink 31: ______________________________________________________________________XXXXXXXX__
  Data phase characteristics:
    Uplink 16:
      Optimal Phase: 18
      Window Length: 35
      Eye Window: X___________________________________XXXX
    Uplink 17:
      Optimal Phase: 16
      Window Length: 35
      Eye Window: __________________________________XXXXX_
    Uplink 18:
      Optimal Phase: 21
      Window Length: 33
      Eye Window: XXXXX_________________________________XX
    Uplink 19:
      Optimal Phase: 19
      Window Length: 32
      Eye Window: XXXX________________________________XXXX
    Uplink 20:
      Optimal Phase: 20
      Window Length: 34
      Eye Window: XXXX__________________________________XX
    Uplink 21:
      Optimal Phase: 19
      Window Length: 34
      Eye Window: XXX__________________________________XXX
    Uplink 22:
      Optimal Phase: 20
      Window Length: 34
      Eye Window: XXXX__________________________________XX
    Uplink 23:
      Optimal Phase: 20
      Window Length: 28
      Eye Window: XXXXXXX____________________________XXXXX
    Uplink 24:
      Optimal Phase: 31
      Window Length: 35
      Eye Window: _________XXXXX__________________________
    Uplink 25:
      Optimal Phase: 33
      Window Length: 35
      Eye Window: ___________XXXXX________________________
    Uplink 26:
      Optimal Phase: 29
      Window Length: 35
      Eye Window: _______XXXXX____________________________
    Uplink 27:
      Optimal Phase: 33
      Window Length: 35
      Eye Window: ___________XXXXX________________________
    Uplink 28:
      Optimal Phase: 39
      Window Length: 35
      Eye Window: _________________XXXXX__________________
    Uplink 29:
      Optimal Phase: 2
      Window Length: 35
      Eye Window: ____________________XXXXX_______________
    Uplink 30:
      Optimal Phase: 38
      Window Length: 33
      Eye Window: _______________XXXXXXX__________________
    Uplink 31:
      Optimal Phase: 38
      Window Length: 32
      Eye Window: _______________XXXXXXXX_________________

==============================================OOO==============================================
09:35:17:setup_element:INFO:	Performing Elink synchronization
09:35:17:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
09:35:17:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
09:35:17:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
09:35:17:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
==============================================OOO==============================================
09:35:17:setup_element:INFO:	Writing SMX Elink masks for group 0, downlink 2
09:35:17:uplink:INFO:	Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
==============================================OOO==============================================
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
 0   | [0]  |   2   |  0  |  [23]   |    2    | [(0, 23), (1, 22)]
 1   | [0]  |   2   |  0  |  [30]   |    2    | [(0, 30), (1, 31)]
 2   | [0]  |   2   |  0  |  [21]   |    2    | [(0, 21), (1, 20)]
 3   | [0]  |   2   |  0  |  [28]   |    2    | [(0, 28), (1, 29)]
 4   | [0]  |   2   |  0  |  [19]   |    2    | [(0, 19), (1, 18)]
 5   | [0]  |   2   |  0  |  [26]   |    2    | [(0, 26), (1, 27)]
 6   | [0]  |   2   |  0  |  [17]   |    2    | [(0, 17), (1, 16)]
 7   | [0]  |   2   |  0  |  [24]   |    2    | [(0, 24), (1, 25)]
|_________________________________________________________________________|
09:35:18:febtest:INFO:	Init all SMX (CSA): 30
09:35:32:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
09:35:32:febtest:INFO:	23-00 | XA-000-09-004-012-014-010-09 |  25.1 | 1159.7
09:35:33:febtest:INFO:	30-01 | XA-000-09-004-002-016-015-01 |  21.9 | 1177.4
09:35:33:febtest:INFO:	21-02 | XA-000-09-004-012-015-010-04 |  25.1 | 1165.6
09:35:33:febtest:INFO:	28-03 | XA-000-09-004-012-015-007-04 |  28.2 | 1153.7
09:35:33:febtest:INFO:	19-04 | XA-000-09-004-012-015-011-04 |  37.7 | 1135.9
09:35:33:febtest:INFO:	26-05 | XA-000-09-004-002-014-015-04 |  25.1 | 1171.5
09:35:34:febtest:INFO:	17-06 | XA-000-09-004-012-013-012-07 |  25.1 | 1177.4
09:35:34:febtest:INFO:	24-07 | XA-000-09-004-012-013-010-07 |  37.7 | 1130.0
09:35:35:febtest:INFO:	Set all CSA to ZERO
FEB type: B FEB_A: 0 FEB_B: 1
09:35:37:ST3_smx:INFO:	chip: 23-0 	 25.062742 C 	 1171.483840 mV
09:35:37:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
09:35:37:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
09:35:37:ST3_smx:INFO:		Electrons
09:35:37:ST3_smx:INFO:	# loops 0
09:35:39:ST3_smx:INFO:	# loops 1
09:35:40:ST3_smx:INFO:	# loops 2
09:35:42:ST3_smx:INFO:	# loops 3
09:35:44:ST3_smx:INFO:	# loops 4
09:35:45:ST3_smx:INFO:	Total # of broken channels: 0
09:35:45:ST3_smx:INFO:	List of broken channels: []
09:35:45:ST3_smx:INFO:	Total # of broken channels: 1
09:35:45:ST3_smx:INFO:	List of broken channels: [6]
09:35:47:ST3_smx:INFO:	chip: 30-1 	 18.745682 C 	 1189.190035 mV
09:35:47:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
09:35:47:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
09:35:47:ST3_smx:INFO:		Electrons
09:35:47:ST3_smx:INFO:	# loops 0
09:35:49:ST3_smx:INFO:	# loops 1
09:35:50:ST3_smx:INFO:	# loops 2
09:35:52:ST3_smx:INFO:	# loops 3
09:35:54:ST3_smx:INFO:	# loops 4
09:35:55:ST3_smx:INFO:	Total # of broken channels: 0
09:35:55:ST3_smx:INFO:	List of broken channels: []
09:35:55:ST3_smx:INFO:	Total # of broken channels: 0
09:35:55:ST3_smx:INFO:	List of broken channels: []
09:35:57:ST3_smx:INFO:	chip: 21-2 	 28.225000 C 	 1177.390875 mV
09:35:57:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
09:35:57:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
09:35:57:ST3_smx:INFO:		Electrons
09:35:57:ST3_smx:INFO:	# loops 0
09:35:59:ST3_smx:INFO:	# loops 1
09:36:00:ST3_smx:INFO:	# loops 2
09:36:02:ST3_smx:INFO:	# loops 3
09:36:04:ST3_smx:INFO:	# loops 4
09:36:05:ST3_smx:INFO:	Total # of broken channels: 0
09:36:05:ST3_smx:INFO:	List of broken channels: []
09:36:05:ST3_smx:INFO:	Total # of broken channels: 0
09:36:05:ST3_smx:INFO:	List of broken channels: []
09:36:07:ST3_smx:INFO:	chip: 28-3 	 28.225000 C 	 1165.571835 mV
09:36:07:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
09:36:07:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
09:36:07:ST3_smx:INFO:		Electrons
09:36:07:ST3_smx:INFO:	# loops 0
09:36:09:ST3_smx:INFO:	# loops 1
09:36:10:ST3_smx:INFO:	# loops 2
09:36:12:ST3_smx:INFO:	# loops 3
09:36:14:ST3_smx:INFO:	# loops 4
09:36:15:ST3_smx:INFO:	Total # of broken channels: 0
09:36:15:ST3_smx:INFO:	List of broken channels: []
09:36:15:ST3_smx:INFO:	Total # of broken channels: 0
09:36:15:ST3_smx:INFO:	List of broken channels: []
09:36:17:ST3_smx:INFO:	chip: 19-4 	 37.726682 C 	 1147.806000 mV
09:36:17:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
09:36:17:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
09:36:17:ST3_smx:INFO:		Electrons
09:36:17:ST3_smx:INFO:	# loops 0
09:36:19:ST3_smx:INFO:	# loops 1
09:36:20:ST3_smx:INFO:	# loops 2
09:36:22:ST3_smx:INFO:	# loops 3
09:36:23:ST3_smx:INFO:	# loops 4
09:36:25:ST3_smx:INFO:	Total # of broken channels: 0
09:36:25:ST3_smx:INFO:	List of broken channels: []
09:36:25:ST3_smx:INFO:	Total # of broken channels: 0
09:36:25:ST3_smx:INFO:	List of broken channels: []
09:36:27:ST3_smx:INFO:	chip: 26-5 	 25.062742 C 	 1183.292940 mV
09:36:27:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
09:36:27:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
09:36:27:ST3_smx:INFO:		Electrons
09:36:27:ST3_smx:INFO:	# loops 0
09:36:28:ST3_smx:INFO:	# loops 1
09:36:30:ST3_smx:INFO:	# loops 2
09:36:32:ST3_smx:INFO:	# loops 3
09:36:33:ST3_smx:INFO:	# loops 4
09:36:35:ST3_smx:INFO:	Total # of broken channels: 0
09:36:35:ST3_smx:INFO:	List of broken channels: []
09:36:35:ST3_smx:INFO:	Total # of broken channels: 0
09:36:35:ST3_smx:INFO:	List of broken channels: []
09:36:37:ST3_smx:INFO:	chip: 17-6 	 28.225000 C 	 1183.292940 mV
09:36:37:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
09:36:37:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
09:36:37:ST3_smx:INFO:		Electrons
09:36:37:ST3_smx:INFO:	# loops 0
09:36:38:ST3_smx:INFO:	# loops 1
09:36:40:ST3_smx:INFO:	# loops 2
09:36:41:ST3_smx:INFO:	# loops 3
09:36:43:ST3_smx:INFO:	# loops 4
09:36:45:ST3_smx:INFO:	Total # of broken channels: 0
09:36:45:ST3_smx:INFO:	List of broken channels: []
09:36:45:ST3_smx:INFO:	Total # of broken channels: 0
09:36:45:ST3_smx:INFO:	List of broken channels: []
09:36:46:ST3_smx:INFO:	chip: 24-7 	 37.726682 C 	 1141.874115 mV
09:36:46:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
09:36:46:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
09:36:46:ST3_smx:INFO:		Electrons
09:36:46:ST3_smx:INFO:	# loops 0
09:36:48:ST3_smx:INFO:	# loops 1
09:36:50:ST3_smx:INFO:	# loops 2
09:36:51:ST3_smx:INFO:	# loops 3
09:36:53:ST3_smx:INFO:	# loops 4
09:36:54:ST3_smx:INFO:	Total # of broken channels: 0
09:36:54:ST3_smx:INFO:	List of broken channels: []
09:36:54:ST3_smx:INFO:	Total # of broken channels: 0
09:36:54:ST3_smx:INFO:	List of broken channels: []
09:36:55:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
09:36:55:febtest:INFO:	23-00 | XA-000-09-004-012-014-010-09 |  28.2 | 1195.1
09:36:55:febtest:INFO:	30-01 | XA-000-09-004-002-016-015-01 |  21.9 | 1206.9
09:36:55:febtest:INFO:	21-02 | XA-000-09-004-012-015-010-04 |  28.2 | 1201.0
09:36:56:febtest:INFO:	28-03 | XA-000-09-004-012-015-007-04 |  28.2 | 1183.3
09:36:56:febtest:INFO:	19-04 | XA-000-09-004-012-015-011-04 |  40.9 | 1165.6
09:36:56:febtest:INFO:	26-05 | XA-000-09-004-002-014-015-04 |  28.2 | 1201.0
09:36:56:febtest:INFO:	17-06 | XA-000-09-004-012-013-012-07 |  28.2 | 1201.0
09:36:57:febtest:INFO:	24-07 | XA-000-09-004-012-013-010-07 |  40.9 | 1159.7
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

############################################################
#                   S U M M A R Y                          #
############################################################
TEST_NAME : FEB-Sensor
TEST_DATE : 24_11_27-09_34_55
OPERATOR  : Alois Alzheimer
SITE : GSI | SETUP : GSI_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 2281| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_B
AMP_MODE : STS
------------------------------------------------------------
SENSOR_NAME: 05313 | SIZE: 62x62 | GRADE: B
MODULE_NAME: M3DR4T2000132B2
LADDER_NAME: L3DR400013
------------------------------------------------------------
VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.4890', '1.848', '2.5030']
VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '2.0190', '1.849', '2.6110']
VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.9780', '1.850', '0.5244']