DTL-STS tests database

FEB_2304 05.12.24 12:36:18

link:
...SMX_0.root
link:
...SMX_2.root
link:
...SMX_4.root
link:
...SMX_6.root
link: XA-000-09-004-012-004-008-06
...SMX_1.root
link: XA-000-09-004-012-004-009-06
...SMX_3.root
link: XA-000-09-004-012-005-009-11
...SMX_5.root
link: XA-000-09-004-012-005-010-11
...SMX_7.root
link: XA-000-09-004-012-005-010-11
...VddmCSAstatus.root
Info
            12:36:18:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
12:36:18:ST3_Shared:INFO:	                       FEB-Microcable                       
12:36:18:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
12:36:20:ST3_Shared:INFO:	STS mode selected
12:36:20:febtest:INFO:	Testing FEB with SN 2304
12:36:22:smx_tester:INFO:	Scanning setup
12:36:22:elinks:INFO:	Disabling clock on downlink 0
12:36:22:elinks:INFO:	Disabling clock on downlink 1
12:36:22:elinks:INFO:	Disabling clock on downlink 2
12:36:22:elinks:INFO:	Disabling clock on downlink 3
12:36:22:elinks:INFO:	Disabling clock on downlink 4
12:36:22:setup_element:INFO:	Checking SOS, encoding_mode: SOS
12:36:22:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
12:36:22:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
12:36:22:elinks:INFO:	Disabling clock on downlink 0
12:36:22:elinks:INFO:	Disabling clock on downlink 1
12:36:22:elinks:INFO:	Disabling clock on downlink 2
12:36:22:elinks:INFO:	Disabling clock on downlink 3
12:36:22:elinks:INFO:	Disabling clock on downlink 4
12:36:22:setup_element:INFO:	Checking SOS, encoding_mode: SOS
12:36:22:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
12:36:22:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
12:36:22:elinks:INFO:	Disabling clock on downlink 0
12:36:22:elinks:INFO:	Disabling clock on downlink 1
12:36:22:elinks:INFO:	Disabling clock on downlink 2
12:36:22:elinks:INFO:	Disabling clock on downlink 3
12:36:22:elinks:INFO:	Disabling clock on downlink 4
12:36:22:setup_element:INFO:	Checking SOS, encoding_mode: SOS
12:36:22:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
12:36:22:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 24
12:36:22:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 25
12:36:22:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 26
12:36:22:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 27
12:36:22:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 28
12:36:22:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 29
12:36:22:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 30
12:36:22:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 31
12:36:22:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
12:36:22:elinks:INFO:	Disabling clock on downlink 0
12:36:22:elinks:INFO:	Disabling clock on downlink 1
12:36:22:elinks:INFO:	Disabling clock on downlink 2
12:36:22:elinks:INFO:	Disabling clock on downlink 3
12:36:22:elinks:INFO:	Disabling clock on downlink 4
12:36:22:setup_element:INFO:	Checking SOS, encoding_mode: SOS
12:36:22:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
12:36:22:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
12:36:22:elinks:INFO:	Disabling clock on downlink 0
12:36:22:elinks:INFO:	Disabling clock on downlink 1
12:36:22:elinks:INFO:	Disabling clock on downlink 2
12:36:22:elinks:INFO:	Disabling clock on downlink 3
12:36:22:elinks:INFO:	Disabling clock on downlink 4
12:36:22:setup_element:INFO:	Checking SOS, encoding_mode: SOS
12:36:22:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [4]
12:36:22:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
==============================================OOO==============================================
12:36:22:setup_element:INFO:	Scanning clock phase
12:36:22:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
12:36:22:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
12:36:23:setup_element:INFO:	Clock phase scan results for group 0, downlink 2
12:36:23:setup_element:INFO:	Eye window for uplink 24: ____________________________________________________________________XXXXXXXXX___
Clock Delay: 32
12:36:23:setup_element:INFO:	Eye window for uplink 25: ____________________________________________________________________XXXXXXXXX___
Clock Delay: 32
12:36:23:setup_element:INFO:	Eye window for uplink 26: ____________________________________________________________________XXXXXXX_____
Clock Delay: 31
12:36:23:setup_element:INFO:	Eye window for uplink 27: ____________________________________________________________________XXXXXXX_____
Clock Delay: 31
12:36:23:setup_element:INFO:	Eye window for uplink 28: ___________________________________________________________________XXXXXXXX_____
Clock Delay: 30
12:36:23:setup_element:INFO:	Eye window for uplink 29: ___________________________________________________________________XXXXXXXX_____
Clock Delay: 30
12:36:23:setup_element:INFO:	Eye window for uplink 30: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
12:36:23:setup_element:INFO:	Eye window for uplink 31: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
12:36:23:setup_element:INFO:	Setting the clock phase to 31 for group 0, downlink 2
==============================================OOO==============================================
12:36:23:setup_element:INFO:	Scanning data phases
12:36:23:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
12:36:23:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
12:36:28:setup_element:INFO:	Data phase scan results for group 0, downlink 2
12:36:28:setup_element:INFO:	Eye window for uplink 24: _________XXXXXXX________________________
Data delay found: 32
12:36:28:setup_element:INFO:	Eye window for uplink 25: ____________XXXXXX______________________
Data delay found: 34
12:36:28:setup_element:INFO:	Eye window for uplink 26: _________XXXXX__________________________
Data delay found: 31
12:36:28:setup_element:INFO:	Eye window for uplink 27: ____________XXXXXX______________________
Data delay found: 34
12:36:28:setup_element:INFO:	Eye window for uplink 28: _____________XXXXX______________________
Data delay found: 35
12:36:28:setup_element:INFO:	Eye window for uplink 29: _______________XXXXXX___________________
Data delay found: 37
12:36:28:setup_element:INFO:	Eye window for uplink 30: _________________XXXXXXX________________
Data delay found: 0
12:36:28:setup_element:INFO:	Eye window for uplink 31: _________________XXXXXXX________________
Data delay found: 0
12:36:28:setup_element:INFO:	Setting the data phase to 32 for uplink 24
12:36:28:setup_element:INFO:	Setting the data phase to 34 for uplink 25
12:36:28:setup_element:INFO:	Setting the data phase to 31 for uplink 26
12:36:28:setup_element:INFO:	Setting the data phase to 34 for uplink 27
12:36:28:setup_element:INFO:	Setting the data phase to 35 for uplink 28
12:36:28:setup_element:INFO:	Setting the data phase to 37 for uplink 29
12:36:28:setup_element:INFO:	Setting the data phase to 0 for uplink 30
12:36:28:setup_element:INFO:	Setting the data phase to 0 for uplink 31
==============================================OOO==============================================
12:36:28:setup_element:INFO:	Beginning SMX ASICs map scan
12:36:28:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
12:36:28:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
12:36:28:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
12:36:28:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
12:36:28:uplink:INFO:	Setting uplinks mask [24, 25, 26, 27, 28, 29, 30, 31]
12:36:28:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 0, uplink 30
12:36:28:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 1, uplink 31
12:36:29:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 0, uplink 28
12:36:29:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 1, uplink 29
12:36:29:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 0, uplink 26
12:36:29:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 1, uplink 27
12:36:29:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 0, uplink 24
12:36:29:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 1, uplink 25
12:36:31:ST3_emu:INFO:	
Setup Element:
  Group: 0
  Downlink: 2
  Uplinks: [24, 25, 26, 27, 28, 29, 30, 31]
  ASICs Map:
    ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
    ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
    ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
    ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
  Clock Phase Characteristic:
    Optimal Phase: 31
    Window Length: 70
    Eye Windows:
      Uplink 24: ____________________________________________________________________XXXXXXXXX___
      Uplink 25: ____________________________________________________________________XXXXXXXXX___
      Uplink 26: ____________________________________________________________________XXXXXXX_____
      Uplink 27: ____________________________________________________________________XXXXXXX_____
      Uplink 28: ___________________________________________________________________XXXXXXXX_____
      Uplink 29: ___________________________________________________________________XXXXXXXX_____
      Uplink 30: _____________________________________________________________________XXXXXXXX___
      Uplink 31: _____________________________________________________________________XXXXXXXX___
  Data phase characteristics:
    Uplink 24:
      Optimal Phase: 32
      Window Length: 33
      Eye Window: _________XXXXXXX________________________
    Uplink 25:
      Optimal Phase: 34
      Window Length: 34
      Eye Window: ____________XXXXXX______________________
    Uplink 26:
      Optimal Phase: 31
      Window Length: 35
      Eye Window: _________XXXXX__________________________
    Uplink 27:
      Optimal Phase: 34
      Window Length: 34
      Eye Window: ____________XXXXXX______________________
    Uplink 28:
      Optimal Phase: 35
      Window Length: 35
      Eye Window: _____________XXXXX______________________
    Uplink 29:
      Optimal Phase: 37
      Window Length: 34
      Eye Window: _______________XXXXXX___________________
    Uplink 30:
      Optimal Phase: 0
      Window Length: 33
      Eye Window: _________________XXXXXXX________________
    Uplink 31:
      Optimal Phase: 0
      Window Length: 33
      Eye Window: _________________XXXXXXX________________

==============================================OOO==============================================
12:36:31:setup_element:INFO:	Performing Elink synchronization
12:36:31:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
12:36:31:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
12:36:31:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
12:36:31:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
==============================================OOO==============================================
12:36:31:setup_element:INFO:	Writing SMX Elink masks for group 0, downlink 2
12:36:31:uplink:INFO:	Enabling uplinks [24, 25, 26, 27, 28, 29, 30, 31]
==============================================OOO==============================================
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
 1   | [0]  |   2   |  0  |  [30]   |    2    | [(0, 30), (1, 31)]
 3   | [0]  |   2   |  0  |  [28]   |    2    | [(0, 28), (1, 29)]
 5   | [0]  |   2   |  0  |  [26]   |    2    | [(0, 26), (1, 27)]
 7   | [0]  |   2   |  0  |  [24]   |    2    | [(0, 24), (1, 25)]
|_________________________________________________________________________|
12:36:31:febtest:INFO:	Init all SMX (CSA): 30
12:36:39:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
12:36:39:febtest:INFO:	30-01 | XA-000-09-004-012-004-008-06 |  25.1 | 1183.3
12:36:39:febtest:INFO:	28-03 | XA-000-09-004-012-004-009-06 |  31.4 | 1165.6
12:36:39:febtest:INFO:	26-05 | XA-000-09-004-012-005-009-11 |  31.4 | 1159.7
12:36:40:febtest:INFO:	24-07 | XA-000-09-004-012-005-010-11 |  31.4 | 1165.6
12:36:41:febtest:INFO:	Set all CSA to ZERO
FEB type: B FEB_A: 0 FEB_B: 1
12:36:43:ST3_smx:INFO:	chip: 30-1 	 25.062742 C 	 1195.082160 mV
12:36:43:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
12:36:43:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
12:36:43:ST3_smx:INFO:		Electrons
12:36:43:ST3_smx:INFO:	# loops 0
12:36:44:ST3_smx:INFO:	# loops 1
12:36:46:ST3_smx:INFO:	# loops 2
12:36:47:ST3_smx:INFO:	Total # of broken channels: 0
12:36:47:ST3_smx:INFO:	List of broken channels: []
12:36:47:ST3_smx:INFO:	Total # of broken channels: 0
12:36:47:ST3_smx:INFO:	List of broken channels: []
12:36:49:ST3_smx:INFO:	chip: 28-3 	 31.389742 C 	 1177.390875 mV
12:36:49:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
12:36:49:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
12:36:49:ST3_smx:INFO:		Electrons
12:36:49:ST3_smx:INFO:	# loops 0
12:36:51:ST3_smx:INFO:	# loops 1
12:36:52:ST3_smx:INFO:	# loops 2
12:36:54:ST3_smx:INFO:	Total # of broken channels: 0
12:36:54:ST3_smx:INFO:	List of broken channels: []
12:36:54:ST3_smx:INFO:	Total # of broken channels: 0
12:36:54:ST3_smx:INFO:	List of broken channels: []
12:36:55:ST3_smx:INFO:	chip: 26-5 	 34.556970 C 	 1165.571835 mV
12:36:55:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
12:36:55:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
12:36:55:ST3_smx:INFO:		Electrons
12:36:55:ST3_smx:INFO:	# loops 0
12:36:57:ST3_smx:INFO:	# loops 1
12:36:59:ST3_smx:INFO:	# loops 2
12:37:00:ST3_smx:INFO:	Total # of broken channels: 0
12:37:00:ST3_smx:INFO:	List of broken channels: []
12:37:00:ST3_smx:INFO:	Total # of broken channels: 0
12:37:00:ST3_smx:INFO:	List of broken channels: []
12:37:02:ST3_smx:INFO:	chip: 24-7 	 31.389742 C 	 1171.483840 mV
12:37:02:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
12:37:02:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
12:37:02:ST3_smx:INFO:		Electrons
12:37:02:ST3_smx:INFO:	# loops 0
12:37:04:ST3_smx:INFO:	# loops 1
12:37:05:ST3_smx:INFO:	# loops 2
12:37:07:ST3_smx:INFO:	Total # of broken channels: 1
12:37:07:ST3_smx:INFO:	List of broken channels: [122]
12:37:07:ST3_smx:INFO:	Total # of broken channels: 0
12:37:07:ST3_smx:INFO:	List of broken channels: []
12:37:07:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
12:37:07:febtest:INFO:	30-01 | XA-000-09-004-012-004-008-06 |  25.1 | 1218.6
12:37:08:febtest:INFO:	28-03 | XA-000-09-004-012-004-009-06 |  31.4 | 1201.0
12:37:08:febtest:INFO:	26-05 | XA-000-09-004-012-005-009-11 |  34.6 | 1183.3
12:37:08:febtest:INFO:	24-07 | XA-000-09-004-012-005-010-11 |  31.4 | 1189.2
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

############################################################
#                   S U M M A R Y                          #
############################################################
TEST_NAME : FEB-Microcable
TEST_DATE : 24_12_05-12_36_18
OPERATOR  : Oleksandr S.; 
SITE : GSI | SETUP : GSI_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 2304| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_B
AMP_MODE : STS
------------------------------------------------------------
------------------------------------------------------------
VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '0.6719', '1.848', '0.9484']
VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.0150', '1.850', '1.2970']
VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.0050', '1.850', '0.2658']
Comment