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FEB_2312 12.12.24 08:43:39
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08:43:39:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
08:43:39:ST3_Shared:INFO: FEB-Sensor
08:43:39:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
08:43:43:ST3_Shared:INFO: STS mode selected
08:43:49:ST3_ModuleSelector:DEBUG: M4UR1T3011313A2
08:43:49:ST3_ModuleSelector:DEBUG: L4UR101131
08:43:49:ST3_ModuleSelector:DEBUG: 03243
08:43:49:ST3_ModuleSelector:DEBUG: 62x62
08:43:49:ST3_ModuleSelector:DEBUG: A
08:43:56:ST3_ModuleSelector:DEBUG: M4UR1T0011310A2
08:43:56:ST3_ModuleSelector:DEBUG: L4UR101131
08:43:56:ST3_ModuleSelector:DEBUG: 21302
08:43:56:ST3_ModuleSelector:DEBUG: 62x42
08:43:56:ST3_ModuleSelector:DEBUG: A
08:43:56:ST3_ModuleSelector:DEBUG: M4UR1T0011310A2
08:43:56:ST3_ModuleSelector:DEBUG: L4UR101131
08:43:56:ST3_ModuleSelector:DEBUG: 21302
08:43:56:ST3_ModuleSelector:DEBUG: 62x42
08:43:56:ST3_ModuleSelector:DEBUG: A
08:44:01:ST3_ModuleSelector:INFO: M4UR1T0011310A2
08:44:01:ST3_ModuleSelector:INFO: 21302
08:44:01:febtest:INFO: Testing FEB with SN 2312
08:44:02:smx_tester:INFO: Scanning setup
08:44:02:elinks:INFO: Disabling clock on downlink 0
08:44:02:elinks:INFO: Disabling clock on downlink 1
08:44:02:elinks:INFO: Disabling clock on downlink 2
08:44:02:elinks:INFO: Disabling clock on downlink 3
08:44:02:elinks:INFO: Disabling clock on downlink 4
08:44:02:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:44:02:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
08:44:03:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:44:03:elinks:INFO: Disabling clock on downlink 0
08:44:03:elinks:INFO: Disabling clock on downlink 1
08:44:03:elinks:INFO: Disabling clock on downlink 2
08:44:03:elinks:INFO: Disabling clock on downlink 3
08:44:03:elinks:INFO: Disabling clock on downlink 4
08:44:03:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:44:03:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
08:44:03:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:44:03:elinks:INFO: Disabling clock on downlink 0
08:44:03:elinks:INFO: Disabling clock on downlink 1
08:44:03:elinks:INFO: Disabling clock on downlink 2
08:44:03:elinks:INFO: Disabling clock on downlink 3
08:44:03:elinks:INFO: Disabling clock on downlink 4
08:44:03:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:44:03:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
08:44:03:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 16
08:44:03:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 17
08:44:03:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 18
08:44:03:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 19
08:44:03:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 20
08:44:03:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 21
08:44:03:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 22
08:44:03:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 23
08:44:03:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24
08:44:03:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25
08:44:03:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26
08:44:03:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27
08:44:03:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28
08:44:03:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29
08:44:03:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30
08:44:03:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31
08:44:03:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:44:03:elinks:INFO: Disabling clock on downlink 0
08:44:03:elinks:INFO: Disabling clock on downlink 1
08:44:03:elinks:INFO: Disabling clock on downlink 2
08:44:03:elinks:INFO: Disabling clock on downlink 3
08:44:03:elinks:INFO: Disabling clock on downlink 4
08:44:03:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:44:03:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
08:44:03:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:44:03:elinks:INFO: Disabling clock on downlink 0
08:44:03:elinks:INFO: Disabling clock on downlink 1
08:44:03:elinks:INFO: Disabling clock on downlink 2
08:44:03:elinks:INFO: Disabling clock on downlink 3
08:44:03:elinks:INFO: Disabling clock on downlink 4
08:44:03:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:44:03:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
08:44:03:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
==============================================OOO==============================================
08:44:03:setup_element:INFO: Scanning clock phase
08:44:03:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
08:44:03:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
08:44:04:setup_element:INFO: Clock phase scan results for group 0, downlink 2
08:44:04:setup_element:INFO: Eye window for uplink 16: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
08:44:04:setup_element:INFO: Eye window for uplink 17: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
08:44:04:setup_element:INFO: Eye window for uplink 18: ___________________________________________________________________XXXXXXXXX____
Clock Delay: 31
08:44:04:setup_element:INFO: Eye window for uplink 19: ___________________________________________________________________XXXXXXXXX____
Clock Delay: 31
08:44:04:setup_element:INFO: Eye window for uplink 20: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
08:44:04:setup_element:INFO: Eye window for uplink 21: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
08:44:04:setup_element:INFO: Eye window for uplink 22: ________________________________________________________________________________
Clock Delay: 40
08:44:04:setup_element:INFO: Eye window for uplink 23: ________________________________________________________________________________
Clock Delay: 40
08:44:04:setup_element:INFO: Eye window for uplink 24: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
08:44:04:setup_element:INFO: Eye window for uplink 25: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
08:44:04:setup_element:INFO: Eye window for uplink 26: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
08:44:04:setup_element:INFO: Eye window for uplink 27: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
08:44:04:setup_element:INFO: Eye window for uplink 28: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
08:44:04:setup_element:INFO: Eye window for uplink 29: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
08:44:04:setup_element:INFO: Eye window for uplink 30: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
08:44:04:setup_element:INFO: Eye window for uplink 31: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
08:44:04:setup_element:INFO: Setting the clock phase to 32 for group 0, downlink 2
==============================================OOO==============================================
08:44:04:setup_element:INFO: Scanning data phases
08:44:04:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
08:44:04:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
08:44:09:setup_element:INFO: Data phase scan results for group 0, downlink 2
08:44:09:setup_element:INFO: Eye window for uplink 16: XXXX__________________________________XX
Data delay found: 20
08:44:09:setup_element:INFO: Eye window for uplink 17: XX__________________________________XXXX
Data delay found: 18
08:44:09:setup_element:INFO: Eye window for uplink 18: __________________________________XXXXX_
Data delay found: 16
08:44:09:setup_element:INFO: Eye window for uplink 19: ________________________________XXXXX___
Data delay found: 14
08:44:09:setup_element:INFO: Eye window for uplink 20: XXXX__________________________________XX
Data delay found: 20
08:44:09:setup_element:INFO: Eye window for uplink 21: XX___________________________________XXX
Data delay found: 19
08:44:09:setup_element:INFO: Eye window for uplink 22: XX__________________________________XXXX
Data delay found: 18
08:44:09:setup_element:INFO: Eye window for uplink 23: XXXXX_____________________________XXXXXX
Data delay found: 19
08:44:09:setup_element:INFO: Eye window for uplink 24: ______XXXXXX____________________________
Data delay found: 28
08:44:09:setup_element:INFO: Eye window for uplink 25: ________XXXXXX__________________________
Data delay found: 30
08:44:09:setup_element:INFO: Eye window for uplink 26: _________XXXXX__________________________
Data delay found: 31
08:44:09:setup_element:INFO: Eye window for uplink 27: _____________XXXXX______________________
Data delay found: 35
08:44:09:setup_element:INFO: Eye window for uplink 28: _______________XXXXX____________________
Data delay found: 37
08:44:09:setup_element:INFO: Eye window for uplink 29: _________________XXXXXX_________________
Data delay found: 39
08:44:09:setup_element:INFO: Eye window for uplink 30: __________________XXXXX_________________
Data delay found: 0
08:44:09:setup_element:INFO: Eye window for uplink 31: _________________XXXXXXX________________
Data delay found: 0
08:44:09:setup_element:INFO: Setting the data phase to 20 for uplink 16
08:44:09:setup_element:INFO: Setting the data phase to 18 for uplink 17
08:44:09:setup_element:INFO: Setting the data phase to 16 for uplink 18
08:44:09:setup_element:INFO: Setting the data phase to 14 for uplink 19
08:44:09:setup_element:INFO: Setting the data phase to 20 for uplink 20
08:44:09:setup_element:INFO: Setting the data phase to 19 for uplink 21
08:44:09:setup_element:INFO: Setting the data phase to 18 for uplink 22
08:44:09:setup_element:INFO: Setting the data phase to 19 for uplink 23
08:44:09:setup_element:INFO: Setting the data phase to 28 for uplink 24
08:44:09:setup_element:INFO: Setting the data phase to 30 for uplink 25
08:44:09:setup_element:INFO: Setting the data phase to 31 for uplink 26
08:44:09:setup_element:INFO: Setting the data phase to 35 for uplink 27
08:44:09:setup_element:INFO: Setting the data phase to 37 for uplink 28
08:44:09:setup_element:INFO: Setting the data phase to 39 for uplink 29
08:44:09:setup_element:INFO: Setting the data phase to 0 for uplink 30
08:44:09:setup_element:INFO: Setting the data phase to 0 for uplink 31
==============================================OOO==============================================
08:44:09:setup_element:INFO: Beginning SMX ASICs map scan
08:44:09:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
08:44:09:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
08:44:09:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
08:44:09:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
08:44:09:uplink:INFO: Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
08:44:10:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 23
08:44:10:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 22
08:44:10:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 30
08:44:10:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 31
08:44:10:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 21
08:44:10:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 20
08:44:10:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28
08:44:10:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 29
08:44:10:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 19
08:44:10:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 18
08:44:10:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26
08:44:10:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 27
08:44:11:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 17
08:44:11:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 16
08:44:11:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 24
08:44:11:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 25
08:44:12:ST3_emu:INFO:
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 23), (1, 22)
ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
ASIC address 0x2: (ASIC uplink, uplink): (0, 21), (1, 20)
ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
ASIC address 0x4: (ASIC uplink, uplink): (0, 19), (1, 18)
ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
ASIC address 0x6: (ASIC uplink, uplink): (0, 17), (1, 16)
ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
Clock Phase Characteristic:
Optimal Phase: 32
Window Length: 69
Eye Windows:
Uplink 16: _______________________________________________________________________XXXXXXX__
Uplink 17: _______________________________________________________________________XXXXXXX__
Uplink 18: ___________________________________________________________________XXXXXXXXX____
Uplink 19: ___________________________________________________________________XXXXXXXXX____
Uplink 20: _____________________________________________________________________XXXXXXXX___
Uplink 21: _____________________________________________________________________XXXXXXXX___
Uplink 22: ________________________________________________________________________________
Uplink 23: ________________________________________________________________________________
Uplink 24: ____________________________________________________________________XXXXXXXX____
Uplink 25: ____________________________________________________________________XXXXXXXX____
Uplink 26: ____________________________________________________________________XXXXXXXX____
Uplink 27: ____________________________________________________________________XXXXXXXX____
Uplink 28: _____________________________________________________________________XXXXXXXX___
Uplink 29: _____________________________________________________________________XXXXXXXX___
Uplink 30: ______________________________________________________________________XXXXXXXX__
Uplink 31: ______________________________________________________________________XXXXXXXX__
Data phase characteristics:
Uplink 16:
Optimal Phase: 20
Window Length: 34
Eye Window: XXXX__________________________________XX
Uplink 17:
Optimal Phase: 18
Window Length: 34
Eye Window: XX__________________________________XXXX
Uplink 18:
Optimal Phase: 16
Window Length: 35
Eye Window: __________________________________XXXXX_
Uplink 19:
Optimal Phase: 14
Window Length: 35
Eye Window: ________________________________XXXXX___
Uplink 20:
Optimal Phase: 20
Window Length: 34
Eye Window: XXXX__________________________________XX
Uplink 21:
Optimal Phase: 19
Window Length: 35
Eye Window: XX___________________________________XXX
Uplink 22:
Optimal Phase: 18
Window Length: 34
Eye Window: XX__________________________________XXXX
Uplink 23:
Optimal Phase: 19
Window Length: 29
Eye Window: XXXXX_____________________________XXXXXX
Uplink 24:
Optimal Phase: 28
Window Length: 34
Eye Window: ______XXXXXX____________________________
Uplink 25:
Optimal Phase: 30
Window Length: 34
Eye Window: ________XXXXXX__________________________
Uplink 26:
Optimal Phase: 31
Window Length: 35
Eye Window: _________XXXXX__________________________
Uplink 27:
Optimal Phase: 35
Window Length: 35
Eye Window: _____________XXXXX______________________
Uplink 28:
Optimal Phase: 37
Window Length: 35
Eye Window: _______________XXXXX____________________
Uplink 29:
Optimal Phase: 39
Window Length: 34
Eye Window: _________________XXXXXX_________________
Uplink 30:
Optimal Phase: 0
Window Length: 35
Eye Window: __________________XXXXX_________________
Uplink 31:
Optimal Phase: 0
Window Length: 33
Eye Window: _________________XXXXXXX________________
==============================================OOO==============================================
08:44:12:setup_element:INFO: Performing Elink synchronization
08:44:12:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
08:44:12:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
08:44:12:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
08:44:12:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
==============================================OOO==============================================
08:44:12:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2
08:44:12:uplink:INFO: Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
==============================================OOO==============================================
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
0 | [0] | 2 | 0 | [23] | 2 | [(0, 23), (1, 22)]
1 | [0] | 2 | 0 | [30] | 2 | [(0, 30), (1, 31)]
2 | [0] | 2 | 0 | [21] | 2 | [(0, 21), (1, 20)]
3 | [0] | 2 | 0 | [28] | 2 | [(0, 28), (1, 29)]
4 | [0] | 2 | 0 | [19] | 2 | [(0, 19), (1, 18)]
5 | [0] | 2 | 0 | [26] | 2 | [(0, 26), (1, 27)]
6 | [0] | 2 | 0 | [17] | 2 | [(0, 17), (1, 16)]
7 | [0] | 2 | 0 | [24] | 2 | [(0, 24), (1, 25)]
|_________________________________________________________________________|
08:44:13:febtest:INFO: Init all SMX (CSA): 30
08:44:27:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
08:44:28:febtest:INFO: 23-00 | XA-000-09-004-012-008-013-12 | 34.6 | 1171.5
08:44:28:febtest:INFO: 30-01 | XA-000-09-004-012-007-014-08 | 28.2 | 1171.5
08:44:28:febtest:INFO: 21-02 | XA-000-09-004-012-004-010-06 | 31.4 | 1171.5
08:44:28:febtest:INFO: 28-03 | XA-000-09-004-012-009-017-06 | 34.6 | 1159.7
08:44:28:febtest:INFO: 19-04 | XA-000-09-004-012-008-012-12 | 31.4 | 1171.5
08:44:29:febtest:INFO: 26-05 | XA-000-09-004-012-008-014-12 | 47.3 | 1112.1
08:44:29:febtest:INFO: 17-06 | XA-000-09-004-012-005-011-11 | 31.4 | 1212.7
08:44:29:febtest:INFO: 24-07 | XA-000-09-004-012-007-012-08 | 31.4 | 1171.5
08:44:30:febtest:INFO: Set all CSA to ZERO
FEB type: B FEB_A: 0 FEB_B: 1
08:44:32:ST3_smx:INFO: chip: 23-0 34.556970 C 1177.390875 mV
08:44:32:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:44:32:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:44:32:ST3_smx:INFO: Electrons
08:44:32:ST3_smx:INFO: # loops 0
08:44:34:ST3_smx:INFO: # loops 1
08:44:36:ST3_smx:INFO: # loops 2
08:44:37:ST3_smx:INFO: # loops 3
08:44:39:ST3_smx:INFO: # loops 4
08:44:40:ST3_smx:INFO: Total # of broken channels: 0
08:44:40:ST3_smx:INFO: List of broken channels: []
08:44:40:ST3_smx:INFO: Total # of broken channels: 0
08:44:40:ST3_smx:INFO: List of broken channels: []
08:44:42:ST3_smx:INFO: chip: 30-1 28.225000 C 1183.292940 mV
08:44:42:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:44:42:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:44:42:ST3_smx:INFO: Electrons
08:44:42:ST3_smx:INFO: # loops 0
08:44:44:ST3_smx:INFO: # loops 1
08:44:45:ST3_smx:INFO: # loops 2
08:44:47:ST3_smx:INFO: # loops 3
08:44:49:ST3_smx:INFO: # loops 4
08:44:50:ST3_smx:INFO: Total # of broken channels: 0
08:44:50:ST3_smx:INFO: List of broken channels: []
08:44:50:ST3_smx:INFO: Total # of broken channels: 3
08:44:50:ST3_smx:INFO: List of broken channels: [0, 1, 35]
08:44:52:ST3_smx:INFO: chip: 21-2 31.389742 C 1183.292940 mV
08:44:52:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:44:52:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:44:52:ST3_smx:INFO: Electrons
08:44:52:ST3_smx:INFO: # loops 0
08:44:54:ST3_smx:INFO: # loops 1
08:44:55:ST3_smx:INFO: # loops 2
08:44:57:ST3_smx:INFO: # loops 3
08:44:59:ST3_smx:INFO: # loops 4
08:45:00:ST3_smx:INFO: Total # of broken channels: 0
08:45:00:ST3_smx:INFO: List of broken channels: []
08:45:00:ST3_smx:INFO: Total # of broken channels: 0
08:45:00:ST3_smx:INFO: List of broken channels: []
08:45:02:ST3_smx:INFO: chip: 28-3 34.556970 C 1165.571835 mV
08:45:02:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:45:02:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:45:02:ST3_smx:INFO: Electrons
08:45:02:ST3_smx:INFO: # loops 0
08:45:04:ST3_smx:INFO: # loops 1
08:45:05:ST3_smx:INFO: # loops 2
08:45:07:ST3_smx:INFO: # loops 3
08:45:09:ST3_smx:INFO: # loops 4
08:45:10:ST3_smx:INFO: Total # of broken channels: 0
08:45:10:ST3_smx:INFO: List of broken channels: []
08:45:10:ST3_smx:INFO: Total # of broken channels: 0
08:45:10:ST3_smx:INFO: List of broken channels: []
08:45:12:ST3_smx:INFO: chip: 19-4 31.389742 C 1183.292940 mV
08:45:12:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:45:12:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:45:12:ST3_smx:INFO: Electrons
08:45:12:ST3_smx:INFO: # loops 0
08:45:14:ST3_smx:INFO: # loops 1
08:45:15:ST3_smx:INFO: # loops 2
08:45:17:ST3_smx:INFO: # loops 3
08:45:18:ST3_smx:INFO: # loops 4
08:45:20:ST3_smx:INFO: Total # of broken channels: 0
08:45:20:ST3_smx:INFO: List of broken channels: []
08:45:20:ST3_smx:INFO: Total # of broken channels: 1
08:45:20:ST3_smx:INFO: List of broken channels: [4]
08:45:22:ST3_smx:INFO: chip: 26-5 47.250730 C 1124.048640 mV
08:45:22:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:45:22:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:45:22:ST3_smx:INFO: Electrons
08:45:22:ST3_smx:INFO: # loops 0
08:45:23:ST3_smx:INFO: # loops 1
08:45:25:ST3_smx:INFO: # loops 2
08:45:27:ST3_smx:INFO: # loops 3
08:45:28:ST3_smx:INFO: # loops 4
08:45:30:ST3_smx:INFO: Total # of broken channels: 0
08:45:30:ST3_smx:INFO: List of broken channels: []
08:45:30:ST3_smx:INFO: Total # of broken channels: 0
08:45:30:ST3_smx:INFO: List of broken channels: []
08:45:32:ST3_smx:INFO: chip: 17-6 31.389742 C 1247.887635 mV
08:45:32:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:45:32:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:45:32:ST3_smx:INFO: Electrons
08:45:32:ST3_smx:INFO: # loops 0
08:45:33:ST3_smx:INFO: # loops 1
08:45:35:ST3_smx:INFO: # loops 2
08:45:37:ST3_smx:INFO: # loops 3
08:45:38:ST3_smx:INFO: # loops 4
08:45:40:ST3_smx:INFO: Total # of broken channels: 0
08:45:40:ST3_smx:INFO: List of broken channels: []
08:45:40:ST3_smx:INFO: Total # of broken channels: 0
08:45:40:ST3_smx:INFO: List of broken channels: []
08:45:41:ST3_smx:INFO: chip: 24-7 31.389742 C 1183.292940 mV
08:45:41:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:45:41:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:45:41:ST3_smx:INFO: Electrons
08:45:41:ST3_smx:INFO: # loops 0
08:45:43:ST3_smx:INFO: # loops 1
08:45:45:ST3_smx:INFO: # loops 2
08:45:46:ST3_smx:INFO: # loops 3
08:45:48:ST3_smx:INFO: # loops 4
08:45:49:ST3_smx:INFO: Total # of broken channels: 0
08:45:49:ST3_smx:INFO: List of broken channels: []
08:45:49:ST3_smx:INFO: Total # of broken channels: 0
08:45:49:ST3_smx:INFO: List of broken channels: []
08:45:50:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
08:45:50:febtest:INFO: 23-00 | XA-000-09-004-012-008-013-12 | 37.7 | 1201.0
08:45:50:febtest:INFO: 30-01 | XA-000-09-004-012-007-014-08 | 28.2 | 1206.9
08:45:50:febtest:INFO: 21-02 | XA-000-09-004-012-004-010-06 | 34.6 | 1206.9
08:45:51:febtest:INFO: 28-03 | XA-000-09-004-012-009-017-06 | 34.6 | 1189.2
08:45:51:febtest:INFO: 19-04 | XA-000-09-004-012-008-012-12 | 34.6 | 1201.0
08:45:51:febtest:INFO: 26-05 | XA-000-09-004-012-008-014-12 | 47.3 | 1147.8
08:45:51:febtest:INFO: 17-06 | XA-000-09-004-012-005-011-11 | 31.4 | 1522.7
08:45:51:febtest:INFO: 24-07 | XA-000-09-004-012-007-012-08 | 31.4 | 1201.0
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-Sensor
TEST_DATE : 24_12_12-08_43_39
OPERATOR : Kerstin S.;
SITE : GSI | SETUP : GSI_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 2312| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_B
AMP_MODE : STS
------------------------------------------------------------
SENSOR_NAME: 21302 | SIZE: 62x42 | GRADE: A
MODULE_NAME: M4UR1T0011310A2
LADDER_NAME: L4UR101131
------------------------------------------------------------
VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.5020', '1.848', '1.9230']
VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '2.0470', '1.850', '2.5840']
VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.9930', '1.850', '0.5358']